双向可控硅整流器中英文对照外文翻译文献

双向可控硅整流器中英文对照外文翻译文献双向可控硅整流器中英文对照外文翻译文献(文档含英文原文和中文翻译)原文：InvestigationonBi-directionalSCRESDProtectionDevicesina0.18μmRFCMOSProcessAbstract:Basedonthebi-directionalsiliconcontrolledrectifier(SCR),twonovelelectrostaticdischarge(ESD)protectiondeviceshavebeenproposed,whichcanpreventESDstressesonboththepositiveandthenegativedirections.Whiletheconventionaldual-directionSCRESDprotectiondeviceisusuallytriggeredbytheavalanchebreakdownbetweenN-wellandP-well,thetwoproposeddevicesusetheembeddedNMOS/PMOSasthetriggeringstructuretodecreasethetriggervoltage.Boththemodifiedstructuresareimplementedina0.18μmRFCMOSprocessandexaminedbythetransmissionlinepulsetestingsystem.Experimentalresultsindicatethattheproposeddeviceshavelowertriggervoltage,smallerleakagecurrent(～nA),aprotectionlevelpassing2kVofhumanbodymodel,andahighholdingvoltage(>3.3V),makingthemimmunetothelatch-upin1.8Vor3.3VI/OESDprotectionapplications.IntroductionElectrostaticdischarge(ESD)hasbecomeoneofthemostseriousreliabilityconcernsincurrentintegratedcircuits(ICs).Withthecontinuousdecreasingofdevicesizeandincreasingofcircuitcomplexity,modernICsaremoresusceptibletoESDstress.ProvidingadequateESDprotectionforICshasthusbecomeanimportantandchallengingtask.TraditionalESDsnapbackprotectiondevicessuchasthebipolarjunctiontransistor(BJT),thegrounded-gateNMOS(GGNMOS),andthelowtriggeringvoltagesiliconcontrolledrectifier(SCR),canusuallyprotectcircuitsinonedirection.TheyprovideaforwardcurrentshuntpathforthepositiveESDstress,andrelyonthebodydiodeprotectingagainstthenegativeESDstress.However,itisalsonecessarytohavethedual-directionalprotectioncapabilityforESDprotectiondevicesusedinsomecircuits,suchasthecolumndriversinliquidcrystaldisplays,RFinputs,interfaceapplicationsanddigital-analogconverters.Themostarea-efficientESDprotectionsolutionisthedual-directionsiliconcontrolledrectifier(DDSCR),whichcanformthesnapbackintwodirectionstoprotectagainstboththepositiveandnegativestresses.Unfortunately,thetriggervoltageofDDSCRisquitehighduetoitsinherenttriggeringmechanism.Forexample,sincethebreakdownvoltageofgateoxideislessthan20Vinthe0.18μmCMOSprocess,atriggervoltageashighasabout15VmakesDDSCRinappropriatetoprovidetheeffectiveESDprotectionformodernICcores.Toreducethetriggervoltage,twonewdevicesbasedonDDSCRaredevelopedandrealizedinthe0.18μmRFCMOSprocessinthispaper.Thetransmissionlinepulse(TLP)testingresultsindicatethattheimproveddevicespossesslowertriggervoltageandsmallerleakagecurrent.1ConventionalDDSCRThecross-sectionofaconventionalDDSCRcontainingtwoembeddedsymmetricalSCRs(SCR1andSCR2)isshowninFig.1.WhenapositiveESDstressisappliedtotheTerminal1,theparasitictransistorT2isoffduetothereverselybiasedN-well/P-well.WhentheESDstressreachestheavalanchebreakdownvoltageofN-well/P-well,significantelectron-holepairsaregenerated.ThecurrentflowsfromtheN-welltotheP-well,andtheparasiticresistanceR4inthecurrentpathresultsinanelectricalpotentialdrop,helpingthebasejunctionofthetransistorT3buildupthepotential.Whenthispotentialisgreaterthan0.7V,T3isturnedon.ThenSCR1issuccessfullytriggeredwiththepositive-feedbackregenerationanddrivenintothedeepsnapbackregionwithalowholdingvoltage.Anactivedischargingpathwithlowimpendenceisformedtoshuntthehugecurrentintheforwarddirection,andtheI/OPADvoltageisclampedtoalowlevel.WhenanegativeESDstressisappliedtotheTerminal1,SCR2istriggeredsimilarlyasSCR1.DDSCRisoffwhenthecircuitworksundernormalconditions.SoDDSCRcanprovidedual-directionalprotection,andpossesssnapbackcharacteristicsagainstboththepositiveandnegativeESDstresses.Fig.1CrosssectionofconventionalDDSCR2NMOS/PMOSModifiedDDSCRs2.1NMOSModifiedDDSCRThetriggervoltageofaconventionalDDSCRisbasicallydeterminedbytheavalanchebreakdownvoltageofN-well/P-well,whichisusuallytoohightopreventESDdamagewithathingateoxideinthe0.18μmRFCMOSprocess.Thetriggeringvoltagecanbereducedsignificantlybychangingthetriggeringmechanism.Inthispaper,weproposeanNMOS-modifiedDDSCR(NMDDSCR)toreducethetriggeringvoltage,asshowninFig.2,whereextramask,T-well,isusedtoisolateNMOSfromthesubstratebiasconditionintheRFCMOSprocess.WhenapositiveESDstressisappliedtotheTerminal1,thechannelinversionregionofNMOS1canbeformed.ThelargecurrentcanthenpassthroughthechannelofNMOS1toNMOS2,andNMOS1servesasaresistor.TheGGNMOSconsistingofNMOS2isthetriggeringcomponentofthisproposeddevice.Asaresult,thetriggervoltageisdecreasedtoabout7Vinthe0.18μmRFCMOSprocess,muchlowerthanthatofaconventionalDDSCR.Fig.2CrosssectionofNMDDSCRWhentheGGNMOSisturnedon,theSCRconsistingofT1andT2istriggered.AlowresistancepathisthenformedtoshuntthehugecurrentandprovideaclampforI/OPAD.WhenanegativeESDisappliedtotheTerminal1,NMDDSCRcanbetriggeredinthesamewayduetoitssymmetricstructure.NMDDSCRisoffwhenthecircuitworksundernormalconditions.Accordingtotheaboveanalysis,thetriggervoltageofNMDDSCRismainlydeterminedbythatoftheembeddedGGNMOS.ThetriggeringmodehaschangedfromtheavalanchebreakdownbetweenN-well/P-welltothatbetweenQUOTE/T-well.Theessenceofthisapproachismodifyingthedopingconcentrationdifferenceoftheavalanchebreakdowninterfacetoadjustthetriggervoltage.2.2PMOSModifiedDDSCRThePMOSmodifiedDDSCR(PMDDSCR)workssimilarlyastheNMDDSCR.WhenapositiveESDstressisappliedtotheTerminallofPMDDSCRshowninFig.3,PMOS1isoffduetothehighgatepotential,guaranteeingPMDDSCRtobeoffwhenthecircuitworksundernormalconditions.TheparasiticlateralPNPtransistorofPMOStakeschargeofthetriggeringofthewholedevice,similartotheroleofGGNMOSplayinginNMDDSCR.WhentheESDstressisincreasedtoreachtheavalanchebreakdownvoltageofN-well/QUOTEinPMOS1,thetransistorT2isturnedon.Subsequently,theSCRconsistingofT1andT2istriggered,andalowresistancepathisformedtoshuntthehugecurrent.SothetriggervoltageofPMDDSCRisalsoeffectivelyreducedbychangingtheconcentrationoftheavalanchebreakdowninterface,havingasimilartriggeringmechanismtoNMDDSCR.Fig.3CrosssectionofPMDDSCR3ResultsandDiscussionBothNMOSandPMOSmodifiedDDSCRdeviceswithawidthof40μmarefabricatedinthe0.18μmRFCMOSprocess,andmeasuredbytheTLPtestingsystem(ModelBARTH4002).Thetestpulsewidthandtherisetimeare100nsand10ns,respectively.Themeasurementwindowissetfrom70%to90%ofthepulse,andtheincrementvoltageis0.5V.Whentheleakagecurrentofthetesteddeviceismorethan1μAataDCbiasof2V,itisconsideredfailed.SincethetriggervoltageofGGNMOSdecreaseslightlywithdecreasingchannellengthoftheembeddedNMOS(QUOTE)bydecreasingthebasewidthoftheparasiticNPNtransistor,QUOTEischosentobe0.2μminthedesignedNMDDSCRstructures,whichisalmosttheminimumchannellengthina0.18μmRFCMOSprocess.TheTLPtestedI-VcurvesofNMDDSCRswiththreedifferentQUOTElengths(QUOTE)arepresentedinFig.4.Thetriggervoltage(QUOTE)isbelow7V,whichisveryclosetothetriggervoltageofGGNMOSinthe0.18μmCMOSprocess,suggestingthatthetriggeringofNMDDSCRreliesbasicallyontheGGNMOS.Theholdingvoltage(QUOTE)ofNMDDSCRislargerthan5V,guaranteeingthatnolatch-upissuehappens.Inaddition,theleakagecurrentoftheseNMDDSCRsisverylow(～nA),asshowninFig.4.Fig.4TLPtestedI-VcurvesandleakagecurrentofNMDDSCRswiththreedifferentQUOTElengthsAsthekeysizeofNMDDSCR,QUOTEaffectstheESDprotectionlevel.AccordingtotheI-VcurvesshowninFig.4,thesecondarybreakdowncurrent(QUOTE)decreaseswithincreasingQUOTEduetotheincreasingcurrentpath.Thelongercurrentpathleadstothegreateron-resistance,andhencethelowerprotectionlevel.Furthermore,theturn-onspeedofNMDDSCRdecreaseswithincreasingcurrentpath.Toohighholdingvoltageandon-resistancearemaindrawbacksofNMDDSCR,whichdeteriorateQUOTE.SotheprotectionlevelofsingleNMDDSCRisjustover2kVofHumanBodyModel.Themulti-fingerstructureNMDDSCRcanbeadoptedtoreducetheon-resistancefortheI/OESDprotectionapplications,althoughthechipareahastobesacrificed.TheTLPtestingresultsofPMDDSCRswiththreedifferentchannellengthsoftheembeddedPMOS(QUOTE)areshowninFig.5,wheretheQUOTElengthofPMDDSCR(QUOTE)isfixedtobeareasonablevalueof2.5μm.Thetriggervoltageisabout8V,increasingslightlywithincreasingQUOTE.SimilarlytoNMDDSCRs,theleakagecurrentofthefabricatedPMDDSCRsisalsoverylow(～nA),asshowninFig.5Fig.5TLPtestedI-VcurvesandleakagecurrentofPMDDSCRswiththreedifferentchannellengthsoftheembeddedPMOSComparedtotheNMDDSCR,thePMDDSCRhashigherprotectionlevelwhichcanreach3kVofhumanbodymodel,butthetriggervoltageofPMDDSCRishigher.Thehighholdingvoltage(exceeding3.3V)andthelowleakagecurrent(～nA)makePMDDSCRmoresuitableforthe1.8Vand3.3VI/OESDprotectionapplications.Similarly,therelativelyhighon-resistancemayalsolimittheprotectionlevelofPMDDSCR.ESDcharacteristicsofthefabricatedNMDDSCRandPMDDSCRsamplesaresummarizedinTable1andTable2forcomparison,whereQUOTEistheholdingcurrentandQUOTEisthesecondarybreakdownvoltage.4ConclusionsTwoimprovedbi-directionalSCRESDprotectiondevices,featuringlowtriggervoltage,smallleakagecurrentandfastturn-onspeed,aredesignedandfabricatedinthe0.18μmRFCMOSprocess.ThetriggervoltageofNMDDSCRandPMDDSCRisbelow7Vandaround8V,respectively,andtheESDprotectionlevelofsingleNMDDSCRandPMDDSCRreaches2kVand3kVofHumanBodyModel,respectively.Boththeproposedstructuresareimmunetolatch-upfor1.8Vand3.3VI/OESDprotectionapplications.译文：0.18mRFCMOS双向可控硅ESD防护器件的研究摘要：基于双向可控硅整流器（SCR），两个新的静电放电（ESD）保护装置已被提出，它可以防止ESD应力同时作用在正负方向。而常规的双向可控硅ESD保护器件通常是由分解N阱与P阱之间的崩落触发的，两个被提出的的设备使用的是嵌入式的NMOS/PMOS作为触发结构以降低触发电压。两种改性结构被实现在一个0.18微米的射频CMOS工艺并由传输线路脉冲检测系统检查。实验结果表明，所提出的器件具有较低的触发电压，较小的漏电流（〜NA），对人体模型的保护级别传递2kV的电压，和高的保持电压（>3.3V），使它们的免疫闭锁在1.8V或3.3V的I/OESD保护应用中。介绍：静电放电（ESD）已成为当前集成电路（IC）的最严重的可靠性问题之一。随着不断的减小设备尺寸和增加电路复杂性，现代集成电路更容易受到ESD应力。因此提供足够的IC的ESD保护已成为重要并具有挑战性的任务。传统的ESD折返保护装置，例如双极结型晶体管（BJT），接地栅NMOS（GGNMOS），以及低电压触发的硅可控整流器（SCR），通常可以保护线路的一个方向。他们为正的ESD应力提供了一个正向电流分路，并且依靠体二极管防止负的ESD应力。然而，一些电路中也是有必要使用ESD保护装置的双向保护能力，如列驱动液晶显示器，RF输入、界面应用程序和数字模拟转换器。最有效的ESD保护方案运用最多的是双向可控硅整流器（DDSCR），它可以在两个方向上形成折返保护，以防止二者正负应力。不幸的是，DDSCR的触发电压大部分是由于其固有的触发机制。例如，由于栅极氧化物的击穿电压在0.18微米CMOS工艺中小于20V，触发电压高约15V，使DDSCR不合适提供现代集成电路芯的有效ESD保护。在本文中，为了降低触发电压，基于DDSCR的两款新设备在0.18微米的射频CMOS工艺中实现并发展。传输线脉冲（TLP）的测试结果表明，该改进的设备具有更低的触发电压和更小的漏电流。1、传统DDSCR含两个嵌入式对称的SCR（SCR1和SCR2）的常规DDSCR的横截面示于图1。当ESD的正应力被施加到接线1，由于N阱/P阱反向偏置，寄生晶体管T2关断。当ESD应力达到的N阱/P阱的击穿电压时，产生显著电子-空穴对。电流从N阱流到P阱，并且流过寄生电阻R4，产生电势降，帮助晶体管T3的基极结建立电位。当该电位大于0.7V时，T3被导通。然后SCR1被成功地触发正向再生反馈且驱动到深折返区域后具有低的保持电压。具有低阻抗的有源放电路径在向前的方向形成为分流巨大的电流，并且I/O焊盘的电压被钳位到一个较低的水平。当负ESD的正应力被施加到接线1，SCR2被类似地触发为SCR1。当电路正常条件下工作时，DVDSCR是关闭的。所以DVDSCR可以提供双定向保护，并具有对两者正负ESD应力的折返特性。图1传统DDSCR断面2NMOS/PMOS修改DDSCRs2.1NMOS修改DDSCR常规DDSCR的触发电压基本上由N阱/P阱的击穿电压确定，这在0.18微米的RFC工艺通常很高，以防止ESD的薄栅氧化层损坏。触发电压可以通过改变触发机构被显著地降低。在本文中，我们提出了一个NMOS改性DDSCR（NMDDSCR），以减少在触发电压，如图2所示，其中，额外的掩模，T型阱，被用在RFCMOS工艺的衬底偏置条件隔离的NMOS流程。当正ESD应力被施加到接线1，可以形成NMOS1的流路反型区。大的电流可通过NMOS1的通道传递给NMOS2，并且NMOS1用作电阻。组成GGNMOS的NMOS2是本文提出的装置的触发组件。结果，在0.18微米的RFCMOS工艺中该触发电压降低到约7V，比传统的DDSCR的要低得多。图2NMDDSCR截面当GGNMOS接通时，可控硅的T1和T2被触发。以旁路巨大的电流形成一个低电阻通路并且提供了一个钳位的I/O焊盘。当负ESD被施加到接线1，由于其对称结构NMDDSCR可以以同样的方式触发，当电路正常条件下工作时，NMDDSCR是关闭的。根据以上分析，NMDDSCR的触发电压主要由嵌入式GGNMOS决定。触发模式已经从N阱/P阱雪崩击穿改变到QUOTE/T阱。这种方法的本质是修改雪崩击穿界面的掺杂浓度差来调整触发电压。2.2PMOS修改DDSCRPMOS修改DDSCR（PMDDSCR）的工作方式类似于NMDDSCR。当正ESD应力施加PMDDSCR的接线1，如图3所示，由于高栅电位，PMOS1是关闭的，保证PMDDSCR被关闭时，电路是在正常条件下工作的。PMOS的寄生横向PNP晶体管负责整个设备的触发，类似于GGNMOS在NMDDSCR中扮演的角色。当ESD应力在PMOS1中增加而达到N阱/QUOTE的雪崩击穿电压时，晶体管T2被导通。随后，可控硅组成的T1和T2被触发，并且以旁路巨大电流的低电阻的通路形成。所以PMDDSCR的触发电压也能通过改变雪崩击穿界面的浓度有效地减小，在NMDDSCR中具