FPGA verilog实现的1602时钟计数器

FPGAverilog实现的1602时钟计数器熬夜到了1点了，终于写出了1602的时钟计数器代码。为什么是时钟计数器呢？因为我还没来得及做校准时间，所以只能称之为时钟计数器，不能成为电子钟。网上很少用人公开这一类代码，一搜FPGA

1602，都是写一个静态的显示，在实际应用中，是没有用的，因此这个简单的例子，给大家抛砖引玉了！上代码：Qii9.0编译过，21EDA开发板测试OKmoduleLCD

(

rst,

key1,

clk,

rw,

rs,

en,

data

);

inputclk,rst,key1;

outputrs,en,rw;

output[7:0]data;

regrs,en_sel;

reg[7:0]data;

reg[7:0]shi,fen,miao;

reg[31:0]count,count1;

//LCDCLK分频计数器

reglcd_clk;

reg[7:0]one_1,one_2,one_3,one_4,one_5,one_6,one_7,one_8,one_9,one_10,one_11,one_12,one_13,one_14,one_15,one_16;

reg[7:0]two_1,two_2,two_3,two_4,two_5,two_6,two_7,two_8,two_9,two_10,two_11,two_12,two_13,two_14,two_15,two_16;

reg[7:0]next,xianshi,two;

parameter

state0

=8'h00,

//设置8位格式,2行,5*7

8'h38;

state1

=8'h01,

//整体显示,关光标,不闪烁

8'h0C

闪烁8'h0e

state2

=8'h02,

//设定输入方式,增量不移位

8'h06

state3

=8'h03,

//清除显示

8'h01

state4

=8'h04,

//显示第一行的指令

80H

state5

=8'h05,

//显示第二行的指令

80H+40H

scan

=8'h06,

nul

=8'h07;

parameter

data0

=8'h10,

//2行，共32个数据

data1

=8'h11,

data2

=8'h12,

data3

=8'h13,

data4

=8'h14,

data5

=8'h15,

data6

=8'h16,

data7

=8'h17,

data8

=8'h18,

data9

=8'h19,

data10

=8'h20,

data11

=8'h21,

data12

=8'h22,

data13

=8'h23,

data14

=8'h24,

data15

=8'h25,

data16

=8'h26,

data17

=8'h27,

data18

=8'h28,

data19

=8'h29,

data20

=8'h30,

data21

=8'h31,

data22

=8'h32,

data23

=8'h33,

data24

=8'h34,

data25

=8'h35,

data26

=8'h36,

data27

=8'h37,

data28

=8'h38,

data29

=8'h39,

data30

=8'h40,

data31

=8'h41;

initial

//初始值

begin

//第一行显示

TEL/p>

one_1<="T";one_2<="E";one_3<="L";one_4<=":";one_5<="1";one_6<="3";one_7<="8";one_8<="6";

one_9<="8";one_10<="1";one_11<="6";one_12<="0";one_13<="5";one_14<="6";one_15<="9";one_16<="";

//第二行显示Clock：00-00-00

two_1<="C";two_2<="l";two_3<="o";two_4<="c";two_5<="k";two_6<=":";two_7<="";two_8<="";

two_9<="-";two_10<="";two_11<="";two_12<="-";two_13<="";two_14<="";two_15<="";two_16<="";

shi<=0;fen<=0;miao<=0;

end

always@(posedgeclk)

//获得LCD时钟

begin

count<=count+1;

if(count==250000)

begin

count<=0;

lcd_clk<=~lcd_clk;

end

end

always@(posedgeclkornegedgerst

)

//时钟计数器

begin

if(!rst)

begin

shi<=0;fen<=0;miao<=0;

count1<=0;

end

else

begin

en_sel<=1;

two_7<=

(shi/10)+8'b00110000;

two_8<=

(shi%10)+8'b00110000;

two_10<=(fen/10)+8'b00110000;

two_11<=(fen%10)+8'b00110000;

two_13<=(miao/10)+8'b00110000;

two_14<=(miao%10)+8'b00110000;

count1<=count1+1'b1;

if(count1==49999999)

//时钟计数

begin

count1<=0;

miao<=miao+1;

if(miao==59)

begin

miao<=0;

fen<=fen+1;

if(fen==59)

begin

fen<=0;

shi<=shi+1;

if(shi==23)

begin

shi<=0;

end

end

end

end

end

end

always@(posedgelcd_clk

)

begin

case(next)

state0:

beginrs<=0;data<=8'h38;next<=state1;end

//配置液晶

state1:

beginrs<=0;data<=8'h0e;next<=state2;end

state2:

beginrs<=0;data<=8'h06;next<=state3;end

state3:

beginrs<=0;data<=8'h01;next<=state4;end

state4:

beginrs<=0;data<=8'h80;next<=data0;end

//显示第一行

data0:

beginrs<=1;data<=one_1;next<=data1;end

data1:

beginrs<=1;data<=one_2;next<=data2;end

data2:

beginrs<=1;data<=one_3;next<=data3;end

data3:

beginrs<=1;data<=one_4;next<=data4;end

data4:

beginrs<=1;data<=one_5;next<=data5;end

data5:

beginrs<=1;data<=one_6;next<=data6;end

data6:

beginrs<=1;data<=one_7;next<=data7;end

data7:

beginrs<=1;data<=one_8;next<=data8;end

data8:

beginrs<=1;data<=one_9;next<=data9;end

data9:

beginrs<=1;data<=one_10;next<=data10;end

data10:

beginrs<=1;data<=one_11;next<=data11;end

data11:

beginrs<=1;data<=one_12;next<=data12;end

data12:

beginrs<=1;data<=one_13;next<=data13;end

data13:

beginrs<=1;data<=one_14;next<=data14;end

data14:

beginrs<=1;data<=one_15;next<=data15;end

data15:

beginrs<=1;data<=one_16;next<=state5;end

state5:

beginrs<=0;data<=8'hC0;next<=data16;end//显示第二行

data16:

beginrs<=1;data<=two_1;next<=data17;end

data17:

beginrs<=1;data<=two_2;next<=data18;end

data18:

beginrs<=1;data<=two_3;next<=data19;end

data19:

beginrs<=1;data<=two_4;next<=data20;end

data20:

beginrs<=1;data<=two_5;next<=data21;end

data21:

beginrs<=1;data<=two_6;next<=data22;end

data22:

beginrs<=1;data<=two_7;next<=data23;end

data23:

beginrs<=1;data<=two_8;next<=data24;end

data24:

beginrs<=1;data<=two_9;next<=data25;end

data25:

beginrs<=1;data<=two_10;next<=data26;end

data26:

beginrs<=1;data<=two_11;next<=data27;end

data27:

beginrs<=1;data<=two_12;next<=data28;end

data28:

beginrs<=1;data<=two_13;next<=data29;end

data29:

beginrs<=1;data<=two_14;next<=data30;end

data30:

be