第五章-组合逻辑电路的VHDL语言描述课件

第五章VHDL基本描述语句5.1基本逻辑门电路5.2选择器电路5.3编码器与译码器电路5.4三态门及总线缓冲器电路5.5加法器电路5.6求补器电路5.7乘法器电路5.8数值比较器电路5.9移位器电路第五章VHDL基本描述语句5.1基本逻辑门电路5.1基本逻辑门电路基本门电路用VHDL语言来描述十分方便。为方便起见，在下面的两输入模块中，使用VHDL中定义的逻辑运算符，同时实现一个与门、或门、与非门、或非门、异或门及反相器的逻辑。这些基本逻辑门电路都组织成基本元件的形式，编程时可直接调用。5.1基本逻辑门电路基本门电路用VHDL语言来描述十分方便5.1.12输入与非门电路LIBRARYIEEE;--2输入与非门USEIEEE.STD_LOGIC_1164.ALL;ENTITYcynand2ISPORT(datain1,datain2:INSTD_LOGIC;dataout:OUTSTD_LOGIC);ENDENTITYcynand2;ARCHITECTUREbehavioralOFcynand2ISBEGINdataout<=datain1NANDdatain2;--行为描述ENDARCHITECTUREbehavioral;5.1.12输入与非门电路LIBRARYIEEE;LIBRARYIEEE;--2输入与非门USEIEEE.STD_LOGIC_1164.ALL;ENTITYcynand2ISPORT(datain1,datain2:INSTD_LOGIC;dataout:OUTSTD_LOGIC);ENDENTITYcynand2;LIBRARYIEEE;--2输入与非门ARCHITECTUREbehavioral_2OFcynand2ISBEGINPROCESS(datain1,datain2)VARIABLEcomb:STD_LOGIC_VECTOR(1DOWNTO0);BEGINcomb:=datain1&datain2;CASEcombISWHEN“00”=>dataout<=‘1’;--结构描述

WHEN"01"=>dataout<='1';WHEN"10"=>dataout<='1';WHEN"11"=>dataout<='0';WHENOTHERS=>dataout<='X';ENDCASE;ENDPROCESS;ENDARCHITECTUREbehavioral_2;ARCHITECTUREbehavioral_2OF仿真波形仿真波形5.1.22输入或非门LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcynor2ISPORT(datain1,datain2:INSTD_LOGIC;dataout:OUTSTD_LOGIC);ENDENTITYcynor2;ARCHITECTUREbehavioralOFcynor2ISBEGINdataout<=datain1NORdatain2;ENDARCHITECTUREbehavioral;5.1.22输入或非门LIBRARYIEEE;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcynor2ISPORT(datain1,datain2:INSTD_LOGIC;dataout:OUTSTD_LOGIC);ENDENTITYcynor2;LIBRARYIEEE;ARCHITECTUREbehavioral_2OFcynor2ISBEGINPROCESS(datain1,datain2)VARIABLEcomb:STD_LOGIC_VECTOR(1DOWNTO0);BEGINcomb:=datain1&datain2;CASEcombISWHEN"00"=>dataout<='1';WHEN"01"=>dataout<='0';WHEN"10"=>dataout<='0';WHEN"11"=>dataout<='0';WHENOTHERS=>dataout<='X';ENDCASE;ENDPROCESS;ENDARCHITECTUREbehavioral_2;ARCHITECTUREbehavioral_2OF仿真波形仿真波形5.1.3反相器电路LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcynotISPORT(datain:INSTD_LOGIC;dataout:OUTSTD_LOGIC);ENDENTITYcynot;ARCHITECTUREbehavioralOFcynotISBEGINdataout<=NOTdatain;ENDARCHITECTUREbehavioral;5.1.3反相器电路LIBRARYIEEE;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcynotISPORT(a,datain:INSTD_LOGIC;dataout:OUTSTD_LOGIC);ENDENTITYcynot;ARCHITECTUREbehavioral_2OFcynotISBEGINPROCESS(a,datain)--RTL描述方式,MAX中需要加入时钟aBEGINIF(datain='1')THENdataout<='0';ELSEdataout<='1';ENDIF;ENDPROCESS;ENDARCHITECTUREbehavioral_2;LIBRARYIEEE;仿真波形仿真波形5.1.42输入异或门电路LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcyxor2ISPORT(datain1,datain2:INSTD_LOGIC;dataout:OUTSTD_LOGIC);ENDENTITYcyxor2;ARCHITECTUREbehavioralOFcyxor2ISBEGINdataout<=datain1XORdatain2;ENDARCHITECTUREbehavioral;5.1.42输入异或门电路LIBRARYIEELIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcyxor2ISPORT(datain1,datain2:INSTD_LOGIC;dataout:OUTSTD_LOGIC);ENDENTITYcyxor2;LIBRARYIEEE;ARCHITECTUREbehavioral_2OFcyxor2ISBEGINPROCESS(datain1,datain2)VARIABLEcomb:STD_LOGIC_VECTOR(1DOWNTO0);BEGINcomb:=datain1&datain2;CASEcombISWHEN"00"=>dataout<='0';WHEN"01"=>dataout<='1';WHEN"10"=>dataout<='1';WHEN"11"=>dataout<='0';WHENOTHERS=>dataout<='X';ENDCASE;ENDPROCESS;ENDARCHITECTUREbehavioral_2;ARCHITECTUREbehavioral_2OF仿真波形仿真波形5.1.52输入同或门电路LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcynxor2ISPORT(datain1,datain2:INSTD_LOGIC;dataout:OUTSTD_LOGIC);ENDENTITYcynxor2;ARCHITECTUREbehavioralOFcynxor2ISBEGINdataout<=NOT(datain1XORdatain2);ENDARCHITECTUREbehavioral;5.1.52输入同或门电路LIBRARYIEEELIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcynxor2ISPORT(datain1,datain2:INSTD_LOGIC;dataout:OUTSTD_LOGIC);ENDENTITYcynxor2;LIBRARYIEEE;ARCHITECTUREbehavioral_2OFcynxor2ISBEGINPROCESS(datain1,datain2)VARIABLEcomb:STD_LOGIC_VECTOR(1DOWNTO0);BEGINcomb:=datain1&datain2;CASEcombISWHEN"00"=>dataout<='1';WHEN"01"=>dataout<='0';WHEN"10"=>dataout<='0';WHEN"11"=>dataout<='1';WHENOTHERS=>dataout<='X';ENDCASE;ENDPROCESS;ENDARCHITECTUREbehavioral_2;ARCHITECTUREbehavioral_2OF仿真波形仿真波形5.1.6多输入门电路LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcyor3ISPORT(datain1,datain2,datain3:INSTD_LOGIC;dataout:OUTSTD_LOGIC);ENDENTITYcyor3;ARCHITECTUREbehavioralOFcyor3ISBEGINdataout<=datain1ORdatain2ORdatain3;ENDARCHITECTUREbehavioral;5.1.6多输入门电路LIBRARYIEEE;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcyor3ISPORT(datain1,datain2,datain3:INSTD_LOGIC;dataout:OUTSTD_LOGIC);ENDENTITYcyor3;ARCHITECTUREbehavioral_2OFcyor3ISBEGINPROCESS(datain1,datain2,datain3)LIBRARYIEEE;VARIABLEcomb:STD_LOGIC_VECTOR(2DOWNTO0);BEGINcomb:=datain1&datain2&datain3;CASEcombISWHEN"000"=>dataout<='0';WHEN"001"=>dataout<='1';WHEN"010"=>dataout<='1';WHEN"011"=>dataout<='1';WHEN"100"=>dataout<='1';WHEN"101"=>dataout<='1';WHEN"110"=>dataout<='1';WHEN"111”=>dataout<='1';WHENOTHERS=>dataout<='X';ENDCASE;ENDPROCESS;ENDARCHITECTUREbehavioral_2;VARIABLEcomb:STD_LOGIC_VEC2.4输入与非门电路LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcynand4ISPORT(datain1,datain2:INSTD_LOGIC;datain3,datain4:INSTD_LOGIC;dataout:OUTSTD_LOGIC);ENDENTITYcynand4;ARCHITECTUREbehavioralOFcynand4ISBEGINdataout<=NOT(datain1ANDdatain2ANDdatain3ANDdatain4);ENDARCHITECTUREbehavioral;2.4输入与非门电路LIBRARYIEEE;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcynand4ISPORT(datain1,datain2:INSTD_LOGIC;datain3,datain4:INSTD_LOGIC;dataout:OUTSTD_LOGIC);ENDENTITYcynand4;ARCHITECTUREbehavioral_2OFcynand4ISBEGINPROCESS(datain1,datain2,datain3,datain4)VARIABLEcomb:STD_LOGIC_VECTOR(3DOWNTO0);BEGINcomb:=datain1&datain2&datain3&datain4;

LIBRARYIEEE;CASEcombISWHEN"0000"=>dataout<='1';WHEN"0001"=>dataout<='1';WHEN"0010"=>dataout<='1';WHEN"0011"=>dataout<='1';WHEN"0100"=>dataout<='1';WHEN"0101"=>dataout<='1';WHEN"0110"=>dataout<='1';WHEN"0111"=>dataout<='1';WHEN"1000"=>dataout<='1';WHEN"1001"=>dataout<='1';WHEN"1010"=>dataout<='1';

WHEN"1011"=>dataout<='1';WHEN"1100"=>dataout<='1';WHEN"1101"=>dataout<='1';WHEN"1110"=>dataout<='1';WHEN"1111"=>dataout<='0';WHENOTHERS=>dataout<='X';ENDCASE;ENDPROCESS;ENDARCHITECTUREbehavioral_2;CASEcombISWHEN"1011"=>5.2数据选择器5.2数据选择器第五章-组合逻辑电路的VHDL语言描述课件LIBRARYIEEE;--2选1数据选择器USEIEEE.STD_LOGIC_1164.ALL;ENTITYcy2_1muxIS PORT(datain1,datain2:INSTD_LOGIC;sel:INSTD_LOGIC;dataout:OUTSTD_LOGIC);ENDENTITYcy2_1mux;

LIBRARYIEEE;--2选1数据选择器ARCHITECTURErtlOFcy2_1muxISBEGINcy21mux_inst:PROCESS(datain1,datain2,sel)BEGINIF(sel='1')THEN dataout<=datain1;ELSEdataout<=datain2;ENDIF;ENDPROCESScy21mux_inst;ENDARCHITECTURErtl;ARCHITECTURErtlOFcy2_1muLIBRARYIEEE;--2选1数据选择器USEIEEE.STD_LOGIC_1164.ALL;ENTITYcy2_1muxIS PORT(datain1,datain2:INSTD_LOGIC;sel:INSTD_LOGIC;dataout:OUTSTD_LOGIC);ENDENTITYcy2_1mux;LIBRARYIEEE;--2选1数据选择器ARCHITECTURErtlOFcy2_1muxISBEGINcy21mux_inst:PROCESS(datain1,datain2,sel)BEGINCASEselIS--CASE语句的控制表达式是selWHEN'0'=>dataout<=datain2;WHEN'1'=>dataout<=datain1;WHENOTHERS=>dataout<='0';ENDCASE;ENDPROCESScy21mux_inst;ENDARCHITECTURErtl;ARCHITECTURErtlOFcy2_1mu仿真波形仿真波形5.2.216选1选择器5.2.216选1选择器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcy16_1muxISPORT(gn:INSTD_LOGIC;datain:INSTD_LOGIC_VECTOR(15DOWNTO0);sel:INSTD_LOGIC_VECTOR(3DOWNTO0);dataout:OUTSTD_LOGIC);ENDENTITYcy16_1mux;

LIBRARYIEEE;ARCHITECTURErtlOFcy16_1muxISBEGINc161mux_inst:PROCESS(gn,datain,sel)

BEGINIF(gn='0')THENIF(sel="0000")THENdataout<=datain(0);ELSIF(sel="0001")THENdataout<=datain(1);ELSIF(sel="0010")THENdataout<=datain(2);ELSIF(sel="0011")THENdataout<=datain(3);ELSIF(sel="0100")THENdataout<=datain(4);

ELSIF(sel="0101")THENdataout<=datain(5);

ELSIF(sel="0110")THENdataout<=datain(6);ELSIF(sel="0111")THENdataout<=datain(7);ELSIF(sel="1000")THENdataout<=datain(8);ELSIF(sel="1001")THENdataout<=datain(9);ELSIF(sel="1010")THENdataout<=datain(10);ELSIF(sel="1011")THENdataout<=datain(11);ELSIF(sel="1100")THENdataout<=datain(12);ELSIF(sel="1101")THENdataout<=datain(13);ELSIF(sel="1110")THENdataout<=datain(14);ELSEdataout<=datain(15);ENDIF;ELSEdataout<='0';ENDIF;ENDPROCESSc161mux_inst;ENDARCHITECTURErtl;ARCHITECTURErtlOFcy16_1m5.3编码器与译码器电路5.3.1编码器5.3编码器与译码器电路5.3.1编码器8线-3线普通编码器8线-3线普通编码器--8线-3线普通编码器libraryIEEE;useIEEE.std_logic_1164.all;useIEEE.std_logic_arith.all;useIEEE.std_logic_unsigned.all;entityptbm8_3isport(a:inSTD_LOGIC_VECTOR(7downto0); y:outSTD_LOGIC_VECTOR(2downto0));endptbm8_3;--8线-3线普通编码器architectureARCHofptbm8_3isBEGINPROCESS(a)BEGIN CASEaISwhen"00000001"=> Y<="000"; when"00000010“=> Y<="001"; when"00000100"=> Y<="010";when"00001000"=> Y<="011";when"00010000"=> Y<="100";when"00100000"=> Y<="101";when"01000000“=> Y<="110";whenothers=>Y<="111"; ENDCASE;ENDPROCESS;endARCH;architectureARCHofptbm8_3i仿真波形仿真波形第五章-组合逻辑电路的VHDL语言描述课件10线-4线优先级编码器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcypriority_encoderIS PORT( datain:INSTD_LOGIC_VECTOR(0TO9);dataout:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDENTITYcypriority_encoder;

ARCHITECTURErtlOFcypriority_encoderISBEGINPROCESS(datain)10线-4线优先级编码器LIBRARYIEEE;BEGIN IF(datain="1111111111")THEN dataout<="1111"; ELSE IF(datain(9)='0')THEN dataout<="0110"; ELSIF(datain(8)='0')THEN dataout<="0111"; ELSIF(datain(7)='0')THENdataout<="1000"; ELSIF(datain(6)='0')THENdataout<="1001"; ELSIF(datain(5)='0')THEN dataout<="1010";

ELSIF(datain(4)='0')THENdataout<="1011";ELSIF(datain(3)='0')THENdataout<="1100"ELSIF(datain(2)='0')THENdataout<="1101";ELSIF(datain(1)='0')THENdataout<="1110";ELSEdataout<="1111";ENDIF;ENDIF;ENDPROCESS;ENDARCHITECTURErtl;BEGINELSIF(datain(4)='0'LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcypriority_encoderIS PORT( datain:INSTD_LOGIC_VECTOR(0TO9);dataout:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDENTITYcypriority_encoder;

ARCHITECTURErtlOFcypriority_encoderISBEGINPROCESS(datain)BEGIN IF(datain="1111111111")THEN dataout<="1111"; ELSE IF(datain(9)='0')THEN dataout<="0110"; ELSIF(datain(8)='0')THEN dataout<="0111"; ELSIF(datain(7)='0')THENdataout<="1000"; ELSIF(datain(6)='0')THENdataout<="1001"; ELSIF(datain(5)='0')THEN dataout<="1010";ELSIF(datain(4)='0')THENdataout<="1011";ELSIF(datain(3)='0')THENdataout<="1100";ELSIF(datain(2)='0')THENdataout<="1101";ELSIF(datain(1)='0')THENdataout<="1110";ELSEdataout<="1111";ENDIF;ENDIF;ENDPROCESS;ENDARCHITECTURErtl;LIBRARYIEEE;8线-3线优先编码器8线-3线优先编码器8线-3线优先编码器LIBRARYieee;USEieee.std_logic_1164.ALL;Entitypriorityisport(A:inbit_vector(7downto0);Y:outbit_vector(2downto0));EndEntitypriority;8线-3线优先编码器LIBRARYieee;architecturev1ofpriorityisbeginprocess(I)beginifA(7)='1‘thenY<="111";elsifA(6)='1'thenY<="110";elsifA(5)='1'thenY<="101";elsifA(4)='1'thenY<="100";elsifA(3)='1'thenY<="011";elsifA(2)='1'thenY<="010";elsifA(1)='1'thenY<="001";elsifA(0)='1'thenY<="000";elseY<=“000”;endif;endprocess;endv1;architecturev1ofpriorityis仿真波形仿真波形5.3.2译码器5.3.2译码器4线16线译码器真值表4线16线译码器真值表LIBRARYIEEE;--4线16线译码器USEIEEE.STD_LOGIC_1164.ALL;ENTITYcydecoder_4_16ISPORT(D,C,B,A:INSTD_LOGIC;G1N,G2N:INSTD_LOGIC;q:OUTSTD_LOGIC_VECTOR(15DOWNTO0));ENDENTITYcydecoder_4_16;

ARCHITECTURErtlOFcydecoder_4_16ISSIGNALtemp_datain:STD_LOGIC_VECTOR(3DOWNTO0);BEGINtemp_datain<=D&C&B&A; PROCESS(D,C,B,A,G1N,G2N) BEGINLIBRARYIEEE;--4线16线译码器IF(G1N='0'ANDG2N='0')THEN--译码器的选通信号低电平有效

CASEtemp_datainIS WHEN"0000"=>q<="1111111111111110"; WHEN"0001"=>q<="1111111111111101"; WHEN"0010"=>q<="1111111111111011"; WHEN"0011"=>q<="1111111111110111"; WHEN"0100"=>q<="1111111111101111"; WHEN"0101"=>q<="1111111111011111"; WHEN"0110"=>q<="1111111110111111"; WHEN"0111"=>q<="1111111101111111";

IF(G1N='0'ANDG2N='0')T

WHEN"1000"=>q<="1111111011111111"; WHEN"1001"=>q<="1111110111111111"; WHEN"1010"=>q<="1111101111111111"; WHEN"1011"=>q<="1111011111111111"; WHEN"1100"=>q<="1110111111111111"; WHEN"1101"=>q<="1101111111111111"; WHEN"1110"=>q<="1011111111111111"; WHEN"1111"=>q<="0111111111111111"; WHENOTHERS=>q<="XXXXXXXXXXXXXXXX"; ENDCASE; ELSE q<="1111111111111111"; ENDIF;ENDPROCESS;ENDARCHITECTURErtl;WHEN"1000"=>仿真波形仿真波形4线10线译码器真值表4线10线译码器真值表LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcybcddecoder_4_10ISPORT(D,C,B,A:INSTD_LOGIC;q:OUTSTD_LOGIC_VECTOR(0TO9));ENDENTITYcybcddecoder_4_10;

ARCHITECTURErtlOFcybcddecoder_4_10ISSIGNALtemp_datain:STD_LOGIC_VECTOR(3DOWNTO0);BEGINtemp_datain<=D&C&B&A;PROCESS(temp_datain)BEGINLIBRARYIEEE;USEIEEE.STD_CASEtemp_datainIS--CASE语句的条件表达式是位矢量temp_datainWHEN"0000"=>q<="1111111110";WHEN"0001"=>q<="1111111101";WHEN"0010"=>q<=""1111111011";WHEN"0011"=>q<="1111110111";WHEN"0100"=>q<="1111101111";WHEN"0101"=>q<="1111011111";WHEN"0110"=>q<="1110111111";WHEN"0111"=>q<="1101111111";WHEN"1000"=>q<="1011111111";WHEN"1001"=>q<="0111111111";WHENOTHERS=>q<="1111111111";ENDCASE;ENDPROCESS;ENDARCHITECTURErtl;CASEtemp_datainIS--CASE仿真波形仿真波形5.4三态门及总线缓冲电路5.4.1三态门5.4三态门及总线缓冲电路5.4.1三态门LIBRARYIEEE;--用进程里的IF语句来实现USEIEEE.STD_LOGIC_1164.ALL;ENTITYtriple_bufferISPORT(datain,en:INSTD_LOGIC;dataout:OUTSTD_LOGIC);ENDENTITYtriple_buffer;LIBRARYIEEE;--用进程里的IFARCHITECTUREtri_method1OFtriple_bufferISBEGINPROCESS(datain,en)BEGINIF(en='1')THENdataout<=datain;ELSEdataout<='Z';ENDIF;ENDPROCESS;ENDARCHITECTUREtri_method1;ARCHITECTUREtri_method1OF仿真波形仿真波形LIBRARYIEEE;--第三种方法用进程里的CASE语句来实现USEIEEE.STD_LOGIC_1164.ALL;ENTITYtriple_bufferISPORT(datain,en:INSTD_LOGIC;dataout:OUTSTD_LOGIC);ENDENTITYtriple_buffer;LIBRARYIEEE;--第三种方法用进程里的CAARCHITECTUREtri_method3OFtriple_bufferISBEGINPROCESS(datain,en)BEGINCASEenISWHEN'1'=>dataout<=datain;WHENOTHERS=>dataout<='Z';ENDCASE;ENDPROCESS;ENDARCHITECTUREtri_method3;ARCHITECTUREtri_method3OF5.4.2总线缓冲器1.单向缓冲器5.4.2总线缓冲器1.单向缓冲器LIBRARYIEEE;--第一种方法用两个进程语句来实现USEIEEE.STD_LOGIC_1164.ALL;ENTITYsingle_buffer_74244ISPORT(en_1,en_2:INSTD_LOGIC;

datain_1,datain_2:INSTD_LOGIC_VECTOR(3DOWNTO0);

dataout_1,dataout_2:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDENTITYsingle_buffer_74244;ARCHITECTUREbuffer_74244_method1OFsingle_buffer_74244ISBEGINLIBRARYIEEE;--第一种方法用两个进程语句method1_1:PROCESS(datain_1,en_1) BEGIN IF(en_1='0')THEN--选通信号是低电平有效的

dataout_1<=datain_1; ELSE dataout_1<="ZZZZ"; ENDIF;ENDPROCESSmethod1_1;method1_2:PROCESS(datain_2,en_2) BEGIN IF(en_2='0')THEN dataout_2<=datain_2; ELSE dataout_2<="ZZZZ"; ENDIF;ENDPROCESSmethod1_2;ENDARCHITECTUREbuffer_74244_method1;method1_1:PROCESS(datain_仿真波形仿真波形2.双向缓冲器2.双向缓冲器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYdouble_buffer_74245ISPORT(oe,dir:INSTD_LOGIC; dataA,dataB:INOUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDENTITYdouble_buffer_74245;ARCHITECTUREbehavioralOFdouble_buffer_74245ISSIGNALoutA,outB:STD_LOGIC_VECTOR(7DOWNTO0);BEGIN LIBRARYIEEE;instA_74245:PROCESS(oe,dir,dataA)--数据从A流向B BEGIN IF((oe='0')AND(dir='1'))THEN outB<=dataA; ELSE outB<="ZZZZZZZZ"; ENDIF; dataB<=outB; ENDPROCESSinstA_74245;

instA_74245:PROCESS(oe,instB_74245:PROCESS(oe,dir,dataB)--数据从B流向A BEGIN IF((oe='0')AND(dir='0'))THEN outA<=dataB; ELSE outA<="ZZZZZZZZ"; ENDIF; dataA<=outA; ENDPROCESSinstB_74245;ENDARCHITECTUREbehavioral;instB_74245:PROCESS(oe,仿真波形仿真波形5.5加法器电路1.半加器5.5加法器电路1.半加器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYhalf_adderISPORT(dataA,dataB:INSTD_LOGIC;sum:OUTSTD_LOGIC;carry:OUTSTD_LOGIC);ENDENTITYhalf_adder;ARCHITECTUREdataflowOFhalf_adderISBEGIN sum<=dataAXORdataB;--和数满足逻辑异或关系

carry<=dataAANDdataB;--进位位满足逻辑与关系ENDARCHITECTUREdataflow;LIBRARYIEEE;仿真波形仿真波形2.全加器2.全加器LIBRARYIEEE;--直接根据真值表设计USEIEEE.STD_LOGIC_1164.ALL;ENTITYfull_adderISPORT(dataA,dataB,carryin:INSTD_LOGIC;sum:OUTSTD_LOGIC;carryout:OUTSTD_LOGIC);ENDENTITYfull_adder;ARCHITECTURErtlOFfull_adderISBEGIN sum<=dataAXORdataBXORcarryin;--和数满足逻辑异或关系

carryout<=(dataAANDdataB)OR(dataAANDcarryin)OR(dataBANDcarryin);ENDARCHITECTURErtl;LIBRARYIEEE;--直接根据真值表设计仿真波形仿真波形由两个半加器元件和一个或门构成的全加器由两个半加器元件和一个或门构成的全加器LIBRARYIEEE;--由两个半加器元件和一个或门构成的全加器USEIEEE.STD_LOGIC_1164.ALL;ENTITYfull_adderISPORT(dataA,dataB,carryin:INSTD_LOGIC;sum:OUTSTD_LOGIC;carryout:OUTSTD_LOGIC);ENDENTITYfull_adder;LIBRARYIEEE;--由两个半加器元件和一个或门ARCHITECTUREstructOFfull_adderISCOMPONENThalf_adderPORT(a,b:INSTD_LOGIC;s:OUTSTD_LOGIC;ca:OUTSTD_LOGIC);ENDCOMPONENT;SIGNALu1sum,u1carry,u2carry:STD_LOGIC;BEGINu1:half_adderPORTMAP(dataA,dataB,u1sum,u1carry);u2:half_adderPORTMAP(u1sum,carryin,sum,u2carry);carryout<=u2carryORu1carry;ENDARCHITECTUREstruct;ARCHITECTUREstructOFfull4位加法器libraryIEEE;--4位加法器useIEEE.std_logic_1164.all;useIEEE.std_logic_arith.all;useIEEE.std_logic_unsigned.all;entityadder4bisport(cin:inSTD_LOGIC;a,b:inSTD_LOGIC_VECTOR(3downto0); cout:outSTD_LOGIC;s:outSTD_LOGIC_VECTOR(3downto0));endadder4b;4位加法器libraryIEEE;--4位加法器architectureARCHofadder4bissignalsint,aa,bb:STD_LOGIC_VECTOR(4downto0);BEGINaa<='0'&a(3downto0);bb<='0'&b(3downto0);sint<=aa+bb+cin;s(3downto0)<=sint(3downto0);cout<=sint(4);endARCH;architectureARCHofadder4bi仿真波形仿真波形3.自定制加/减法电路3.自定制加/减法电路5.6求补器电路LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;useIEEE.std_logic_arith.all;useIEEE.std_logic_unsigned.all;ENTITYcomplementISPORT(datain:INSTD_LOGIC_VECTOR(15DOWNTO0);dataout:OUTSTD_LOGIC_VECTOR(15DOWNTO0));ENDENTITYcomplement;ARCHITECTUREbehavioralOFcomplementISSIGNALtemp:STD_LOGIC_VECTOR(15DOWNTO0);BEGIN temp<=NOTdatain;--对输入数据取反

dataout<=temp+"0000000000000001";--对反码加1ENDARCHITECTUREbehavi