mx6ul ddr3调校应用手册此主要说明如何i MX6ULDDR

MX6ULDDR3 JohnLi(R64710)GSMCAS,,UpdateDDRstresstesttoolstoversion2.40AddDDRconfigurationaidusage

硬件资源，文档及工具硬件资 DDR3调校用的DDR压力测试工 配置DDR3相关参 硬件连 生成DDR3初始化 AppendixA:DDR3基本知 AppendixB:WriteLeveling设 AppendixC:Write/readdelayline概 Designfiles,includinghardwareschematics,Gerbers,andOrCADfiles.(REVDesignfiles,includinghardwareschematics,Gerbers,andOrCADfiles..ZIP(9.9MB)MCIMX6UL-EVKSPF-28617_C1.pdf,DDRMT41K256M16HA-125:E512MB可以从美光其: /parts/dram/ddr3-sdram/mt41k256m16ha-注意从美光公开的可能缺少一些关键的参数，如时序和页大小之类的，所 除了DDR3的，我们可能也需要JEDECDDR3规范，可以从以下地址，需要注 i.MX6UltraLiteApplicationsProcessorReference(REV0)PDF(33.1MB)IMX6ULRMi.MX6UltraLiteEVKBoardHardwareUser's(REV0)PDF(732.4kB)IMX6ULEVKHDG，使用一个通过USB(otg)连接的工具，来测试，校准目标板上的DDR，名称为” 工具已经升级到了V2.52的版本，可以使用新版本，与V2.40相比增加了一些功能)，DDR3相关参数配置比较复杂，准备了一个excel工具来简化这个过程，可以从恩智浦社区连接mu /docs/DOC-329899,I.MX6ULDDR3ScriptAid,请在使用前参考它的readme页.DDR3测试工具要求工作在i.MX6UL的模式下(BOOT_MODE[1:0]=0b01,在i.MX6ULEVKCPUSW602SW602_1=0,SW602_2=1),(i.MX6ULromcode如果不能正常的从内部启动模式启动起来，它会自动进入模式,因为i.MX6UL是使使用的固件到i.MX6UL的内部RAM中，用于测试外部的DDR3。USBPCEVKUSBOTGJ1102。然后插入5V电源，电源接口为J2001。Romcode在进入模式后，首先会通过USB口上报自己这意味着i.MX6UL板子已经进入模式，硬件连接如下图DDR3生成工具还没有发布所以我们直接使用ddrstresstest工具中的默认)Memorytypeof-125numberis:DDR3-DRAMdensity(Gb)=256MxDRAMBusNumberofNumberofROWAddresses=15NumberofCOLUMN=10PagetRCtRASBuswidth=16(i.MX6UL16DensityperchipSelect(Gb)DDRNumberofChipSelectsused=1(EVKCS04TotalDRAMDensity(Gb)DRAMClockFreq(Mhz)=400(i.MX6ULDRAMClockCycleTime(ns)=2.5ns自动配置i.MX6ULMMDC400MhzDDR3可以工作在1600)nS),而不是时钟周期参数(clock),800MHz来计算的，不正确。DRAMDSESetting-DRAMDSESetting-DRAMDSESetting-DRAMDSESetting-SystemODTDeviceMemorypartMemoryDRAMdensity4DRAMBusNumberof8NumberofROWNumberofCOLUMNPageSize2Self-RefreshTemperaturetRCD=tRP=CLtRCMintRASMinSystemi.MxBusDensityperchipselect4NumberofChipSelects1TotalDRAMDensity4DRAMClockFreqDRAMClockCycleTimeAddressMirror(forSIDRAMDSESetting-DQ/DQMDRAMDSESetting-ADDR/CMD/CTLDRAMDSESetting-CKDRAMDSESetting-DQSSystemODTSettingRealview.incDDR3txt文件打开此，修改以下项//Disable//setmem 0x020bc000 0x30//注掉此项，DCD不可以此地DDR3//Fortargetboard,mayneedtorunwritelevelingcalibrationtofinetunethesesettings.setmem/320x021b080c= //ReadDQSGatingsetmem/320x021b083c //MPDGCTRL0//Readsetmem/320x021b0848 //MPRDDLCTL//Writesetmem/320x021b0850 //MPWRDLCTL//readdatabitdelay:(3isthe mendeddefaultvalue,althoughoutofresetvalueis0)setmem/320x021b081c= //MMDC_MPRDDQBY0DLsetmem/320x021b0820 ////writedatabitsetmem0x021b082csetmem0x021b0830,:ddr-test-mx6ul.bin:到目标板上的测试固件,MX6UL_MMDC_DDR3_register_programming_aid.inc,DDR初始化DDRstresstestV2.40i.MX6UL的设定，所以选择为TARGET:ARMSpeed:Default(i.MX6ULdefault528Mhz800Mhz,1GhzVerifyDCDDDRDensity:Default或是选择i.MX6ULEVK板使用的512MB,注意如果选择大于或小于你的定义的尺寸，DDRstresstest会报错DDRCS:0i.MX6ULDDRChannel:i.MX6UL16bitChannelLoadInitScrpit,选择\ddr_stress_tester_v2.40\script\mx6ul\Download:点击Download后，会打印出DDR的配置信息，这个配置信息是从初始化中设置MMDC相关寄存器实际读出来的，所以如果这个信息不对，那肯定也不对。DDRCalibrationDDRCalibration相关参数：DDRFreq(MHz):i.MX6UL400Mhz,400DDR有问题，400Mhz的频率上运行，也可以选择相应频率来做校准。DDRCalibration:点击DDRCalibration按钮，开始校准(需要一段时间)。校准结果会打印在SaveResult:SaveResult -校准结束后，可以直接力测试(?)，或是关闭DDRstress测试程序，将获得的校准值写回到初始化中。//Writesetmemsetmem/320x021B080C= //[MMDC_MPWLDECTRL0]MMDCPHYWriteLevelingControlRegister <26:25>WL_CYC_DEL1 =2'b00:setWriteLevelingCycleDelayforByte1: nodelayis <24>WL_HC_DEL1 =1'b0: setWriteLevelingHalfCycleDelayforByte1:nodelayis <22:16>WL_DL_ABS_OFFSET1=7'h13:setAbsoluteWrite-LevelingDelayOffsetforByte1:; <10:9>WL_CYC_DEL0 =2'b00:setWriteLevelingCycleDelayforByte0: nodelayis =1'b0: setWriteLevelingHalfCycleDelayforByte0:nodelayis <6:0>WL_DL_ABS_OFFSET0=7'h0F:setAbsoluteWrite-LevelingDelayOffsetforByte0://DQSgating,readdelay,writedelaycalibrationvaluesbasedoncalibrationcompareof//Itis mendedfortheusertoruncalibrationcodeonher/hisspecific//andrecefollowingdelayvalues//ReadDQSGatingsetmemsetmem/320x021B083C= //[MMDC_MPDGCTRL0]MMDCPHYReadDQSGatingRegister <31>RSTRD = ResetReadDataFIFO&Associated <30> = ReadDQSGatingSample <29>DG = ReadDQSGating <28> = AutomaticReadDQSGating <27:24>DGHC = ReadDQSGatingHalfCyclesDelayforByte1: <23> = DGExtendupper <22:16>DG_DL_ABS_OFFSET1= AbsoluteReadDQSGatingDelayOffsetfor <11:8> = ReadDQSGatingHalfCyclesDelayforByte0: <6:0>DG_DL_ABS_OFFSET0= AbsoluteReadDQSGatingDelayOffsetfor//Readsetmemsetmem/320x021B0848= //[MMDC_MPRDDLCTL]MMDCPHYReaddelay-Configuration <14:8>RD_DL_ABS_OFFSET1= AbsoluteReadDelayOffsetfor <6:0>RD_DL_ABS_OFFSET0= AbsoluteReadDelayOffsetfor//Writesetmem/320x021B0850=0x C//0x D//[MMDC_MPWRDLCTL]MMDCPHYWritedelay-linesConfigurationRegister <14:8>WR_DL_ABS_OFFSET1= AbsoluteWriteDelayOffsetfor <6:0>WR_DL_ABS_OFFSET0= AbsoluteWriteDelayOffsetfor注意：DDRStresstestV2.4中，如果writeleveling的值如果校准出来大于1/8clock周期，则自动设setmemsetmem/320x021B0018= or //[MMDC_MDMISC]MMDCCore <21>CK1_GATING =1'b1: MMDCdrivesonlyoneclocktowardtheDDR <20> = Calibrationistargetedto: <19> = setAddressMirroringas <18> = Thisisadebugfeature:Whensetto"1"theMMDCwillhandleread/writeaccessata <17:16> = <12>BI = <11> = <10:9>MIF3 = <8:6> =3'b101:3'b101standsfor DDR4 = setNumberofbanksperDDRdevice.0standsfor8<4:3>DDR=2'b00:DDR3SDRAMdeviceis = SoftwareReset:0meansdoi.MX6ULEVK板DDRstresstestDDRStressTest框中OverNightTest:如果要做长期测试，可以勾选此条，选择后，DDRStressTestStartFreq(MHz):因为i.MX6UL400Mhz,400Mhz,135Mhz,EndFreq(MHz):EndFreq(MHz)=StartFreq(MHz)来做长期稳定测试，这儿我们672Mhz来做超频测试DDRStressTest:DDRStressTest8400x(1.1~1.15)=440Mhz~460Mhzi.MX6ULEVKSaveResult:点击SaveResult按钮，保存\ddr_stress_tester_v2.40\log\ DDR3稳定。i.MX6UL16bitDDR尺寸选择就少很多，我们分别列16bit1GB内存，16bit512MB内存，16bit256MBDDRDDR设置。16bitFF尺寸相关i.MX6ULMMDC0x8000_0000,所以0x8000_0000/0x200_0000(256Mbit)=0x40,0x40-1=0x3F.所以256MB,512M,1GB256/32(MB)+0x3F=0x47,512/32(MB)+0x3F=0x4F,1024/32+3F=0x5F。0Xx4xxxxxxRow=160Xx5xxxxxxbus=16bit0Xxxx8xxxx。TimingtimingddrtimingMMDC0_MDCFG0=0x021b000ctRFCtXSMMDC0_MDOR=0x021b0030tXPRDDR3参数包括两个部分：i.MX6ULBSPL3.14.38，ubootDDR3参数方法如下：*Copyright(C) scaleSemiconductor,*SPDX-License- *Referdocs/README.imxmageformoredetailsabouthow-to*andcreateimximageboot*Thesyntaxistakenascloseaspossiblewiththe#defineASSEMBLY #include<config.h>/*imageversionIMAGE_VERSION*BootDevice:one*spi/sd/nand/onenand,#ifdefCONFIG_SYS_BOOT_QSPI #elif #ifdef/*PLUGIN/*PLUGINplugin-binary-file scale/mx6ul_14x14_evk/plugin.bin #ifdefCONFIG_SECURE_BOOTCSFCONFIG_CSF_SIZE*DeviceConfigurationData*Eachentrymusthavethe*Addr- ** Addr-typeregisterlength(1,2or4 Addressabsoluteaddressofthe valuetobestoredinthe/*EnableallclocksDATA40x020c4068DATA40x020c406cDATA40x020c4070DATA40x020c4074DATA40x020c4078DATA40x020c407cDATA40x020c4080DATA40x020c4084DATA40x020E04B4DATA40x020E04ACDATA40x020E027CDATA40x020E0250DATA40x020E024CDATA40x020E0490DATA40x020E0288DATA40x020E0270DATA40x020E0260DATA40x020E0264DATA40x020E04A0DATA40x020E0494DATA40x020E0280DATA40x020E0284DATA40x020E04B0DATA40x020E0498DATA40x020E04A4DATA40x020E0244DATA40x020E0248DATADATA40x021B001CDATA40x021B0800DATA40x021B080C//writelevelingDATA40x021B083C////ReadDQSDATA40x021B0800DATA40x021B080C//writelevelingDATA40x021B083C////ReadDQSGatingDATA40x021B0848////ReadDATA40x021B0850C//D//WriteDATA40x021B081CDATA40x021B0820DATA40x021B082CDATA40x021B0830DATA40x021B08C0DATA40x021B0858DATA40x021B08b8DATA40x021B0004DDATA40x021B0008DATA40x021B000CDATA40x021B0010DATA40x021B0014DATA40x021B0018//DATA40x021B001CDATA40x021B002CDATA40x021B0030DATA40x021B0040FDATA40x021B0000DATA40x021B001CDATA40x021B001CDATA40x021B001CDATA40x021B001CDATA40x021B001CDATA40x021B0020DATA40x021B0818DATA40x021B0004DDATA40x021B0404DATA40x021B001CAppendixADDR3DDR=DoubleDataRate双倍速率同步动态随机器。严格的说DDR应该叫DDRSDRAMDDR，其中，SDRAMSynchronousDynamicRandomAccessMemory的缩写，即同步动态随机存取器。而DDRSDRAM是DoubleDataRateSDRAM的缩写，是双倍速率同步动态随机器的意思。它能够在时钟的上升期和下降期各传输一次数据,DDR内DDR内存可以在脉冲的上升和下降沿都传输数据，因此传输数据的等效频率是工作频率的BL）8寻址时序（Timing）:DDR2DDR转变而来后延迟周期数增加一样，DDR3CL周DDR2DDR2CL2～5DDR35～11之间，且附加延迟（AL）的设计也有所变化。DDR2AL0～4DDR3AL有三0、CL-1CL-2。另外，DDR3还新增加了一个时序参数——写入延迟DDR3ZQ校准功能:ZQ240欧姆的低公差EngineODCE）ODT的终结电阻值。当系统发出这一指令后，将用相应的时钟周期（51225664个时钟周期）ODT电阻进行重新校准AppendixBWriteLevelingDDRlayoutDQSCKT-Topologyfly-by所以我们T-Topology,都使用相近的值0x1F,fly-by的比较近的两片使用0x44T-Topologywritelevelingcalibration.fly-byAppendixC:Write/readdelayline读DQSdelaylinecalibration用于在读BYTEDQS信号的delay,当读BYTE数据从01/2周期的窗口。DQSdelaylinecalibrationdelay AppendixD:DRAM接口高阶应用指导-DDR3 HowtoReachHomeWeb USA/EuropeorLocationsNotscaleTechnicalInformationCenter,EL5162100EastElliotRoadTempe,Arizona

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