电气实践23.1fpga程序二设计实验附录

1libraryuseuseentitydecoderisport(a,b,c:instd_logic;d1,d2:instd_logic;d_out:outstd_logic);

指令 architecturemainofdecodersignals:std_logic_vector(2downto0);casesiswhen"001"=>d_out<=d1andd2;when"010"=>d_out<=d1ord2;when"011"=>d_out<=d1;--d1notwhen"100"=>d_out<=(d1andnotd2)or(notd1andd2);when"101"=>d_out<=(d1andd2)or(notd1andnotd2);whenothers=>d_out<='Z';endcase;endprocess;libraryuseuseentitystate_stepperisport(clk,dir:instd_logic;q:outstd_logic_vector(3downto

architecturessofstate_stepperistypestate_typeis(s0,s1,s2,s3);signalstate:state_type;signalq_out:std_logic_vector(3downto0);ifclk'eventandclk='1'thencasestateiswhens0=>endif;whens1=>endif;whens2=>endif;whens3=>endif;endcase;endif;endwithstateq_out<="0001""0010""0100""1000"endss;library useuseieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entityCTR60isq:outstd_logic_vector(7downto0);c:outstd_logic);endarchitecturebehaveofCTR60signalIQ:std_logic_vector(7downto0);process(clr,clk,IQ)isif(clr='1')thenIQ<=" elsif(clk'eventandclk='1')thenif(IQ(7downto0)=" IQ(7downto0)<=" elsif(IQ(3downto0)="1001")thenIQ(3downto0)<="0000";IQ(7downto4)<=IQ(7downto4)+1;elseIQ(3downto0)<=IQ(3downto0)+1;endendif;endprocess;endbehave;library useuseieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entityCTR24isq:outstd_logic_vector(7downto0));endCTR24;architecturebehaveofCTR24signalIQ:std_logic_vector(7downto0);process(clr,clk,IQ)isif(clr='1')thenIQ<=" elsif(clk'eventandclk='1')thenif(IQ(7downto0)=" IQ(7downto0)<=" endif;endprocess;endbehave;

elsif(IQ(3downto0)="1001")thenIQ(3downto0)<="0000";IQ(7downto4)<=IQ(7downto4)+1;elseIQ(3downto0)<=IQ(3downto0)+1;endif;library useuseieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entitycontrolish_in:instd_logic_vector(7downto0);m_in:instd_logic_vector(7downto0);s_in:instd_logic_vector(7downto0);H_OUT:outstd_logic_vector(7downto0);M_OUT:outstd_logic_vector(7downto0);S_OUT:outstd_logic_vector(7downto0);en:outstd_logic;F_out:outstd_logic_vector(2downto0));endcontrol;architecturebehaveofcontroltypestate_typeis(s0,s1,s2,s3,s4,s5,s6);signalstate:state_type;signalIQH:std_logic_vector(7downto0);signalIQM:std_logic_vector(7downto0);signalIQS:std_logic_vector(7downto0); if(mode'eventandmode='1')thencasestateiswhens0=>state<=s1;whens1=>state<=s2;whens2=>state<=s3;whens3=>state<=s4;whens4=>state<=s5;whens5=>state<=s6;whenendcase;endif;end if(mode'eventandmode='1')thencasestateiswhens0=>whens1=>if(IQH(7downto4)="0010")thenIQH(7downto4)<="0000";elseIQH(7downto4)<=IQH(7downto4)+1;endif;IQH(3downto0)<=h_in(3downto0);whens2=>if(IQH(3downto0)="1001")thenIQH(3downto0)<="0000";elseIQH(3downto0)<=IQH(3downto0)+1;endif;IQH(7downto4)<=h_in(7downto4);whens3=>if(IQM(7downto4)="0101")thenIQM(7downto4)<="0000";elseIQM(7downto4)<=IQM(7downto4)+1;endif;IQM(3downto0)<=m_in(3downto0);whens4=>if(IQM(3downto0)="1001")thenIQM(3downto0)<="0000";elseIQM(3downto0)<=IQM(3downto0)+1;endif;IQM(7downto4)<=m_in(7downto4);whens5=>if(IQS(7downto4)="0101")thenIQS(7downto4)<="0000";elseIQS(7downto4)<=IQS(7downto4)+1;endif;IQS(3downto0)<=s_in(3downto0);whens6=>if(IQS(3downto0)="1001")thenIQS(3downto0)<="0000";elseIQS(3downto0)<=IQS(3downto0)+1;endif;IQS(7downto4)<=s_in(7downto4);endcase;endendprocess;endbehave;library useuseieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entitydivideisclk_out:outendarchitecturebehaveofdivideissignalsignalcout:integerrange0to199999;if(CLK_IN'eventandCLK_IN='1')thenif(cout<=50000)thenelsif(cout<99999)elsecout<=0;endif;endif;endprocess;endbehave;library useuseieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entityscanisf_in:instd_logic_vector(2downto0);H_IN:instd_logic_vector(7downto0);M_IN:instd_logic_vector(7downto0);S_IN:instd_logic_vector(7downto0);Segctr:outstd_logic_vector(7downto0);q_out:outstd_logic_vector(3downtoendarchitecturescaofscantypestate_typeis(s0,s1,s2,s3,s4,s5);signalstate:state_type;signalQ:std_logic_vector(3downto0); if(clk'eventandclk='1')thencasestateiswhens0=>state<=s1;whens1=>state<=s2;whens2=>state<=s3;whens3=>state<=s4;whens4=>state<=s5;whenendcase;endif;end casestatewhens0=>Segctr(6downto0)<=" elseSegctr<=" endQ<=H_IN(7downto4);whens1=>Segctr(5downto0)<="000000";elseSegctr<=" endQ<=H_IN(3downto0);whens2=>Segctr(7downtoSegctr(4downto0)<="00000";elseSegctr<=" endQ<=M_IN(7downto4);whens3=>Segctr(7downtoSegctr(3downto0)<="0000";elseSegctr<=" endQ<=M_IN(3downto0);whens4=>Segctr(7downtoSegctr(2downto0)<="000";elseSegctr<=" endQ<=S_IN(7downto4);whens5=>Segctr(7downtoSegctr(1downto0)<="00";elseSegctr<=" Q<=S_IN(3downto0);endif;endcase;endprocess;endlibrary --显示译模块disuseuseieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entitydisyisport(a:instd_logic_vector(3downto0);f:outstd_logic_vector(7downto0));enddisarchitecturedataofdisyiscasea whenothers=>f<=" endcase;endprocess;enddata;library useentitytri_gateport(indate,en:instd_logic;yout:outstd_logic);endarchitecturetrioftri_gateisendif;endprocess;endtri;library useuseieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entityClockisSeg7:outstd_logic_vector(7downto0);Segctr:outstd_logic_vector(7downto0));endarchitecturedigital_clockofClocksignalCM,CS,CLK1Hz,CLK_COU,EN:std_logic;signalHour:std_logic_vector(7downto0);signalMinute:std_logic_vector(7downto0);signalSecond:std_logic_vector(7downtosignalHSCAN:std_logic_vector(7downto0);signalMSCAN:std_logic_vector(7downto0);signalSSCAN:std_logic_vector(7downto0);signalflash:std_logic_vector(2downto0);signalY:std_logic_vector(3downto0);componentCTR60isport(clr,clk:instd_logic;q:outstd_logic_vector(7downto0);c:outstd_logic);endcomponentcomponentCTR24isport(clr,clk:instd_logic;q:outstd_logic_vector(7downto0));endcomponentCTR24;componentcontrolisport(mode,set:instd_logic;h_in:instd_logic_vector(7downto0);m_in:instd_logic_vector(7downto0);s_in:instd_logic_vector(7downto0);H_OUT:outstd_logic_vector(7downto0);M_OUT:outstd_logic_vector(7downto0);S_OUT:outstd_logic_vector(7downto0);en:outstd_logic;F_out:outstd_logic_vector(2downto0));endcomponentcontrol;componentdivideisport(CLK_IN:instd_logic;clk_out:outstd_logic);endcomponentdivide;componentscanisport(clk,clk1:instd_logic;f_in:instd_logic_vector(2downto0);H_IN:instd_logic_vector(7downto0);M_IN:instd_logic_vector(7downto0);S_IN:instd_logic_vector(7downto0);Segctr:outstd_logic_vector(7downto0);q_out:outstd_logic_vector(3downtoendcomponentcomponentdisyport(a:instd_lo