组合逻辑电路设计设计05(第五章C-VHDL组合电路-设计实例)

数字电路与逻辑设计一、基于VHDL的组合逻辑分析二、VHDL基本语素及语法三、基于VHDL的组合逻辑设计数字电路与逻辑设计5-3-3基于VHDL的组合逻辑设计一、逻辑抽象分析因果关系，确定输入/输出变量定义逻辑状态的含意（赋值）二、逻辑功能描述：列出真值表，布尔表达式，HDL语言等三、选定电路形式（器件类型）四、根据具体器件进行调整：对逻辑式化简（基本逻辑门）变换（中规模逻辑器件MSI）将HDL语句封装为完整程序代码（PLD）五、画出逻辑电路图，或下载到PLD组合逻辑设计步骤VHDL组合逻辑电路设计要领一、逻辑抽象分析逻辑问题，确定输入、输出逻辑变量；理清输出变量如何随输入变量变化（逻辑关系）；二、VHDL程序代码合成通过VHDL语句的规定语义来勾画输出信号的逻辑行为（输出信号如何随输入信号变化）。（1）三态输出电路（2）数据选择器（3）比较器（4）编码器（5）译码器一、常用组合逻辑电路设计（2）数据选择器8选1MUXlibraryieee;useieee.std_logic_1164.all;entitymux81isPort(D:in

std_logic_vector(0to7);sel:in

std_logic_vector(2downto0);Y:out

std_logic);endmux81;architecture

archmux

ofmux41is

begin

with

sel

select

Y<=D(0)when"000",D(1)when"001",D(2)when"010",D(3)when"011",D(4)when"100",D(5)when"101",D(6)when"110",D(7)whenothers;end

archmux;

中规模集成数据选择器74x151（8选1）中规模集成数据选择器74x151（8选1）应用1中规模集成数据选择器74x151（8选1）应用2中规模集成数据选择器74x151（8选1）应用2（1）三态输出电路

（2）比较器（3）数据选择器（4）编码器（5）译码器一、常用组合逻辑电路设计（1）三态输出电路(1位宽度)AENBEN=1B=A;EN=0B=高阻态libraryieee;useieee.std_logic_1164.all;entitytrioutisport(A:in

std_logic;en:in

std_logic;B:out

std_logic);endtriout;architecturebehaveoftrioutisbegin

B<=Awhenen='1'else

'Z';endbehave;

--注意此处的“Z”要大写；三态输出电路（多位宽度）

A7-A0ENB7-B0EN=1B=A;EN=0B=高阻态88libraryieee;useieee.std_logic_1164.all;entitytrioutisport(A:in

std_logic_vector(7downto0);en:in

std_logic;B:out

std_logic_vector(7downto0));endtriout;architecturebehaveoftrioutisbegin

B<=Awhenen='1'else

"ZZZZZZZZ";

endbehave;

--注意多位时用双引号；（1）三态输出电路

（2）数据选择器（3）比较器（4）编码器（5）译码器一、常用组合逻辑电路设计（3）比较器AGTBALTBAEQBAB如果a>b，输出为：agtb=‘1‘，altb=’0’，aeqb=‘0’;如果a<b，输出为：altb=‘1‘，agtb=’0’，aeqb=‘0’;如果a=b，输出为：aeqb=‘1‘，agtb=’0’，altb=‘0’。Libraryieee;Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;ENTITYcmpabIS

PORT

(A,B:in

std_logic_vector(7downto0); AGTB,ALTB,AEQB:out

std_logic); ENDcmpab;ARCHITECTUREaOFcmpabISBEGIN

aeqb<='1'when

a=belse'0';agtb<='1'whena>belse'0';altb<='1'whena<belse'0';ENDa;ARCHITECTUREbOFcmpabISBEGIN

process(a,b)begin

ifA>Bthenagtb<='1';

elsifA=Bthenaeqb<='1';

elsealtb<='1';

endif;

end

process;ENDb;（1）三态输出电路

（2）比较器（3）数据选择器（4）编码器（5）译码器一、常用组合逻辑电路设计（4）编码器(A普通8-3编码器)I6I7I5I4I3I2I1I0Y2Y1Y08-3编码器I7I6I5I4I3I2I1I0Y2Y1Y01111111000011111101001111110110101111011101111101111100110111111011011111111001111111111LIBRARYieee;USEieee.std_logic_1164.all;ENTITYencoderISPORT(i:IN

BIT_VECTOR(7DOWNTO0);y:OUT

BIT_VECTOR(2DOWNTO0));

ENDencoder;ARCHITECTURErtlOFencoderISBEGINy<="000"wheni="11111110"else"001"wheni="11111101"else"010"wheni="11111011"else"011"wheni="11110111"else"100"wheni="11101111"else"101"wheni="11011111"else"110"wheni="10111111"else"111"wheni="01111111"else

"000";ENDrtl;（4）编码器(Ｂ优先8-3编码器)I6I7I5I4I3I2I1I0Y2Y1Y08-3编码器I7I6I5I4I3I2I1I0Y2Y1Y0XXXXXXX0000XXXXXX01001XXXXX011010XXXX0111011XXX01111100XX011111101X011111111001111111111LIBRARYieee;USEieee.std_logic_1164.all;ENTITYencoderISPORT(i:IN

BIT_VECTOR(7DOWNTO0);y:OUT

BIT_VECTOR(2DOWNTO0));

ENDencoder;ARCHITECTURErtlOFencoderISBEGINy<="000"wheni(0)='0'

else"001"wheni(1)='0'

else"010"wheni(2)='0'

else"011"wheni(3)='0'

else"100"wheni(4)='0'

else"101"wheni(5)='0'

else"110"wheni(6)='0'

else"111"wheni(7)='0'

else"000";ENDrtl;STD_LOGIC类型信号的取值空间。

若A:OUTSTD_LOGIC；则A可赋予‘0’、‘1’、‘Z’、……，形式如下A<='0';

std_logic信号的取值空间{'0',-----Forcing0'1',-----Forcing1'Z',-----HignImpedance'W',-----WeakUnknown'L',-----Weak0;'H',-----Weak1;'U',-----Undefined'X',-----ForcingUnknown

'-',------Don’tCare;}“九值逻辑”

标准逻辑类型对数字逻辑电路的逻辑特性描述更加完整，真实，因此在VHDL程序中，对逻辑信号的定义通常采用标准逻辑类型（1）三态输出电路

（2）比较器（3）数据选择器（4）编码器（5）译码器一、常用组合逻辑电路设计（5）译码器A.3－8译码器LIBRARYieee;USEieee.std_logic_1164.all;ENTITYdecode_3to8ISPORT(a,b,c,G1,G2A,G2B:INSTD_LOGIC;Y:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDdecode_3to8;ARCHITECTURErtlOFdecode_3to8ISSIGNALindata:STD_LOGIC_VECTOR(5DOWNTO0);BEGINindata<=G1&G2A&G2B&c&b&a;y<="11111110"whenindata="100000"else"11111101"whenindata="100001"else"11111011"whenindata="100010"else"11110111"whenindata="100011"else"11101111"whenindata="100100"else"11011111"whenindata="100101"else"10111111"whenindata="100110"else"01111111"whenindata="100111"else"11111111";ENDrtl;译码器（2）译码器B.数码管译码器A3A2A1A0abcdefgLibraryieee;Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;EntitybcdisPort(A:instd_logic_vector(3downto0);Seven

:outstd_logic_vector(6downto0));Endbcd;ArchitectureaofbcdisBeginSeven<="0111111"whenA="0000"else

--0

"0000110"whenA="0001"else

--1

"1011011"whenA="0010"else

--2

"1001111"whenA="0011"else

--3

"1100110"whenA="0100"else

--4

"1101101"whenA="0101"else

--5

"1111101"whenA="0110"else

--6

"0000111"whenA="0111"else

--7

"1111111"whenA="1000"else

--8

"1101111"whenA="1001"else

--9

"0000000";Enda;例1：组合逻辑设计

四舍五入电路输入8421BCD码，输出F。libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entitysswrisport(d:instd_logic_vector(3downto0);y:outstd_logic);endsswr;architecturebehaveofsswrisbeginy<='0'when0<=dandd<5else'1'when5<=dandd<10else'Z';endbehave;例2:设计组合逻辑电路设计一个1bit全加器。输入X,Y,CI输出Z,COlibraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entityfull_bit_adderisport(a,b,ci:instd_logic;y,cout:outstd_logic);endfull_bit_adder;architecturebh1offull_bit_adderisbeginy<=((nota)and(notb)andci)or((nota)and(b)and(notci))or((a)and(notb)and(notci))or((a)and(b)and(ci));cout<=(bandci)or(aandci)or(aandb);endbh1;architecturebh2offull_bit_adderisbeginy<=axorbxorci;cout<=(aandb)or(aandci)or(bandci);endbh2;configurationcon1offull_bit_adderisforbh2endfor;endcon1;例3：四位二进制数转换为BCD码。entitybin2bcdisport(d_bin:instd_logic_vector(3downto0);d_bcd_H,d_bcd_L:outstd_logic_vector(3downto0));endbin2bcd;architectureaa

ofbin2bcdisBegind_bcd_L<=d_binwhend_bin<10else

d_bin+6;d_bcd_H<=“0000”whend_bin<10else

“0001”;endaa;entitybcd2bisport(d:instd_logic_vector(3downto0);Bh,Bl:outstd_logic_vector(3downto0));endbcd2b;architectureaaofbcd2bissignala,b:std_logic_vector(7downto0);begina<="0000"&d;b<=awhend<10elsea+6;Bh<=b(7downto4);Bl<=b(3downto0);endaa;architectureabofbcd2bisbeginBh<="0001"whend>9else"0000";Bl<=d+6whend>9elsed;endab;例4：设计一位BCD码加法器entitybcd_adderisport(d1,d2:instd_logic_vector(3downto0);Bh,Bl:outstd_logic_vector(3downto0));endbcd_adder;architectureaaofbcd_adderissignala,b,t,s:std_logic_vector(7downto0);begina<="0000"&d1;b<="0000"&d2;t<=a+b;s<=twhent<10elset+6;Bh<=s(7downto4);Bl<=s(3downto0);endaa;码制转换设计题：将4位自然二进制数转换为BCD码，并通过数码管显示转换结果。四位二进制码转换为BCD码，并译码显示。

（数码管为共阴极）Libraryieee;Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;EntitybcdisPort(A:instd_logic_vector(3downto0);bcd0,bcd1:outstd_logic_vector(3downto0);seven0,seven1:outstd_logic_vector(6downto0));Endbcd;Architectureaofbcdis

signaltmp:std_logic_vector(3downto0);Beginbcd0<=Awhen(A<10)elseA+6;bcd1<=“0000”when(A<10)else“0001”;tmp<=bcd0;

seven0<="011