数电qutaras-典型电路的设计案例

典型电路设计案例1、计数器设计LIBRARYieee;USEieee.std_logic_1164.ALL;USEieee.std_logic_unsigned.ALL;ENTITYcountISGeneric(n:integer:=3);PORT(clk:inSTD_LOGIC;q:outSTD_LOGIC_vector(n-1downto0));ENDcount;ARCHITECTUREaOFcountISsignaltmp:STD_LOGIC_vector(n-1downto0);BEGINprocess(clk)beginifclk'eventandclk='1'thentmp<=tmp+1;endif;endprocess;q<=tmp;ENDa;an位二进制加法计数器24进制计数器ENQAQBCLKLIBRARYieee;USEieee.std_logic_1164.ALL;USEieee.std_logic_unsigned.ALL;ENTITYcount24ISPORT(en,Reset,clk:inSTD_LOGIC;

qa:outSTD_LOGIC_VECTOR(3DOWNTO0);--个位数计数

qb:outSTD_LOGIC_VECTOR(1DOWNTO0));--十位数计数ENDcount24;ARCHITECTUREa1OFcount24ISBEGINprocess(clk)variabletma:STD_LOGIC_VECTOR(3DOWNTO0);variabletmb:STD_LOGIC_VECTOR(1DOWNTO0);ResetbeginIfReset=‘0‘thentma:="0000";tmb:="00";else

ifclk'eventandclk='1'thenifen='1'theniftma="1001"thentma:="0000";tmb:=tmb+1;--如果个位数为9，个位数清零，十位数加一

elsif

tmb="10"andtma="0011"then

tma:="0000";tmb:="00";--如果十位数为2，个位数为3，个位数十位数均清零

elsetma:=tma+1;--以上条件均不满足，则个位数加一

endif;

endif;endif;endif;qa<=tma;qb<=tmb;将结果输出endprocess;ENDa1;LIBRARYieee;USEieee.std_logic_1164.ALL;USEieee.std_logic_unsigned.ALL;ENTITYcount60ISPORT(en,Reset,clk:inSTD_LOGIC;

qa:outSTD_LOGIC_VECTOR(3DOWNTO0);--个位数计数

qb:outSTD_LOGIC_VECTOR(2DOWNTO0);--十位数计数

rco:OUTSTD_LOGIC);--计数进位ENDcount60;ARCHITECTUREaOFcount60ISBEGINprocess(clk)variabletma:STD_LOGIC_VECTOR(3DOWNTO0);variabletmb:STD_LOGIC_VECTOR(2DOWNTO0);60进制计数器ENQAQBCLKRCOResetbeginIfReset=‘0’thentma:="0000";

tmb:="0000";elseifclk'eventandclk='1'thenifen='1'thenrco<=tmb(2)andtmb(0)andtma(3)andtma(0);--计算是否有进位，即是否计数超过59，超过则有进位，否则无进位

iftma="1001"thentma:="0000";--如果个位数为9，则个位数清零

iftmb="101"thentmb:="000";elsetmb:=tmb+1;endif;

--如果十位数为5，则十位数清零，否则十位数加一

elsetma:=tma+1;--如果个位数不为9，则个位数加一

endif;endif;

endif;endif;qa<=tma;qb<=tmb;将结果输出endprocess;ENDa;2、分频器设计

计数器就是对时钟脉冲计数，同时计数器还是一个分频器。下图为一个3位的计数器的仿真波形图。<1>一个3bits的计数器，它所能计数的范围为0~7（=23-1）。同理，nbits的计数器所能计数范围为0~2n-1。<2>Q0、Q1、Q2的波形频率分别为时钟脉冲信号Clk的1/2、1/4、1/8，由此可以知道，nbits的计数器可获得的最低分频频率为时钟脉冲信号Clk的1/2n。<3>输出信号Q(2downto0)的频率等于信号Q2的频率，信号Q(2downto1)的频率也为信号Q2的频率。由此可以知道，矢量信号的频率为最高位信号的频率。<4>对于4MHz频率信号，若得到1Hz时钟脉冲信号Clk，通过公式f=1/2n可计算出n≈22，即应设计一个22位的计数器。4MHz到1Hz的分频器

LIBRARYieee;USEieee.std_logic_1164.ALL;USEieee.std_logic_unsigned.ALL;ENTITYcountISPORT(clk:inSTD_LOGIC;q:outSTD_LOGIC;ENDcount;ARCHITECTUREaOFcountISsignaltmp:STD_LOGIC_vector(21downto0);Beginprocess(clk)beginifclk'eventandclk='1'thentmp<=tmp+1;endif;endprocess;q<=tmp(21);ENDa;十进制计数器

LIBRARYieee;USEieee.std_logic_1164.ALL;USEieee.std_logic_unsigned.ALL;ENTITYcount10ISPORT(clk:INSTD_LOGIC;

seg:OUTSTD_LOGIC_VECTOR(6DOWNTO0));ENDcount10;ARCHITECTUREa1OFcount10ISsignalsec:STD_LOGIC;signalq:STD_LOGIC_VECTOR(21DOWNTO0);signalnum:STD_LOGIC_VECTOR(3DOWNTO0);BEGINprocess(clk)----get1hzclockpulsebeginifclk'eventandclk='1'thenq<=q+1;endif;sec<=q(21);--get1hzclockpulseendprocess;timing:process(sec)beginifsec'eventandsec='1'thenifnum<9thennum<=num+1;elsenum<="0000";endif;endif;endprocess;B1:block--bcd-7segsBegin--gfedcbaseg<="0111111"whennum=0else"0000110"whennum=1else"1011011"whennum=2else"1001111"whennum=3else"1100110"whennum=4else"1101101"whennum=5else"1111101"whennum=6else"0000111"whennum=7else"1111111"whennum=8else"1101111"whennum=9else"0000000";endblock;ENDa1;3交通灯控制器的设计

设计一个十字路口交通灯控制器，东西、南北方向有红灯、黄灯、绿灯，持续时间分别为45、5、40秒。东西方向b南北方向a十字路口东西方向b南北方向a十字路口交通灯控制器ClkRaYaGaYbRbGb电路框图GA,RBT=40S?NoYesYA,RBT=5S?NoYesRA,GBT=40S?NoYesRA,YBT=5S?NoYes交通灯控制流程图S0S1S2S3LIBRARYieee;USEieee.std_logic_1164.ALL;USEieee.std_logic_unsigned.ALL;ENTITYnclightISPort(clk:instd_logic;

ra,rb,ya,yb,ga,gb:outstd_logic);ENDnclight;Architectureaofnclightistypestateis(S0,S1,S2,S3);signalpresentstate,nextstate:state;signaltmp1,tmp2:integerrange0to40;signaltimeout1,timeout2:std_logic;signalq:std_logic_vector(21downto0);signalsec:std_logic;Begin----get1hzclockpulseprocess(clk)beginifclk'eventandclk='1'thenq<=q+1;endif;sec<=q(21);--get1hzclockpulseendprocess;timing:process(sec)beginifsec'eventandsec='1'then

iftmp1=39thentimeout1<='1';timeout2<='0';tmp1<=0;elseiftimeout1='1'then

iftmp2=4thentimeout2<='1';timeout1<='0';tmp2<=0;elsetmp2<=tmp2+1;endif;

elsetmp1<=tmp1+1;endif;endif;

endif;endprocess;changestate:process(presentstate)Begincasepresentstateis

whenS0=>iftimeout1='0'then

nextstate<=s0;

ra<='0';

ya<='0';ga<='1';

rb<='1';

yb<='0';gb<='0';elsenextstate<=s1;endif;whenS1=>iftimeout2='0'then

nextstate<=s1;

ra<='0';ya<='1';

ga<='0';

rb<='1';yb<='0';gb<='0';elsenextstate<=s2;endif;whenS2=>iftimeout1='0'then

nextstate<=s2;

ra<='1';

ya<='0';ga<=‘1';

rb<='0';yb<='0';gb<='1';

elsenextstate<=s3;endif;whenS3=>iftimeout2='0'then

nextstate<=s3;

ra<='1';

ya<='0';ga<='0';

rb<='0';yb<='1';

gb<='0';elsenextstate<=s0;endif;

whenothers=>nextstate<=s0;timeout1<='0';timeout2<='0';

endcase;endprocess;enda;4、数控分频器设计

对于一个加法计数器，装载不同的计数初始值时，会有不同频率的溢出输出信号。计数器溢出时，输出‘1’电平，同时溢出时的‘1’电平反馈给计数器的输入端作为装载信号；否则输出‘0’电平。Libraryieee;Useieee.std_logic_1164.all;EntityspeakerisPort(

clk:instd_logic;

Freq_num:inintegerrange0to2047；--16#7FF#speaker:outstd_logic);Endspeaker;Architecturea1ofspeakerissignalpower_speaker:std_logic;beginProcess(clk)variablecount11bit:integerrange0to2047;Beginifclk'eventandclk='1'thenifcount11bit=2047thencount11bit:=Freq_num;

power_speaker<='1';Elsecount11bit:=count11bit+1;

power_speaker<='0';endif;endif;endprocess;--将输出再进行2分频，将脉冲展宽，以使扬声器有足够功率发音process(power_speaker)variablecount2bit:std_logic;Beginifpower_speaker'eventandpower_speaker='1'then

count2bit:=notcount2bit;ifcount2bit='1'thenspeaker<='1';elsespeaker<='0';endif;endif;endprocess;Enda1;C调音阶频率表

音阶频率/Hz音阶频率/Hz音阶频率/Hz1661.227830.61415.311479.986739.99370.001318.525659.33329.631174.664587.33293.671108.733554.37277.19987.762493.88246.94880.001440.00220.00参考代码表clk=1MHz计数器的模为2048

音调音符1234567初始值高1730175017701790181518301930中1410149015601600162216501690低77391210361116119712901372次低100200300400500600700音乐演奏电路

35

635—65

312—设计框图数控分频器扬声器驱动电路扬声器Freq_numClk1MHz分频器4Hz16进制计数器ROM模块SpeakerIndexLibraryieee;Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;EntitytoneisPort(index:inintegerrange0to16;tone:outintegerrange0to16#7FF#);Endtone;Architecturea1oftoneisBeginprocess(index)Begin35

635—65

312—caseindexiswhen0=>

tone<=1560;when1=>

tone<=1622;when2=>

tone<=1650;when3=>

tone<=1560;when4=>

tone<=1622;when5=>

tone<=1622;when6=>

tone<=1622;when7=>

tone<=1622;

when8=>

tone<=1650;when9=>

tone<=1622;when10=>tone<=1560;when11=>tone<=1410;when12=>tone<=1490;when13=>tone<=1490;when14=>tone<=1490;when15=>tone<=1490;

whenothers=>tone<=2047;Endcase;Endprocess;Enda1;35

635—65

312—音调音符1234567初始值高1730175017701790181518301930中1410149015601600162216501690低77391210361116119712901372次低100200300400500600700Libraryieee;Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;EntitytopisPort(clk:instd_logic;spkout:outstd_logic);Endtop;Architecturea1oftopiscomponenttonePort(index:inintegerrange0to16;tone:outintegerrange0to16#7FF#);endcomponent;componentspeakerPort(clk:instd_logic;

Freq_in:inintegerrange0to16#7FF#;speaker:outstd_logic);endcomponent;signalindex1:integerrange0to16;signaltone2:integerrange0to16#7FF#;signalck4:std_logic;beginprocess(clk)variableq:std_logic_vector(17downto0);Beginifclk'eventandclk='1'thenq:=q+1;

endif;ck<=q(17);endprocess;process(ck)Beginifck'eventandck='1'thenifindex1=15thenindex1<=0;elseindex1<=index1+1;

endif;endif;endprocess;u1:toneportmap(index1,tone2);u2:speakerportmap(clk,tone2,spkout);Enda1;例2：用lpm_rom兆函数模块实现七段码显示0-F。

IP核的使用（提高电路设计效率的有效方法）

LPM宏单元库分为：

门单元函数，如：lpm_and，lpm_mux…

算术运算函数，如：lpm_add_sub，

lpm_mult

存贮函数，如：lpm_ff，lpm_rom…

七段显示译码电路七段码显示:abcdefg1.七段译码关系表如下：

a[3..0] a,b,c,d,e,f,g 0 1,1,1,1,1,1,