文稿参考-调试lcd屏sn65dsi

ZHCSAT9D–SEPTEMBER2012–REVISEDDECEMBER查询样品执行MIPI®®D-PHY版本1.00.00物理层前端 1.8V主VCC电显示串行接口(DSI)版本 单通道DSI在每个通道上可针对1条，2 LVDS输出电压摆幅、共模和MIPI®超低功耗状态条，3条或4条D-PHY数据信道进行配置，每信 (ULPS)支持 针对简化印刷电路板(PCB)走线的LVDS通道支持格式为RGB666和RGB888的18比特每 素(bpp)和24bppDSI数据 静电放电(ESD)额定值±2kV（模型在具有精简消隐的18bpp和24bpp色彩时，最大 分辨率高达60fpsWUXGA1920x1200。在 (PBGA)(ZQE)封装内18bpp和24bpp时适用于60fps1366x768 温度范围：-40°C至1280xPRODUCTFlatlink™针对单链路LVDS的输 PRODUCT支持单通道DSI至单链路LVDS运行模 LVDS输出时钟范围为25MHz至 外部基准时钟(REFCLK)供源SN65DSI83DSI至FlatLink™桥特有一个单通道MIPI®D-PHY前端配置，此配置中在每个通道上具有4条信道，每条信道的运行速率高达1Gbps；最大输出带宽4Gbps。此桥MIPI®DSI18bppRGB666和时钟上的FlatLink™兼容LVDS输出，从而提供一个单链路LVDS，每条链路具有4条数据信道。SN65DSI8360WUXGA1920x1200（24bpp）18bpp和24bpp60fps1366x7681280x800DSILVDS接口间的数据流性，其中包括低摆幅LVDS输出以及MIPI®定义的超低功耗状态(ULPS)支持。Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddierstheretoappearsattheendofthisdatasheet.FlatlinkisatrademarkofTexasMIPIisaregisteredtrademarkofArasanChipSystems,Copyright©2012,TexasInstrumentsAllothertrademarksareCopyright©2012,TexasInstrumentsPRODUCTPREVIEWinformationconcernsproductsintheformativeordesignphaseofdevelopment.Characteristicdataotherspecificationsaredesigngoals.TexasInstruments EnglishDataSheet:therighttochangeordiscontinuetheseproductswithoutThesedeviceshavelimitedbuilt-inESDprotection.TheleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoamduringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates.DEVICEFUNCTIONALBLOCKDSIPACKETDSIPACKETLVDSDATALANEDATALANE(CircuitsameasDATALANECLOCKCLK DATALANE(CircuitsameasDATALANE(CircuitsameasDATALANE

PRODUCTPRODUCT(TOPVIEW)987654321ABCDEFGHJPRODUCTTominimizethepowersupplynoisefloor,providegooddecouplingneartheSN65DSI83powerpins.Theuseoffourceramiccapacitors(2x0.1μFand2x0.01μF)providesgoodperformance.Attheleast,itis mendedtoinstallone0.1μFandone0.01μFcapacitorneartheSN65DSI83.ToavoidlargecurrentloopsandtracePRODUCTPINDA0P,H3,LVDSInput(HS)CMOSInput(LS)MIPI®D-PHYChannelADataLane0;datarateupto1DA1P,H4,MIPI®D-PHYChannelADataLane1;datarateupto1DA2P,H6,MIPI®D-PHYChannelADataLane2;datarateupto1DA3P,H7,MIPI®D-PHYChannelADataLane3;datarateupto1H5,MIPI®D-PHYChannelAClockLane;operatesupto500B3,A3,B4,B5,A5,B6,B7,A7,C2,D2,D1,F2,F1,G2,G1,E2,NoThesepinsshouldnotbeconnectedtoanysignal,powerorA_Y0P,C8,LVDSFlatLink™ChannelALVDSDataOutputA_Y1P,D8,FlatLink™ChannelALVDSDataOutputA_Y2P,E8,FlatLink™ChannelALVDSDataOutputA_Y3P,G8,FlatLink™ChannelALVDSDataOutput3.A_Y3PandA_Y3NshallbeleftNCfor18bpppanels.F8,FlatLink™ChannelALVDS.Thispinshouldbeleftunconnectedfornormal.ThispinshouldbeleftunconnectedfornormalPRODUCTPINFUNCTIONSPRODUCTLocalI2CInterfaceTargetAddressSelect.SeeTable2.Innormaloperationthispinisaninput.WhentheADDRpinisprogrammedhigh,itshouldbetiedtothesame1.8VpowerrailswheretheSN65DSI83VCC1.8Vpowerrailispullup(Failsafe)ChipEnableandReset.Deviceisreset(shutdown)whenENisOptionalExternalReferenceClockforLVDSPixelClock.IfanExternalReferenceClockisnotused,thispinshouldbepulledtoGNDwithanexternalresistor.ThesourceofthereferenceclockshouldbeplacedascloseaspossiblewithaseriesresistornearthesourcetoreduceEMI.LocalI2CInterfaceOpenDrainLocalI2CInterfaceBi-directionalDataCMOSInterruptE4,F4,F5,PowerReferenceE6,F6,J21.8VPower1.1VOutputfromVoltageRegulator.Thispinmusthavea1µFexternalcapacitortoGND.ORDERINGPARTPARTPACKAGE/SHIP64-BallPBGA, UMoveroperatingfree-airtemperaturerange(unlessotherwiseSupplyVoltage-VInputVoltageCMOSInput-VDSIInptTerminals(DAxP/N,DBx-VStorage-ElectrostaticHumanBodyModelCharged-devicemodelVStressesthoselistedunderabsoluteumratingsmaycausepermanentdamagetothedevice.Thesearestressratingsonlyandfunctionaloperationofthedeviceattheseoranyconditionsthoseindicatedunder mendedoperatingconditionsisnotimplied.Exposuretoabsolute-um-ratedconditionsforextendedperiodsmayaffectdevicereliability.TestedinaccordancewithJEDECStandard22,TestMethodA114-TestedinaccordancewithJEDECStandard22,TestMethodC101-THERMALTHERMALZQE64Junction-to-ambientthermalJunction-to-case(top)thermalJunction-to-boardthermalJunction-to-topcharacterizationJunction-to-boardcharacterizationJunction-to-case(bottom)thermal有关传统和新的热度量的信息，请参阅IC封装热度量应用报告，SPRA953MENDEDOPERATINGPRODUCToveroperatingfree-airtemperaturerange(unlessotherwisePRODUCTVCCPowerVSupplynoiseonanyVCCVOperatingfree-air-CaseDSIinputpinvoltage-LocalI2CinputDSIHSclockinputDSIHSdatatoclocksetupUIDSIHSdatatoclockholdtime;seeFigureLVDSoutputdifferentialΩTheunitinterval(UI)isonehalfoftheperiodoftheHSclock;at500MHztheminimumsetupandholdtimeis150PRODUCTPRODUCTELECTRICALoveroperatingfree-airtemperaturerange(unlessotherwiseTESTLow-levelcontrolsignalinput0.3xVHigh-levelcontrolsignalinput0.7xHigh-leveloutputIOH=–4Low-leveloutputIOL=4InputfailsafeleakageVCC=0;VCC(PIN)=1.8HighlevelinputAnyinputLowlevelinputHigh-impedanceoutputAnyoutputShort-circuitoutputAnyoutputdrivingGNDDeviceactiveSeeDevicestandbyAlldataandclocklanesareinultra-lowpowerstate(ULPS)ShutdownEN=ENcontrolinputMIPIDSIVIH-LPreceiverinputhighseeFigureVIL-LPreceiverinputlowHSdifferentialinputHSdifferentialinputvoltageVIL-LPreceiverinputlowthreshold;ultra-lowpowerstate(ULPS)VCM-HScommonmodevoltage;steady-ΔVCM-includingsymboldeltaandinterferenceVIH-HSsingle-endedinputhighseeFigureVIL-HSsingle-endedinputlow-VTERM-voltage(bothDpANDDnapplytoTerminationisswitchedsimultaneousforDnandDpRDIFF-HSmodedifferentialinputΩAlltypicalvaluesareatVCC=1.8VandTA=SN65DSI83:SINGLEChannelDSItoSINGLEChannelDSI,1280xnumberofLVDSlanes=3datalanes+1CLKnumberofDSIlanes=4datalanes+1CLKLVDSCLKOUT=DSICLK=RGB888,umvaluesareatVCC=1.95VandTA=ELECTRICALCHARACTERISTICSPRODUCToveroperatingfree-airtemperaturerange(unlessotherwisePRODUCTTESTFLATLINKLVDSSteady-statedifferentialoutputvoltageforA_YxP/NandB_YxP/NCSR100ΩnearendCSR100ΩnearendCSR100ΩnearendCSR100ΩnearendCSR200ΩnearendCSR200ΩnearendCSR200ΩnearendCSR200ΩnearendSteady-statedifferentialoutputvoltageforA_CLKP/NandB_CLKP/NCSR100ΩnearendCSR100ΩnearendCSR100ΩnearendCSR100ΩnearendCSR200ΩnearendCSR200ΩnearendCSR200ΩnearendCSR200ΩnearendChangeinsteady-statedifferentialoutputvoltagebetweenoppositebinarystatesRL=voltage(3)CSR0x19.6=1andCSR0x1B.6=seeFigure1VCSR0x19.6=0,seeFigureseeFigurePull-downfordisabledLVDS1TestedatVCC=1.8V,TA=-40°CforMIN,TA=25°CforTYP,TA=85°CforPRODUCTPRODUCTSWITCHINGoveroperatingfree-airtemperaturerange(unlessotherwiseTESTDSILPglitchsuppressionpulseOutputclockHigh-leveloutputclock(CLK)pulse4/7Delaytime,CLK↑to1stserialbittc=6.49Inputclockjitter<25ps-Delaytime,CLK↑to2ndserialbit1/7tc–1/7tc+Delaytime,CLK↑to3rdserialbit2/7tc–2/7tc+Delaytime,CLK↑to4thserialbit3/7tc–3/7tc+Delaytime,CLK↑to5thserialbit4/7tc–4/7tc+Delaytime,CLK↑to6thserialbit5/7tc–5/7tc+Delaytime,CLK↑to7thserialbit6/7tc–6/7tc+Differentialoutputrise-seeFigureDifferentialoutputfall-EN,ULPS,EnabletimefromENortc(o)=12.91Disabletimetostandby;seeFigureResetREFCLKFreqeuncy.Supportedfrequencies:25MHz-154MHztr,REFCLKriseandfallsREFCLKPeak-to-PeakPhaseREFCLKDutyREFCLKorDSICLK(DACP/N,SSCenabledInputCLKcenterspreaddepthModulationFrequencyAlltypicalvaluesareatVCC=1.8VandTA=ForEMIreductionpurpose,SN65DSI83supportsthecenterspreadingoftheLVDSCLKoutputthroughtheREFCLKorDSICLKinput.ThecenterspreadCLKinputtotheREFCLKorDSICLKispassedthroughtotheLVDSCLKoutputA_CLKP/Nand/orB_CLKP/N.Figure1.DSIHSModeReceiverTimingLP-InputLP-InputHS-CommonHS-CommonLP-Input

Vih-Vcm-LowPower(LP)Mode

HighSpeed(HS)ModeFigure2.DSIReceiverVoltage49.9±1%(200PRODUCT 0Figure3.TestLoadandVoltageDefinitionsforFlatLink™t0-

Figure4.SN65DSI83FlatLink™Timing

1.65-1.95

Treset(Reset

1 InitseqInitseq

seqInitseq5InitseqTheInitializationsequencecanbefoundat mendedInitializationSequencesectionofthis.The“Initseq*”correspondstothesequencenumberinthe mendedInitializationSequencesection. esactivealongwithCHALVDSdatalanes0-2afterPLLlockeventoccursandCLKsource(REF_CLKorDSIHSCLK)isactive(Initseq7).OtherLVDSCLK/datalanesstaylowuntiltheyareconfiguredtobeenabledincorrespondingCSRsTheLP11toHStransitiontothedatalanesandtheCLKlaneMUSTbedoneperthetimingrequirementsspecifiedintheMIPI®D-PHYSpecification.Figure5.ShutdownandRESETTimingDefinitionWhileVCCisDSI

ULPS(LP00

PRODUCTSeetheULPSsectionofthedatasheetfortheULPSentryandexitPRODUCTULPSentryandexitprotocolandtimingrequirementsmustbemetperMIPI®DPHYFigure6.ULPSTimingDEVICEResetWhenENisde-asserted(low),theSN65DSI83isinSHUTDOWNorRESETstate.Inthisstate,CMOSinputsareignored,theMIPI®D-PHYinputsaredisabledandoutputsarehighimpedance.ItiscriticaltotransitiontheENinputfromalowtoahighlevelaftertheVCCsupplyhasreachedtheminimumoperatingvoltageasshowninFigure7.ThisisachievedbyacontrolsignaltotheENinput,orbyanexternalcapacitorconnectedbetweenENandGND.PRODUCTPRODUCTFigure7.ColdStartVCCRampupto

Whenimplementingtheexternalcapacitor,thesizeoftheexternalcapacitordependsonthepoweruprampoftheVCCsupply,whereaslowerramp-upresultsinalargervalueexternalcapacitor.SeethelatestreferenceschematicfortheSN65DSI83deviceand,orconsiderapproximay200nFcapacitorasareasonablefirstestimateforthesizeoftheexternalcapacitor.BothENimplementationsareshowninFigure8andFigureR=200CCFigure8.ExternalCapacitorControlled Figure9.ENInputfromActiveWhentheSN65DSI83isresetwhileVCCishigh,theENpinmustbeheldlowforatleast10msbeforebeingassertedhighasshowninFigure5tobesurethatthedeviceisproperlyreset.TheDSIlanesincludingtheCLKlanesMUSTbedriventoLP11whilethedeviceisinresetuntiltheENpinisassertedhighperthetimingshowninFigure5.PRODUCTPRODUCTmendedInitializationItis mendedtousethefollowinginitializationsequencefortheSN65DSI83.AlsoseetoFigure7.InitializationSequenceInitAfterpowerisappliedandstable,allDSIInputlanesincludingDSICLK(DAxP/N,DBxP/N)MUSTbedriventoLP11state.InitAsserttheENInitWaitfor1msfortheinternalvoltageregulatortoInitInitializeallCSRregisterstotheirappropriatevaluesbasedontheimplementation(TheSN65DSI83isnotfunctionaluntiltheCSRregistersareinitialized)InitStarttheDSIInitSetthePLL_ENbit(CSRInitWaitforthePLL_LOCKbittobeset(CSRInitSettheSOFT_RESETbit(CSRClockConfigurationsandTheFlatLink™LVDSclockmaybederivedfromtheDSIchannelAclock,orfromanexternalreferenceclocksource.WhentheMIPI®D-PHYchannelAHSclockisusedastheLVDSclocksource,theD-PHYclocklanemustoperateinHSfree-running(continuous)mode;thisfeatureeliminatestheneedforanexternalreferenceclockreducingsystemcostsThereferenceclocksourceisselectedbyHS_CLK_SRC(CSR0x0A.0)programmedthroughthelocalI2Cinterface.Ifanexternalreferenceclockisselected,itismultipliedbythefactorinREFCLK_MULTIPLIER(CSR0x0B.1:0)togeneratetheFlatLink™LVDSoutputclock.Whenanexternalreferenceclockisselected,itmustbebetween25MHzand154MHz.IftheDSIchannelAclockisselected,itisdividedbythefactorinDSI_CLK_DIVIDER(CSR0x0B.7:3)togeneratetheFlatLink™LVDSoutputclock.Additionally,LVDS_CLK_RANGE(CSR0x0A.3:1)andCH_DSI_CLK_RANGE(CSR0x12)mustbesettothefrequencyrangeoftheFlatLink™LVDSoutputclockandDSIChannelAinputclockrespectivelyfortheinternalPLLtooperatecorrectly.Afterthesesettingsareprogrammed,PLL_EN(CSR0x0D.0)mustbesettoenabletheinternalPLL.LVDSOutputTheSN65DSI83processesDSIpacketsandproduces datadriventotheFlatLink™LVDSinterfaceinanindustrystandardformat.Single-LinkLVDSissupportedbytheSN65DSI83.Duringconditionssuchasthedefaultcondition,andsomesynchronizationperiods,whereno streamdataispassingfromtheDSIinputtotheLVDSoutput,theSN65DSI83transmitszerovaluepixeldataontheLVDSoutputswhilemaintainingtransmissionoftheverticalsyncandhorizontalsyncstatus.Figure10illustratesaSingle-LinkLVDS18bppFigure11illustratesaSingle-Link24bppapplicationusingFormat2,controlledbyCHA_24BPP_FORMAT1(CSR0x18.1).IndataFormat2,thetwoMSBpercoloraretransferredontheY3P/NLVDSlane.Figure12illustratesa24bppSingle-LinkapplicationusingFormat1.IndataFormat1,thetwoLSBpercoloraretransferredontheY3P/NLVDSlane.Figure13illustratesaSingle-LinkLVDSapplicationwhere24bppdataisreceivedfromDSIandconvertedto18bppdatafortransmissiontoan18bpppanel.ThisapplicationisconfiguredbysettingCHA_24BPP_FORMAT1(CSR0x18.1)to‘1’andCHA_24BPP_MODE(CSR0x18.3)to‘0’.Inthisconfiguration,theSN65DSI83willnottransmitthe2LSBpercolorsincetheY3P/NLVDSlaneisdisabled.Note:Figure10,Figure11,Figure12,andFigure13onlyillustrateafewexampleapplicationsfortheSN65DSI83.Otherapplicationsarealsosupported.cycle‘n-cyclecycle‘n-cycle DE=DataEnable;A_Y3P/NareOutputFigure10.FlatLink™OutputData;Single-Link18cyclecycle‘n-cycle0PRODUCTDE=DataPRODUCTFigure11.FlatLink™OutputData(Format2);Single-Link24cyclecycle‘n-cycle DE=DataFigure12.FlatLink™OutputData(Format1);Single-Link24PRODUCTPRODUCTcyclecyclecyclecycle‘n-cycle DE=DataEnable;A_Y3P/NareOutputLow;A_Y3P/NareOutputFigure13.FlatLink™OutputData(Format1);24bpptoSingle-Link18bppDSILaneTheSN65DSI83supportsfourDSIdatalanes,andmaybeconfiguredtosupportone,two,orthreeDSIdatalanesperchannel.UnusedDSIinputpinsontheSN65DSI83shouldbeleftunconnectedordriventoLP11state.ThebytesreceivedfromthedatalanesaremergedinHSmodetoformpacketsthatcarrythe stream.DSIdatalanesarebitandbytealigned.HSBYTESTRANSMITTED(n)ISINTEGERMULTIPLEHSBYTESTRANSMITTED(n)ISINTEGERMULTIPLEOFLANE BYTE BYTE BYTE BYTEn- LANE BYTE BYTE BYTE LANE BYTE BYTE6BYTE BYTEn- LANE BYTE BYTE7BYTE BYTEn- HSBYTESTRANSMITTED(n)IS1LESSTHANINTEGERMULTIPLEOF4LANE BYTE BYTE BYTE BYTEn- LANE BYTE BYTE BYTE LANE BYTE BYTE6BYTE BYTEn- LANE BYTE BYTE7BYTE HSBYTESTRANSMITTED(n)IS2LESSTHANINTEGERMULTIPLEOFLANE BYTE BYTE BYTE BYTEn- LANE BYTE BYTE BYTE LANE BYTE BYTE6BYTE LANE BYTE BYTE7BYTE HSBYTESTRANSMITTED(n)IS3LESSTHANINTEGERMULTIPLEOF4LANE0 BYTE0 BYTE4 BYTE8 BYTEn-1 LANE BYTE BYTE BYTE LANE BYTE BYTE6BYTE LANE BYTE BYTE7BYTE LANE BYTE BYTE BYTE LANE BYTE BYTE BYTE LANE BYTE BYTE BYTE HSBYTESTRANSMITTED(n)IS1LESSTHANINTEGERMULTIPLEOF3LANE BYTE BYTE BYTE LANE BYTE BYTE BYTE LANE BYTE BYTE BYTE HSBYTESTRANSMITTED(n)IS2LESSTHANINTEGERMULTIPLEOFLANE BYTE BYTE BYTE LANE BYTE BYTE BYTE LANE BYTE BYTE BYTE LANEBYTE BYTE BYTE LANEBYTE BYTE3BYTE HSBYTESTRANSMITTED(n)IS1LESSTHANINTEGERMULTIPLEOFLANEBYTE BYTE BYTE LANEBYTE BYTE BYTEPRODUCT4DSIDataLaneConfiguration2DSIDataLaneFigure14.SN65DSI83DSILaneMergingDSIPixelStreamTheSN65DSI83processes18bpp(RGB666)and24bpp(RGB888)DSIpacketsoneachchannelasshowninFigure15,Figure16,andFigure17.1 2 1 WORDCOUNT 2DATATYPEVIRTUALWORD18bppLooselyPackedPixelStream(VariableSizePayload)CRC1

1 1 1 1

1 1

1 1PRODUCTPRODUCT00172727272727272727FirstPixelinSecondPixelinThirdPixelinVariableSizePayload(ThreePixelsPerNineBytesofFigure15.18bpp(LooselyPacked)DSIPacket1 2 1 WORDCOUNT 2DATATYPEVIRTUALWORD18bppPackedPixelStream(VariableSizePayload)CRC11111111111110567370175673701756737017R5G5BB5R5G5BB5R5G5BB5R5G5BBFirstPixelinSecondPixelinThirdPixelinFourthPixelin6-VariableSizePayload(FourPixelsPerNineBytesofFigure16.18bpp(TightlyPacked)DSIPacket1 2 1 WORDCOUNT 2DATATYPEVIRTUALWORD24bppPackedPixelStream(VariableSizePayload)CRCPacket Packet Packet1Byte1Byte1Byte1Byte1Byte1Byte1Byte1Byte1007R77G7B77R77G7B77R77G7B7B7B78-bits8-bitsFirstPixelinSecondPixelinThirdPixelinPRODUCTVariableSizePayload(ThreePixelsPerNineBytesofPRODUCTFigure17.24bppDSIPacket TransmissionTheSN65DSI83supportsburst modeandnon-burst modewithsynceventsorwithsyncpulsespackettransmissionasdescribedintheDSIspecification.Theburstmodesupports pressedpixelstreampacketsthatleaveaddedtimeperscanlineforpowersavingsLPmode.TheSN65DSI83requiresatransitiontoLPmodeonceperframetoenablePHYsynchronizationwiththeDSIhostprocessor;however,forarobustandlow-powerimplementation,thetransitiontoLPmodeis mendedoneveryline.Figure18illustratestheDSI transmissionappliedtoSN65DSI83applications.Inallapplications,theLVDSoutputratemustbelessthanorequaltotheDSIinputrate.Thefirstlineofa frameshallstartwithaVSSpacket,andallotherlinesstartwithVSEorHSS.Thepositionofthesynchronizationpacketsintimeisofutmostimportancesincethishasadirectimpactonthevisualperformanceofthedisplaypanel;thatis,thesepacketsgeneratetheHSandVS(horizontalandverticalsync)signalsontheLVDSinterfaceafterthedelayprogrammedintoCHA_SYNC_DELAY_LOW/HIGH(CSR0x28.7:0and0x29.3:0).AsrequiredintheDSIspecification,theSN65DSI83requiresthatpixelstreampacketscontainanintegernumberofpixels(i.e.endonapixelboundary);itis mendedtotransmitanentirescanlineononepixelstreampacket.Whenascanlineisbrokenintomultiplepackets,inter-packetlatencyshallbeconsideredsuchthatthe pipeline(ie.pixelqueueorpartiallinebuffer)doesnotrunempty(i.e.under-run);duringscanlineprocessing,ifthepixelqueuerunsempty,theSN65DSI83transmitszerodata(18’b0or24’b0)ontheLVDSWhentheHSclockisusedasasourcefortheLVDSpixelclock,theLPmodetransitionsapplyonlytothedatalanes,andtheDSIclocklaneremainsintheHSmodeduringtheentiretransmission.TheDSI83doesnotsupporttheDSIVirtualChannelcapabilityorreversedirection(peripheraltoprocessor)transmissions.tttttttChannel

Verticalsync/PRODUCTPRODUCTandNullPacketsDSINullPacket,BlankingPacket,oratransitiontoLPModeLineLVDSTransferandNullPacketsDSINullPacket,BlankingPacket,oratransitiontoLPModeLineLVDSTransfertHSVSDEPixelStream0x000VerticalBlankingPeriodLVDSTransferttChannelChannelttHS HS(ttVS VS(DE DE(VSissignaledforaprogrammablenumberoflines(t)andisassertedwhenHSisassertedforthefirstlineoftheframe.VSisde-assertedwhenHSisassertedafterthenumberoflinesprogrammedhasbeenreached.TheillustrationshowsVSactivelowDEisassertedwhenactivepixeldataistransmittedonLVDS,andpolarityissetindependenttoHS/VS.TheillustrationshowsDEactivehighAfterthelastpixelinanactivelineisoutputtoLVDS,theLVDSdataisoutputFigure18.DSIChannelTransmissionandTransferTheSN65DSI83supportstheMIPI®definedultra-lowpowerstate(ULPS).WhilethedeviceisintheULPS,theCSRregistersareaccessibleviaI2Cinterface.ULPSsequenceshouldbeissuedtoallactiveDSICLKand/orDSIdatalanesoftheenabledDSIChannelsfortheSN65DSI83entertheULPS.TheFollowingsequenceshouldbefollowedtoenterandexittheULPS.HostissuesaULPSentrysequencetoallDSICLKanddatalanesWhenhostisreadytoexittheULPSmode,hostissuesaULPSexitsequencetoallDSICLKanddatalanesthatneedtobeactiveinnormaloperation.WaitforthePLL_LOCKbit(CSR0x0A.7)tobeSettheSOFT_RESETbit(CSRDeviceresumesnormal streamingresumesontheLVDSPatternTheSN65DSI83supportsapatterngenerationfeatureonLVDSChannels.ThisfeaturecanbeusedtotesttheLVDSoutputpathandLVDSpanelsinasystemplatform.ThepatterngenerationfeaturecanbeenabledbysettingtheCHA_TEST_PATTERNbitataddress0x3C.NoDSIdataisreceivedwhilethepatterngenerationfeatureisenabled.PRODUCTPRODUCTTable Addr.RegisterPRODUCTPRODUCTLocalI2CInterfaceTheSN65DSI83localI2CinterfaceisenabledwhenENisinputhigh,accesstotheCSRregistersissupportedduringultra-lowpowerstate(ULPS).TheSCLandSDAterminalsareusedforI2CclockandI2Cdatarespectively.TheSN65DSI83I2Cinterfaceconformstothetwo-wireserialinterfacedefinedbytheI2CBusSpecification,Version2.1(January2000),andsupportsfastmodetransfersupto400kbps.ThedeviceaddressbyteisthefirstbytereceivedfollowingtheSTARTconditionfromthemasterdevice.The7bitdeviceaddressforSN65DSI83isfactorypresetto010110XwiththeleastsignificantbitbeingdeterminedbytheADDRcontrolinput.Table2clarifiestheSN65DSI83targetaddress.Table2.SN65DSI83I2CTargetAddressDescription(1)SN65DSI83I2CTARGETBIT7BITBITBITBITBITBITBIT0010110WhenADDR=1,AddressCycleis0x5A(Write)and0x5BWhenADDR=0,AddressCycleis0x58(Write)and0x59ThefollowingprocedureisfollowedtowritetotheSN65DSI83I2CThemasterinitiatesawriteoperationbygeneratingastartcondition(S),followedbytheSN65DSI837-bitaddressandazero-value“W/R”bittoindicateawritecycle.TheSN65DSI83acknowledgestheaddressThemasterpresentsthesub-address(I2CregisterwithinSN65DSI83)tobewritten,consistingofonebyteofdata,MSB-first.TheSN65DSI83acknowledgesthesub-addressThemasterpresentsthefirstbyteofdatatobewrittentotheI2CTheSN65DSI83acknowledgesthebyteThemastermaycontinuepresentingadditionalbytesofdatatobewritten,witheachbytetransfercompletingwithanacknowledgefromtheSN65DSI83.ThemasterterminatesthewriteoperationbygeneratingastopconditionThefollowingprocedureisfollowedtoreadtheSN65DSI83I2CThemasterinitiatesareadoperationbygeneratingastartcondition(S),followedbytheSN65DSI837-bitaddressandaone-value“W/R”bittoindicateareadcycle.TheSN65DSI83acknowledgestheaddressTheSN65DSI83transmitthecontentsofthememoryregistersMSB-firststartingatregister00h.IfawritetotheSN65DSI83I2Cregisteroccurredpriortotheread,thentheSN65DSI83willstartatthesub-addressspecifiedinthewrite.TheSN65DSI83willwaitforeitheranacknowledge(ACK)oranot-acknowledge(NACK)fromthemasteraftereachbytetransfer;theI2Cmasteracknowledgesreceptionofeachdatabytetransfer.IfanACKisreceived,theSN65DSI83transmitsthenextbyteofThemasterterminatesthereadoperationbygeneratingastopconditionThefollowingprocedureisfollowedforsettingastartingsub-addressforI2CThemasterinitiatesawriteoperationbygeneratingastartcondition(S),followedbytheSN65DSI837-bitaddressandazero-value“W/R”bittoindicateawritecycleTheSN65DSI83acknowledgestheaddressThemasterpresentsthesub-address(I2CregisterwithinSN65DSI83)tobewritten,consistingofonebyteofdata,MSB-first.TheSN65DSI83acknowledgesthesub-addressThemasterterminatesthewriteoperationbygeneratingastopconditionControlandStatusRegistersManyoftheSN65DSI83functionsarecontrolledbytheControlandStatusRegisters(CSR).AllCSRregistersareaccessiblethroughthelocalI2Cinterface.SeethefollowingtablesfortheSN65DSI83CSRdescriptions.orundefinedbitfieldsshouldnotbemodified.Otherwise,thedevicemayoperateincorrectly.Table3.CSRBitFieldDefinitions–ID0x00–Addresses0x08-0x00={0x01,0x20,0x20,0x20,0x44,0x53,0x49,0x38,(1)RO=ReadOnly;RW=Read/Write;RW1C=Read/Write‘1’toClear;WO=WriteOnly(readsreturnundeterminedPRODUCTTable4.CSRBitFieldDefinitions–ResetandPRODUCTACCESS0Thisbitautomaticallyclearswhensetto‘1’andreturnszeroswhenread.ThisbitmustbesetaftertheCSR’sareupdated.ThisbitmustalsobesetaftermakinganychangestotheDISclockrateorafterchangingbetweenDSIburstandnon-burstmodes.–Noaction–ResetdevicetodefaultconditionexcludingtheCSR07–PLLnotlocked–PLL0ThisfieldselectsthefrequencyrangeoftheLVDSoutputclock.000–25MHz≤LVDS_CLK<37.5MHz001–37.5MHz≤LVDS_CLK<62.5010–62.5MHz≤LVDS_CLK<87.5011–87.5MHz≤LVDS_CLK<112.5100–112.5MHz≤LVDS_CLK<137.5101–137.5MHz≤LVDS_CLK≤154MHz11011100–LVDSpixelclockderivedfrominputREFCLK1–LVDSpixelclockderivedfromMIPID-PHYchannelAHScontinuous0WhenCSR0x0A.0=‘1’,thisfieldcontrolsthedividerusedtogeneratetheLVDSoutputclockfromtheMIPID-PHYChannelAHScontinuousclock.WhenCSR0x0A.0=‘0’,thisfieldmustbeprogrammedto00000.00000–LVDSclock=sourceclock(default)00001–Divideby200010–Divideby00011–Divideby•••10111–Divideby11000–Divideby11001through11111–WhenCSR0x0A.0=‘0’,thisfieldcontrolsthemultiplierusedtogeneratetheLVDSoutputclockfromtheinputREFCLK.WhenCSR0x0A.0=‘1’,thisfieldmustbeprogrammedto00.00–LVDSclock=sourceclock(default)01–Multiplyby2–Multiplyby–MultiplybyPRODUCTTable4.CSRBitFieldDefinitions–ResetandClockRegistersPRODUCTACCESS0Whenthisbitisset,thePLLisenabledwiththesettingsprogrammedintoCSR0x0AandCSR0x0B.ThePLLshouldbedisabledbeforechanginganyofthesettingsinCSR0x0AandCSR0x0B.TheinputclocksourcemustbeactiveandstablebeforethePLLisenabled.–PLLdisabled–PLL0Table5.CSRBitFieldDefinitions–DSIACCESSThisfieldcontrolsthenumberoflanesthatareenabledforDSIChannelA.00–Fourlanesareenabled01–Threelanesare–Twolanesare–OnelaneisenabledNote:UnusedDSIinputpinsontheSN65DSI83shouldbeleft0–SinglebiterrorsaretoleratedforthestartoftransactionSoTleadersequence(default)–NoSoTbiterrorsare0ThisfieldcontrolstheequalizationfortheDSIChannelADataLanes00–Noequalization(default)01–1dB––2dBThisfieldcontrolstheequalizationfortheDSIChannelAClock00–Noequalization(default)01–1dB––2dBThisfieldspecifiestheDSIClockfrequencyrangein5MHzincrementsfortheDSIChannelAClock0x00through0x07–0x08–40≤frequency<45MHz0x09–45≤frequency<50•••0x63–495≤frequency<500MHz0x64–500MHz0x65through0xFF–0(1)RO=ReadOnly;RW=Read/Write;RW1C=Read/Write‘1’toClear;WO=WriteOnly(readsreturnundeterminedPRODUCTTable6.CSRBitFieldDefinitions–LVDSPRODUCTACCESS7–DEispositivepolaritydriven‘1’duringactivepixeltransmissiononLVDS–DEisnegativepolaritydriven‘