数字集成电路-电路、系统与设计(第二版)课后练习题 第五章

CHAPTER5THECMOSINVERTERQuantificationofintegrity,performance,andenergymetricsofaninverterOptimizationofaninverterdesign5.1ExercisesandDesignProblems5.2TheStaticCMOSInverter—AnIntuitivePerspective5.3EvaluatingtheRobustnessoftheCMOSInverter:TheStaticBehavior5.4PerformanceofCMOSInverter:TheDynamicBehaviorAnalysisPerspective5.5Power,Energy,andEnergy-DelaySPICE5.6Perspective:TechnologyScalinganditsImpactontheInverterMetrics180Section5.1ExercisesandDesignProblems1815.1ExercisesandDesignProblems1.a.DeterminethesizesoftheNMOSandPMOStransistors.b.PlottheVTC(usingHSPICEandderiveitsparameters(VOH,VOL,VM,VIH,andVIL.c.IstheVTCaffectedwhentheoutputofthegatesisconnectedtotheinputsof4similargates?.d.Resizetheinvertertoachieveaswitchingthresholdofapproximately0.75V.Donotlay-outthenewinverter,useHSPICEforyoursimulations.Howarethenoisemarginsaffectedbythismodification?2.Figure5.2showsapiecewiselinearapproximationfortheVTC.ThetransitionregionisapproximatedbyastraightlinewithaslopeequaltotheinvertergainatVM.TheintersectionofthislinewiththeVOHandtheVOLlinesdefinesVIHandVIL.a.ThenoisemarginsofaCMOSinverterarehighlydependentonthesizingratio,r=kp/kn,oftheNMOSandPMOStransistors.UseHSPICEwithVTn=|VTp|todeterminethevalueofrthatresultsinequalnoisemargins?Giveaqualitativeexplanation.c.DeriveexpressionsfortheinvertergainatVMforthecaseswhenthesizingratioisjustaboveandjustbelowthelimitsoftherangewherebothdevicesarevelocitysaturated.WhataretheoperatingregionsoftheNMOSandthePMOSforeachcase?Considertheeffectofchannel-lengthmodulationbyusingthefollowingexpressionforthesmall-signalresistanceinthesaturationregion:ro,sat=1/(λID.Figure5.1CMOSinverterlayout.InOutGNDVDD=2.5V.PolyMetal1NMOSPMOSPolyMetal12λ182THECMOSINVERTERChapter53.c.FindNMLandNMH,andplottheVTCusingHSPICE.d.Computetheaveragepowerdissipationfor:(iVin=0Vand(iiVin=2.5Ve.UseHSPICEtosketchtheVTCsforRL=37k,75k,and150konasinglegraph.f.CommentontherelationshipbetweenthecriticalVTCvoltages(i.e.,VOL,VOH,VIL,VIHandtheloadresistance,RL.g.Dohighorlowimpedanceloadsseemtoproducemoreidealinvertercharacteristics?4.b.Aretherisingandfallingdelaysequal?Whyorwhynot?c.Computethestaticanddynamicpowerdissipationassumingthegateisclockedasfastaspossible.5.ThenextfigureshowstwoimplementationsofMOSinverters.ThefirstinverterusesonlyNMOStransistors.VOHVOLinVoutFigure5.2AdifferentapproachtoderiveVILandVIH.VoutVinM1W/L=1.5/0.5+2.5VFigure5.3Resistive-loadinverterRL=75kΩSection5.1ExercisesandDesignProblems183a.CalculateVOH,VOL,VMforeachcase.b.UseHSPICEtoobtainthetwoVTCs.Youmustassumecertainvaluesforthesource/drainareasandperimeterssincethereisnolayout.ForourscalableCMOSprocess,λ=0.125μm,andthesource/drainextensionsare5λforthePMOS;fortheNMOSthesource/draincontactregionsare5λx5λ.c.FindVIH,VIL,NMLandNMHforeachinverterandcommentontheresults.Howcanyouincreasethenoisemarginsandreducetheundefinedregion?d.CommentonthedifferencesintheVTCs,robustnessandregenerationofeachinverter.6.ConsiderthefollowingNMOSinverter.AssumethatthebulkterminalsofallNMOSdeviceareconnectedtoGND.AssumethattheinputINhasa0Vto2.5Vswing.a.Setuptheequation(stocomputethevoltageonnodex.Assumeγ=0.5.b.WhatarethemodesofoperationofdeviceM2?Assumeγ=0.c.WhatisthevalueontheoutputnodeOUTforthecasewhenIN=0V?Assumeγ=0.d.Assumingγ=0,deriveanexpressionfortheswitchingthreshold(VMoftheinverter.RecallthattheswitchingthresholdisthepointwhereVIN=VOUT.AssumethatthedevicesizesforM1,M2andM3are(W/L1,(W/L2,and(W/L3respectively.Whatarethelimitsontheswitchingthreshold?Forthis,considertwocases:i(W/L1>>(W/L2VDD=2.5VVINVOUTVDD=2.5VVINVOUTM2M1M4M3W/L=0.375/0.25W/L=0.75/0.25W/L=0.375/0.25W/L=0.75/0.25Figure5.4InverterImplementationsVDD=2.5VOUTM1INM2M3VDD=2.5Vx184THECMOSINVERTERChapter5ii(W/L2>>(W/L17.a.DeviceM2hasitsgateterminalconnectedtoitssourceterminal.IfVIN=0V,whatistheoutputvoltage?Insteadystate,whatisthemodeofoperationofdeviceM2forthisinput?b.ComputetheoutputvoltageforVIN=2.5V.YoumayassumethatVOUTissmalltosimplifyyourcalculation.Insteadystate,whatisthemodeofoperationofdeviceM2forthisinput?c.AssumingPr(IN=0=0.3,whatisthestaticpowerdissipationofthiscircuit?8.a.DeterminethetpLHofthiscircuit,assuminganidealstepfrom0to2.5Vattheinputnode.b.AssumethataresistorRSof5kΩisusedtodischargethecapacitancetoground.Deter-minetpHL.c.Determinehowmuchenergyistakenfromthesupplyduringthechargingofthecapacitor.HowmuchofthisisdissipatedinM1.Howmuchisdissipatedinthepull-downresistanceduringdischarge?HowdoesthischangewhenRSisreducedto1kΩ.d.TheNMOStransistorisreplacedbyaPMOSdevice,sizedsothatkpisequaltotheknoftheoriginalNMOS.Willtheresultingstructurebefaster?Explainwhyorwhynot.9.ThecircuitinFigure5.7isknownasthesourcefollowerconfiguration.ItachievesaDClevelshiftbetweentheinputandtheoutput.ThevalueofthisshiftisdeterminedbythecurrentI0.Assumexd=0,γ=0.4,2|φf|=0.6V,VT0=0.43V,kn’=115μA/V2andλ=0.VDD=2.5VOUTM1(4μm/1μmINM2(2μm/1μm,VTn=-0.4VFigure5.5AdepletionloadNMOSinverterVDD=2.5VOutFigure5.6CircuitdiagramwithannotatedW/Lratios=5pFSection5.1ExercisesandDesignProblems185a.SupposewewantthenominallevelshiftbetweenViandVotobe0.6VinthecircuitinFigure5.7(a.Neglectingthebackgateeffect,calculatethewidthofM2toprovidethislevelshift(Hint:firstrelateVitoVointermsofIo.b.NowassumethatanidealcurrentsourcereplacesM2(Figure5.7(b.TheNMOStransis-torM1experiencesashiftinVTduetothebackgateeffect.FindVTasafunctionofVoforVorangingfrom0to2.5Vwith0.5Vintervals.PlotVTvs.Voc.PlotVovs.ViasVovariesfrom0to2.5Vwith0.5Vintervals.Plottwocurves:oneneglectingthebodyeffectandoneaccountingforit.Howdoesthebodyeffectinfluencetheoperationofthelevelconverter?Cjsw,andassumethatVSB=0Vforallproblemsexceptpart(e.Figure5.7NMOSsourcefollowerconfigurationVDD=2.5VViVoVDD=2.5VViVoVbias=(a(bIo1um/0.25umM1186THECMOSINVERTERChapter511.UsingHspiceanswerthefollowingquestions.a.SimulatethecircuitinProblem10andmeasuretPandtheaveragepowerforinputVin:pulse(0VDD5n0.1n0.1n9n20n,asVDDvariesfrom1V-2.5Vwitha0.25Vinterval.[tP=(tPHL+tPLH/2].Usingthisdata,plot‘tPvs.VDD’,and‘Powervs.VDD’.forthisproblem.b.ForVddequalto2.5Vdeterminethemaximumfan-outofidenticalinvertersthisgatecandrivebeforeitsdelaybecomeslargerthan2ns.c.Simulatethesamecircuitforasetof‘pulse’inputswithriseandfalltimesoftin_rise,fall=1ns,2ns,5ns,10ns,20ns.Foreachinput,measure(1theriseandfalltimestout_riseandVDD=2.5VVINVOUTCL=Cinv-gateL=LP=LN=0.25μmVSB-+(Wp/Wn=1.25/0.375Figure5.8CMOSinverterwithcapacitiveSection5.1ExercisesandDesignProblems18712.ConsiderthelowswingdriverofFigure5.9:a.Whatisthevoltageswingontheoutputnode(Vout?Assumeγ=0.b.Estimate(itheenergydrawnfromthesupplyand(iienergydissipatedfora0Vto2.5Vtransitionattheinput.Assumethattheriseandfalltimesattheinputare0.Repeattheanalysisfora2.5Vto0Vtransitionattheinput.anNWELLimplementation.AssumethattheinputsINandINhavea0Vto2.5VswingandthatVIN=0VwhenVIN=2.5Vandvice-versa.AlsoassumethatthereisnoskewbetweenINandIN(i.e.,theinverterdelaytoderiveINfromINiszero.a.WhatvoltageisthebulkterminalofM2connectedto?VinVoutVDD=2.5VWL3μm0.25μm=p2.5V0VCL=100fFWL1.5μm0.25μm=nFigure5.9LowSwingDriverVLOW=0.5VOutM1ININM225μm/0.25μm25μm/0.25μmCL=1pFFigure5.10LowSwingDriver188THECMOSINVERTERChapter5b.Whatisthevoltageswingontheoutputnodeastheinputsswingfrom0Vto2.5V.Showthelowvalueandthehighvalue.c.AssumethattheinputsINandINhavezeroriseandfalltimes.AssumeazeroskewbetweenINandIN.Determinethelowtohighpropagationdelayforchargingtheoutputnodemeasuredfromthethe50%pointoftheinputtothe50%pointoftheoutput.Assumethatthetotalloadcapacitanceis1pF,includingthetransistorparasitics.d.Assumethat,insteadofthe1pFload,thelowswingdriverdrivesanon-linearcapacitor,whosecapacitancevs.voltageisplottedbelow.Computetheenergydrawnfromthelowsupplyforcharginguptheloadcapacitor.Ignoretheparasiticcapacitanceofthedrivercir-cuititself.14.TheinverterbelowoperateswithVDD=0.4Vandiscomposedof|Vt|=0.5Vdevices.ThedeviceshaveidenticalI0andn.a.Calculatetheswitchingthreshold(VMofthisinverter.b.CalculateVILandVIHoftheinverter.15.Sizingachainofinverters.a.Inordertodrivealargecapacitance(CL=20pFfromaminimumsizegate(withinputcapacitanceCi=10fF,youdecidetointroduceatwo-stagedbufferasshowninFigureVDD=0.4VVINVOUTFigure5.11InverterinWeakInversionRegimeSection5.1ExercisesandDesignProblems189thattheinputcapacitanceofagateisproportionaltoitssize.Determinethesizingofthetwoadditionalbufferstagesthatwillminimizethepropagationdelay.b.Ifyoucouldaddanynumberofstagestoachievetheminimumdelay,howmanystageswouldyouinsert?Whatisthepropagationdelayinthiscase?c.Describetheadvantagesanddisadvantagesofthemethodsshownin(aand(b.ibilitywithexistingsystemcomponents,youdecidetouseconstantvoltagescaling.a.Intraditionalconstantvoltagescaling,transistorwidthsscaleinverselywithS,W∝1/S.Toavoidthepowerincreasesassociatedwithconstantvoltagescaling,however,youdecidetochangethescalingfactorforW.Whatshouldthisnewscalingfactorbetomain-tainapproximatelyconstantpower.Assumelong-channeldevices(i.e.,neglectvelocitysaturation.b.Howdoesdelayscaleun