16位cpu设计课程设计

PAGEPAGE20目 录课程设计目的 3开发工具选择 3方案选择 3指令系统设计 4模型机框图设计 4指令流程图 5微指令格式（微程序控制器）设计 6微程序（微程序控制器）设计 7VHDL程序代码 9调试仿真 16课程设计回顾总结 18参考文献 18课程设计目的、计算机组成原理课程设计的主要任务是让学生通过动脑和动手解决计算机设计中的实在所设计的模型计算机上调试运行。、通过一台模型机的设计过程，明确计算机的控制原理与控制过程，巩固和灵活应用所事计算机研制与设计打下基础。开发工具选择使用QUARTUS5.0软件编写并调试VHDL程序，然后做功能仿真。方案选择16址方式：直接寻址、寄存器寻址、寄存器间接寻址和变址寻址。（控制存储器）中。微程序执行过程：如图1所示，为微程序控制基本框：从控存中逐条取出“取指令操作地址寄存器中。从控存中逐条的取出对应的微指令并执行。执行完一条机器指令对应的微程序后又回到取指微程序的入口地址，继续第步，以完成取下一条机器指令的公共操作。微命令序列……指令代码IR

微地址

译码器PSW

运行状态

形成电路 微命令字段微指令寄存器μIR

微地址字段PC 存器μAR

……控制存储器CM图1微程序控制基本框指令系统设计操作码目的操作数寻址方式 目的操作数源操作数寻址方式源操作数15 1211 109 65操作码目的操作数寻址方式 目的操作数源操作数寻址方式源操作数模拟机采用了定长的指令格式，每条指令字长为16位。采用的寻址方式为直接寻址0寄存器寻址0、寄存器间接寻址10）和变址寻址1，操作码类型及编码方式如下操作码staaddsuband1or1shl编码方式000000010010001101000101模型机框图设计IRMDRACCPCR0MCR1ALUMARD2所示，模型机采用单总线结构，主要包括运部件ALUPCACCIRIRMDRACCPCR0MCR1ALUMARD图2：模型机数据通路寄存器的位数：所有的寄存器都均为16位A通用寄存器R0，R1该模拟机有2个通用寄存器，用于提供操作数。B指令寄存器IR为了提高取指令的速度，将指令从内存中读出，经数据总线直接置入IR。C数据寄存器MDR、地址寄存器MAR地址寄存器MAR提供访问主存的地址；数据寄存器MDR，把从内存取出的数据暂存于MDR中，在用到该数据进行运算时，再从MDR中取出数据进行运算。D程序计数器PC用于存放下一条指令的内存地址。总线宽度：该模拟机只有一条总线，且总线宽度为16(3)ALU位数及运算功能ALU可以实现16位操作数的运算，即ALU的位数为16位。ALU运算功能为：可以实现简单的加0001ad、减0010su、逻辑与and、或010：or）操作。(4)微命令的设置（各标识的含义）经过认真分析各信息传送路径，对指令过程基本掌握，并为相应的微命令做了一下设置：171615141312111098765-0PC_busload_IRload_MARMDR_busload-MDRALU_ACCINC_PCAddr_busCSR_NWALU_addALU_sub下地址30292827262524232221201918微地址ACC_ACC_D_loadC_loadR1_loadR0_loadloadACCloadaddDaddCbus_Dbus_Cbus_R1bus_R0_PC_bus_ACC333231ALUALUALU_and_or_srl指令流程图指令的流程图如图3所示，共有6条指令，每条指令都要经过取指令、分析指令和执行指令3个步骤。在取指令阶段，8条指令是一样的，首先程序计数器PC的内容通过总线送入地址寄存器MAR，存储信息，PC+1传送给PC，把读出的内容传送给指令寄存器IR。再接下来的操作中，根据不同的指令，执行顺序也不同。PC→MARRi→CRi→MARRi→CRi→CPC+1→PCPC→MARM→MDR→CRj→MDRRj→DM→MDR→CPC+1→PCRj→DM→MDR→DCorD→RjC+Ri→MARM→MDR→DC－D→RjCandD→MDRM→MDR→CC→RjD+Rj→MARM→MDR→DMDR→MC+D→MDRMDR→M开始PC—>MAR开始PC—>MARM—>IR，PC+1—>PCstaaddsubandorshlA→MARM→MDR→CC左移一位→ACC结束微指令格式（微程序控制器）设计控制信号描控制信号描 述load_PCPCACC_busACC的内容驱动总线load_ACC ACCPC_busPC_bus用PC的内容驱动总线load_IRIRload_MAR MARMDR_bus MDR的内容驱动总线load_MDR 将总线上的数据装载至ALU_ACC 用ALU的结果装载ACCINC_PCPC+1并将结果存至PC中Addr_bus IR指令中的地址部分驱动总线CSMAR的内容设置存储器地址R_NWR_NWCSALU_addC ALUACCC的逻辑加操作ALU_addD ALUACCD的逻辑加操作ALU_add ALU中执行逻辑加操作ALU_subALU中执行减操作ALU_and ALU中执行与操作ALU_orALU中执行与操作ALU_shlALU中执行左移操作R0_busR0的内容驱动总线load_R0R0R1_busR1的内容驱动总线load_R1R1C_busC的内容驱动总线load_CCD_busD的内容驱动总线load_DD表1微指令格式微程序（微程序控制器）设计根据微处理器的数据通路和指令系统，可得出微程序的流程图如图4所示。微程序的编码采用直接编码方法，每一个控制信号对应一位，共有28个控制信号，根据微指令格式把相关的控制信号整合到一起进行编码。PC_busload_MAR 0INC_PCCS 1R_NWMDR_bus 2load_IRop 3staPC_bus48 load_MARINC_PCCSR_NWMDR_busload_Cload_MDRload_ACCR1_busALU_ACCACC_busload_MAR

add49R1_busload_MDRload_CPC_busload_MARINC_PCCSR_NWMDR_busload_Dload_MDRload_ACCR0_busALU_ACC

22CS21ACC_bus

sub50R0_busload_MARCSR_NWCSR_NW30load_C37load_CR1_busR1_busMDR_bus31load_MAR38load_MARload_C32CS39load_DR1_busR_NWload_MDR40ALU_ACC33MDR_busALU_orload_Dload_D41ACC_busALU_ACC34ALU_ACCload_MDRALU_subALU_and42load_R12425262728ACC_busload_MDR

and51R0_busload_MDR35ACC_busload_MDR

orR0_busload_MDR

shladdr_busload_MARCSR_NWMDR_busload_ACCALU_ACCALU_shlACC_busload_MDRload_R19 CSR_NWMDR_bus

16ALU_addC17ACC_busload_MAR

load_MDR20ALU_ACC

29load_R0 36CS10 load_Cload_R0

CSR_NW

MDR_busload_D根据图4微程序流程图的下地图44条微指令，该模拟机微程序的编码如下0=>00000000000000001010001000000000011=>00000000000000000000000011000000102=>00000000000000000101000000000000113=>00000000000000000000000000001111114=>00000000000000000000000011000001015=>00000000100000000001000000000001106=>00000000010000010000100000000001117=>00001000000000000000010000000010008=>00000000000000100010000000000010019=>000000000000000000000000110000101010=>000000001000100000010000000000000011=>000000001000000000000000000000110012=>000000000000000010100010000000110113=>000000000000000000000000110000111014=>000000100000000000010000000000111115=>000000000001000100001000000001000016=>000100000000000000000100000001000117=>000000000000001000100000000001001018=>000000000000000000000000110001001119=>000000100000000000010000000001010020=>000000000000000000000100001001010121=>000000000000001000001000000001011022=>000000000000000000000000100000000023=>000000000000000000000000110001100024=>000000001000000000010000000001100125=>000000000100000000001000000001101026=>000000100000000000000000000001101127=>000000000000000000000100000101110028=>000000000000001000001000000001110129=>000000000010000000000000000000000030=>000000001000000000000000000001111131=>000000000100000000100000000010000032=>000000000000000000000000110010000133=>000001000000000000010000000010001034=>100000000000000000000100000010001135=>000000000000001000001000000010010036=>000000000000000000000000100000000037=>000000001000000000000000000010011038=>000000000100000000001000000010011139=>000000100000000000000000000010100040=>010000000000000000000100000010100141=>000000000000001000001000000010101042=>000000000010000000000000000000000043=>000000000000000000000000110010110044=>000000001000000000010000000010110145=>001000000000000000000100000010111046=>000000000000001000000000010010111147=>000000000000100000000000000000000048=>000000000000000010100010000000010049=>000000000100000000001000000000101150=>000000000001000000100000000001011151=>000000000001000000001000000001111052=>000000000001000000001000000010010153=>0000000000000000001000010000101011VHDL程序代码--头文件LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;PACKAGEcpu_defsISTYPE opcodeIS(sta,add,sub,and1,or1,shl,jmp, TYPE regcodeIS(r0,r1);TYPE xzhcodeIS(zh,j,jj,bi);CONSTANTword_w:CONSTANTop_w:NATURAL:=4;CONSTANTreg_w::=4;CONSTANTxzh_w:NATURAL:=2;CONSTANTrfillop:STD_LOGIC_VECTOR(op_w-1downto0):=(others=>'0');CONSTANTrfillreg:STD_LOGIC_VECTOR(reg_w-1downto0):=(others=>'0');CONSTANTrfillxzh:STD_LOGIC_VECTOR(xzh_w-1downto0):=(others=>'0');--FUNCTIOnslv2op(slv:INSTD_LOGIC_VECTOR)RETURNFUNCTIONop2slv(op:inopcode)RETURNSTD_LOGIC_VECTOR;FUNCTIONregslv(reg:inregcode)RETURNSTD_LOGIC_VECTOR;FUNCTIONxzhslv(xzh:inxzhcode)RETURNSTD_LOGIC_VECTOR;ENDPACKAGEcpu_defs;PACKAGEBODYcpu_defsISTYPE optableISARRAY(opcode)OFSTD_LOGIC_VECTOR(op_w-1DOWNTO0);TYPE regtableISARRAY(regcode)OFSTD_LOGIC_VECTOR(reg_w-1DOWNTO0);TYPE xzhtableISARRAY(xzhcode)OFSTD_LOGIC_VECTOR(xzh_w-1DOWNTOCONSTANTtrans_tableop:optable:=("0000","0001","0010","0011","0100","0101","0110","0111");CONSTANTtrans_tabler:regtable:=("0000","0001");CONSTANTtrans_tablex:xzhtable:=("00","01","10","11");FUNCTIONop2slv(op:INopcode)RETURNSTD_LOGIC_VECTORISBEGINRETURNtrans_tableop(op);ENDFUNCTIONop2slv;FUNCTIONregslv(reg:inregcode)RETURNSTD_LOGIC_VECTORISBEGINRETURNtrans_tabler(reg);ENDFUNCTIONregslv;FUNCTIONxzhslv(xzh:inxzhcode)RETURNSTD_LOGIC_VECTORISBEGINRETURNtrans_tablex(xzh);ENDFUNCTIONxzhslv;ENDPACKAGEBODYcpu_defs;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL,IEEE.NUMERIC_STD.ALL;USEWORK.CPU_DEFS.ALL;ENTITYCPUISPORT(clock :IN STD_LOGIC;reset :IN STD_LOGIC;mode :IN STD_LOGIC_VECTOR(3DOWNTO0);mem_addr :IN UNSIGNED(word_w-op_w-1DOWNTO0);output :OUT STD_LOGIC_VECTOR(word_w-1DOWNTOdata_r_out:OUTSTD_LOGIC_VECTOR(33DOWNTO0);op_out :OUT STD_LOGIC_VECTOR(op_w-1DOWNTOadd_r_out :OUT UNSIGNED(5DOWNTO0));ENDENTITY;ARCHITECTURErtlOFCPUISTYPEmem_arrayISARRAY(0TO2**5)OFSTD_LOGIC_VECTOR(word_w-1DOWNTO0);SIGNAL mem :mem_array;CONSTANTprog :0=>op2slv(sta)&xzhslv(j)®slv(r0)&xzhslv(bi)®slv(r1)1=>STD_LOGIC_VECTOR(TO_UNSIGNED(3,word_w)),2=>op2slv(add)&xzhslv(bi)®slv(r0)&xzhslv(j)®slv(r1),3=>STD_LOGIC_VECTOR(TO_UNSIGNED(0,word_w)),4=>op2slv(sub)&xzhslv(j)®slv(r1)&xzhslv(jj)®slv(r0),5=>op2slv(and1)&xzhslv(jj)®slv(r1)&xzhslv(j)®slv(r0),6=>op2slv(or1)&xzhslv(j)®slv(r1)&xzhslv(j)®slv(r0),7=>op2slv(shl)&xzhslv(j)®slv(r0)&xzhslv(zh)&STD_LOGIC_VECTOR(TO_UNSIGNED(10,reg_w)),8=>STD_LOGIC_VECTOR(TO_UNSIGNED(9,word_w)),9=>STD_LOGIC_VECTOR(TO_UNSIGNED(8,word_w)),10=>STD_LOGIC_VECTOR(TO_UNSIGNED(15,word_w)),OTHERS=>(OTHERS=>'0'));TYPEmicrocode_arrayISARRAY(0TO53)OFSTD_LOGIC_VECTOR(33DOWNTO0);CONSTANTcode :microcode_array:=(0=>"0000000000000000101000100000000001",1=>"0000000000000000000000001100000010",2=>"0000000000000000010100000000000011",3=>"0000000000000000000000000000111111",4=>"0000000000000000000000001100000101",5=>"0000000010000000000100000000000110",6=>"0000000001000001000010000000000111",7=>"0000100000000000000001000000001000",8=>"0000000000000010001000000000001001",9=>"0000000000000000000000001100001010",10=>"0000000010001000000100000000000000",11=>"0000000010000000000000000000001100",12=>"0000000000000000101000100000001101",13=>"0000000000000000000000001100001110",14=>"0000001000000000000100000000001111",15=>"0000000000010001000010000000010000",16=>"0001000000000000000001000000010001",17=>"0000000000000010001000000000010010",18=>"0000000000000000000000001100010011",19=>"0000001000000000000100000000010100",20=>"0000000000000000000001000010010101",21=>"0000000000000010000010000000010110",22=>"0000000000000000000000001000000000",23=>"0000000000000000000000001100011000",24=>"0000000010000000000100000000011001",25=>"0000000001000000000010000000011010",26=>"0000001000000000000000000000011011",27=>"0000000000000000000001000001011100",28=>"0000000000000010000010000000011101",29=>"0000000000100000000000000000000000",30=>"0000000010000000000000000000011111",31=>"0000000001000000001000000000100000",32=>"0000000000000000000000001100100001",33=>"0000010000000000000100000000100010",34=>"1000000000000000000001000000100011",35=>"0000000000000010000010000000100100",36=>"0000000000000000000000001000000000",37=>"0000000010000000000000000000100110",38=>"0000000001000000000010000000100111",39=>"0000001000000000000000000000101000",40=>"0100000000000000000001000000101001",41=>"0000000000000010000010000000101010",42=>"0000000000100000000000000000000000",43=>"0000000000000000000000001100101100",44=>"0000000010000000000100000000101101",45=>"0010000000000000000001000000101110",46=>"0000000000000010000000000100101111",47=>"0000000000001000000000000000000000",48=>"0000000000000000101000100000000100",49=>"0000000001000000000010000000001011",50=>"0000000000010000001000000000010111",51=>"0000000000010000000010000000011110",52=>"0000000000010000000010000000100101",53=>"0000000000000000001000010000101011");SIGNALcount :UNSIGNED(word_w-op_w-1DOWNTO0);SIGNALop :STD_LOGIC_VECTOR(op_w-1DOWNTOSIGNALz_flag :STD_LOGIC;SIGNALmdr_out :STD_LOGIC_VECTOR(word_w-1DOWNTOSIGNALmar_out :UNSIGNED(reg_w-1DOWNTO0);SIGNALIR_out :STD_LOGIC_VECTOR(word_w-1DOWNTO0);SIGNALacc_out :UNSIGNED(word_w-1DOWNTO0);SIGNALsysbus_out:STD_LOGIC_VECTOR(word_w-1DOWNTOSIGNALcc:STD_LOGIC_VECTOR(word_w-1DOWNTO0);SIGNALrr1:STD_LOGIC_VECTOR(word_w-1DOWNTOBEGINPROCESS(reset,clock)VARIABLEinstr_reg:STD_LOGIC_VECTOR(word_w-1DOWNTO0); VARIABLEacc :UNSIGNED(word_w-1DOWNTO0);CONSTANTzero :UNSIGNED(word_w-1DOWNTO0):=(OTHERS=>'0');VARIABLEmdr :STD_LOGIC_VECTOR(word_w-1DOWNTO0);VARIABLEr0 :STD_LOGIC_VECTOR(word_w-1DOWNTO0);VARIABLEr1 :STD_LOGIC_VECTOR(word_w-1DOWNTO0);VARIABLEc :STD_LOGIC_VECTOR(word_w-1DOWNTO0);VARIABLEd :UNSIGNED(word_w-1DOWNTO0);VARIABLEmar :UNSIGNED(reg_w-1DOWNTO0);sysbus :STD_LOGIC_VECTOR(word_w-1DOWNTO0);VARIABLEmicrocode:microcode_array;add_r :UNSIGNED(5DOWNTO0);data_r :STD_LOGIC_VECTOR(33DOWNTOtemp :STD_LOGIC_VECTOR(5DOWNTOBEGINIFreset='0'THENadd_r:=(OTHERS=>'0');count<=(OTHERS=>'0');instr_reg:=(OTHERS=>'0');acc:=(OTHERS=>'0');mdr:=(OTHERS=>'0');mar:=(OTHERS=>'0');z_flag<='0';mem<=sysbus:=(OTHERSr0:=x"0005";r1:=x"0006";c:=(OTHERS=>'0');d:=(OTHERS=>'0');ELSIFRISING_EDGE(clock)THEN--microprogramcontrollerdata_r :=code(TO_INTEGER(add_r));IFdata_r(5DOWNTO0)="111111"THENtemp:="11"&op(3DOWNTO0);add_r:=UNSIGNED(temp);ELSEadd_r:=UNSIGNED(data_r(5DOWNTO0));ENDIF;data_r_out<=data_r;add_r_out<=add_r;--PCIFdata_r(17)='1'THEN --PC_bus='1'sysbus:=rfillop&STD_LOGIC_VECTOR(count);ENDIF;IFdata_r(20)='1'THEN --load_PC='1'count<=UNSIGNED(mdr(word_w-op_w-1DOWNTO0));ELSIFdata_r(11)='1'THEN--INC_PC='1'count<=count+1;ELSEcount<=count;ENDIF;DOWNTO

--IRIFdata_r(16)='1'THEN instr_reg:=mdr;ENDIF;IFdata_r(10)='1'THEN --Addr_bus='1'sysbus:=rfillop&rfillxzh&rfillreg&rfillxzh&instr_reg(reg_w-1ENDIF;op <=instr_reg(word_w-1DOWNTOIR_out<=instr_reg;op_out<=op;--ALUIFdata_r(22)='1'THEN--R0_bus='1'sysbus:=STD_LOGIC_VECTOR(r0);ENDIF;IFdata_r(21)='1'THEN--load_R0='1'r0:=mdr;ENDIF;IFdata_r(24)='1'THEN--R1_bus='1'sysbus:=STD_LOGIC_VECTOR(r1);ENDIF;IFdata_r(23)='1'THEN--load_R1='1'r1:=mdr;ENDIF;IFdata_r(26)='1'THEN--c_bus='1'sysbus:=STD_LOGIC_VECTOR(c);ENDIF;IFdata_r(25)='1'THEN--load_c='1'c:=mdr;ENDIF;IFdata_r(28)='1'THEN--d_bus='1'sysbus:=STD_LOGIC_VECTOR(d);ENDIF;IFdata_r(27)='1'THEN--load_d='1'd:=UNSIGNED(mdr);ENDIF;IFdata_r(19)='1'THEN--ACC_bus='1'sysbus:=STD_LOGIC_VECTOR(acc);ENDIF;IFdata_r(18)='1'THEN acc:=UNSIGNED(sysbus);ENDIF;IFdata_r(14)='1'THEN sysbus:=mdr;ENDIF;IFdata_r(12)='1'THEN--ALU_ACC='1'IFdata_r(6)='1'THEN acc:=UNSIGNED(c)-d;ELSIFdata_r(7)='1'THEN acc:=UNSIGNED(c)+d;ELSIFdata_r(29)='1'THEN acc:=UNSIGNED(c)+acc;ELSIFdata_r(30)='1'THEN acc:=UNSIGNED(d)+acc;ELSIFdata_r(33)='1'THEN --ALU_and='1'acc:=UNSIGNED(c)andd;ELSIFdata_r(32)='1'THEN --ALU_or='1'acc:=UNSIGNED(c)ord;ELSIFdata_r(31)='1'THEN --ALU_srl='1'acc:=UNSIGNED(c(word_w-1-1DOWNTO0))&'0';ENDIF;ENDIF;--IFacc=zeroTHEN--z_flag<='1';--ELSE--z_flag<='0';--ENDIF;acc_out<=acc;cc<=c;rr1<=r1;--RAMIFdata_r(15)='1'THEN--load_MAR='1'mar:=UNSIGNED(sysbus(reg_w-1DOWNTOELSIFdata_r(13)='1'THEN --load_MDR='1'mdr:=sysbus;ELSIFdata_r(9)='1'THEN --CS='1'IFdata_r(8)='1'THEN --R_NW='1'mdr:=mem(TO_INTEGER(mar));ELSEmem(TO_INTEGER(mar))<=mdr;ENDIF;ENDIF;mdr_out<=mdr;mar_out<=mar;ENDIF;sysbus_out<=sysbus;ENDPROCESS;PROCESS(mode,mem_addr)BEGINoutput<=(OTHERS=>'0');CASEmodeisWHEN"0000"output<=sysbus_out;WHEN"0001"=>output(word_w-op_w-1DOWNTO0)<=STD_LOGIC_VECTOR(count);WHEN"0010"=>output<=STD_LOGIC_VECTOR(acc_out);WHEN"0011"=>output<=WHEN"0100"=>output(reg_w-1DOWNTO0)<=STD_LOGIC_VECTOR(mar_out);WHEN"0101"=>output<=mdr_out;WHEN"0110"=>output<=mem(TO_INTEGER(mem_addr));WHEN"0111"=>output<=STD_LOGIC_VECTOR(cc);WHEN"1000"=>output<=STD_LOGIC_VECTOR(rr1);WHENothers=>output<=(OTHERS=>'Z');ENDCASE;ENDPROCESS;ENDARCHITECTURE;＇．．5飞SiE­,＇．．5飞SiE­,-,d拉吐－u1 5-cnnad

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