电子设计自动化基础-7综合基础知识课件

综合基本知识李晓明综合基本知识李晓明1内容模块综合过程关键约束介绍约束文件实例DC图形界面内容模块综合过程2综合的过程Synthesis=residue=16’h0000;if(high_bits==2’b10)residue=state_table[index];elsestate_table[index]=16’h0000;HDLSourceGenericBoolean(GTECH)TranslateTargetTechnologyOptimize+MapTranslation+Optimization+Mapping综合的过程Synthesis=residue=16’3SynthesisIsConstraint-DrivenDesignCompiler对设计进行优化，以达到你的设计目标LargeAreaSmallShort

Delay

High••••••设计者设定目标(throughconstraints)SynthesisIsConstraint-Driven4电子设计自动化基础-7综合基础知识课件5write模块综合过程gtech.dbGTECH

my_chip.v(hd)writeOPTIMIZATION+MAPPINGsourceDC_MEMORYTRANSLATIONscriptsconstraints.tclmappedmy_chip.dbmy_chip.edifcompileDC_MEMORYMY_CHIPcore_slow.dbtarget_libraryHDLsourceunmappedmy_chip.dbread_dbanalyze/elaborateY=A+BMY_CHIPread_vhdlread_verilogwrite模块综合过程gtech.dbGTECHmy_ch6工艺库cell(OR2_3){area:8.000;pin(Y){direction:output;timing(){related_pin:"A";timing_sense:positive_unate;rise_propagation(drive_3_table_1){values("0.2616,0.2608,0.2831,..)}rise_transition(drive_3_table_2){values("0.0223,0.0254,...) ....function:"(A|B)";max_capacitance:1.14810;min_capacitance:0.00220;}pin(A){direction:input;capacitance:0.012000; ....CellnameCellAreaPinA->PinYnominaldelays(look-uptable)DesignRulesforOutputPinElectricalCharacteristicsofInputPinsPinYfunctionalityY=A|BtABYExampleofacelldescriptionin.libFormat工艺库cell(OR2_3){CellnameCe7moduleTOP(A,B,C,D,CLK,OUT1);inputA,B,C,D,CLK;output[1:0]OUT1;wireINV1,INV0,bus1,bus0;

ENCODERU1(.AIN(A),....Q1(bus1));

INV U2(.A(BUS0),.Z(INV0)),

U3(.A(BUS1),.Z(INV1));

REGFILEU4(.D0(INV0),.D1(INV1),.CLK(CLK));

endmodule设计目标PinCellReferencePortDesignClockNetmoduleTOP(A,B,C,D,CLK,OUT1);8D0Q[1:0]D1REGFILEU4OUT[1:0]INV0INV1AINBINCINDINQ0Q1ENCODERINVINVU1U2ABCDCLKBUS0BUS1ABCDCLKU3TOPPinCLK设计目标ClockReferenceandDesignDesignCellNetPortDesigns:

{TOP,ENCODER,REGFILE}References:{ENCODER,REGFILE,INV}Cells:{U1,U2,U3,U4}D0Q[1:0]REGFILEU4OUT[1:0]INV9SettingDesignRuleConstraintsthemostcommonlyspecifieddesignruleconstraints:TransitiontimeFanoutloadCapacitanceSettingDesignRuleConstraint10SettingTransitionTimeConstraintsThetransitiontimeofanetisthetimerequiredforitsdrivingpintochangelogicvalues.DesignCompilercalculatesthetransitiontimeforeachnetbymultiplyingthedriveresistanceofthedrivingpinbythesumofthecapacitiveloadsconnectedtothedrivingpin.SettingTransitionTimeConstr11SettingFanoutLoadConstraintsThemaximumfanoutloadforanetisthemaximumnumberofloadsthenetcandrive.Thefanoutloadvaluedoesnotrepresentcapacitance;itrepresentstheweightednumericalcontributiontothetotalfanoutload.SettingFanoutLoadConstraint12SettingCapacitanceConstraintsThetransitiontimeconstraintsdonotprovideadirectwaytocontroltheactualcapacitanceofnets.Theset_max_capacitancecommandsetsamaximumcapacitanceforthenetsattachedtothenamedportsortoallthenetsinadesignbysettingthemax_capacitanceattributeonthespecifiedobjects.SettingCapacitanceConstraint13同步设计（SynchronousDesign）D

Q

QBD

Q

QBD

Q

QBD

Q

QBClk

TO_BE_SYNTHESIZEDFF1FF2FF3FF4MNXSTWhatinformationmustyouprovidetoconstrainalltheregister-to-registerpathsinyourdesign?同步设计（SynchronousDesign）DQ14定义时钟UserMUSTDefine:ClockSource(portorpin)ClockPeriodPeriodClkNX

S

DQDQ

TO_BE_SYNTHESIZEDFF2FF3Usermayalsodefine:DutyCycleOffset/SkewClockNameClk1ClockCycle定义时钟UserMUSTDefine:PeriodClk15CommandstoSetTimingConstraintsCommandstoSetTimingConstra16SetTimingConstraintsMultipleclocks:

paycloseattentiontothecommonbaseperiodoftheclocks.Thecommonbaseperiodistheleastcommonmultipleofalltheclockperiods.

Forexample,ifyouhaveclockperiodsof10,15,and20,thecommonbaseperiodis60.VirtualClock:

Insomecases,asystemclockmightnotexistinablock.Youcanusethecreate_clock-namecommandtocreateavirtualclockformodelingclocksignalspresentinthesystembutnotintheblock.Bycreatingavirtualclock,youcanrepresentdelaysthatarerelativetoclocksoutsidetheblock.SetTimingConstraintsMultiple17ClockNetworkDelayClockNetworkDelayBydefault,DesignCompilerassumesthatclocknetworkshavenodelay(idealclocks).Usetheset_clock_skewcommandtospecifytiminginformationabouttheclocknetworkdelay(eitherestimatedoractualdelay)Usethe-propagatedoption:specifythatyouwantDesignCompilertocalculateclocknetworkdelaybypropagatingtimesthroughtheclocknetwork.Usethe-plus_uncertainty(-minus_uncertainty)options:toaddsomemarginoferrorintothesystemtoaccountforvariancesintheclocknetworkresultingfromlayout.ClockNetworkDelayClockNetwo18set_input_delayTO_BE_SYNTHESIZEDAClk(50MHz)EXTERNALCIRCUITcreate_clock-period20[get_portsClk]set_dont_touch_network[get_clocksClk]set_input_delay-max7.4-clockClk[get_portsA]DQNClkCLK-OUTPUT7.4ns(worst)U1set_input_delayTO_BE_SYNTHESIZ19set_output_delaycreate_clock-period20[get_portsClk]set_dont_touch_network[get_clocksClk]set_output_delay-max7.0-clockClk[get_portsB]ClkSDQTO_BE_SYNTHESIZEDBEXTERNALCIRCUITSetupRequirement:7.0nsClock(50MHz)U3set_output_delaycreate_clock-20SpecifyingCombinationalPathDelayForpurelycombinationaldelaysthatarenotboundedbyaclockperiodusetheset_max_delayandset_min_delaycommandstodefinethemaximumandminimumdelaysforthespecifiedpaths.AcommonwaytoproducethistypeofasynchronouslogicinHDLcodeistouseasynchronoussetsorresetsonlatchesandflip-flops.Becausetheresetsignalcrossesseveralblocks,constrainthissignalatthetoplevel.SpecifyingCombinationalPath21SpecifyingTimingExceptionsUsetimingexceptionstoconstrainordisableasynchronouspathsorpathsthatdonotfollowthedefaultsingle-cyclebehavior.Beawarethatspecifyingnumeroustimingexceptionscanincreasethecompileruntime.Youcanspecifythefollowingconditionsbyusingtimingexceptioncommands:Falsepaths(set_false_path)Minimumdelayrequirements(set_min_delay)Maximumdelayrequirements(set_max_delay)Multicyclepaths(set_multicycle_path)SpecifyingTimingExceptionsUs22Thefifthpath(U1/GtoU1/D)isafunctionalfalsepathbecausenormaloperationneverrequiressimultaneouswritingandreadingoftheconfigurationregister.Thefifthpath(U1/GtoU1/D)23SettingAreaConstraintsDesignareaconsistsoftheareasofeachcomponentandnet.ThefollowingcomponentsareignoredwhenDesignCompilercalculatesdesignarea:UnknowncomponentsComponentswithunknownareasTechnology-independentgenericcellsSettingAreaConstraintsDesign24描述环境属性set_driving_cellset_loadset_operating_conditionsset_wire_load_model描述环境属性set_driving_cellset_load25

TO_BE_SYNTHESIZED估计电容负载为了精确计算输出电路的时序，DC需要知道输出元件驱动的总电容set_load

命令可定义端口外部电容负载:缺省情况下,DC假定端口外部电容负载为0set_load[expr[load_ofmy_lib/inv1a0/A]*3]OUT1AOUT1AAOUT1AN2Aset_load[load_ofmy_lib/and2a0/A][get_portsOUT1]BTO_BE_SYNTHESIZED估计电容负载为了精确计26估计输入端驱动强度为了精确计算输出电路的时序，DC需要知道信号到达输入端的转换时间set_driving_cell命令可定义驱动输入端的外部元件

:缺省值为0dc_shell-t>set_driving_cell-lib_celland2a0\ [get_portsIN1]ND2IN1

TO_BE_SYNTHESIZED估计输入端驱动强度为了精确计算输出电路的时序，DC需要知道信27OperatingConditions:NameLibraryProcessTempVolt----------------------------------------------------typ_25_1.80my_lib1.0025.001.80slow_125_1.62my_lib1.00125.001.62fast_0_1.98my_lib1.000.001.98设置工作环境缺省：对于一个设计，没有指定的工作环境（operatingconditions）使用

report_liblibname

查看vendor-supplied工作环境dc_shell-t>set_operating_conditions-max“slow_125_1.62”quotesareoptional设置工作环境，键入:OperatingConditions:设置工作环境缺省：28线负载模型（

WireLoadModel）线负载模型(WLM)是对连线的RC寄生参数的估计，基于连线的扇出（fanout）:模型由vendor提供vendor采用该工艺制造其他芯片时，得到统计值，由此得到线负载模型的估计值线负载模型（WireLoadModel）线负载模型(W29WireLoadModel:标准格式Name:160KGATESLocation:ssc_core_slowResistance:0.000271Capacitance:0.00017Area:0Slope:50.3104FanoutLength---------------------------------131.44281.753132.074182.385232.68

Example:StandardFormatRperunitlengthCperunitlengthExtrapolationslopeTimeUnit:1nsCapacitiveLoadUnit:1.000000pfPullingResistanceUnit:1kilo-ohmWireLoadModel:标准格式Name30OptimizingYourDesignResolvingMultipleInstances Ifyourdesignreferencesanydesignmorethanonce,youmustresolvethesemultipleinstancesbeforerunningthecompilecommand.Theuniquifymethod:Thismethodusestheuniquify

commandtocreateacopyofthedesignforeachinstance.Thecompile-once-don’t-touchmethod:Thismethodusestheset_dont_touch

commandtopreservethesubdesignduringoptimization.Theungroupmethod:Thismethodusestheungroup

commandtoremovethehierarchy.OptimizingYourDesignResolvin31uniquify

commandtocopyandrenamethedesignforeachinstance.ungrouphasthesameeffectastheuniquifymethod(makinguniquecopiesofthedesign)butalsoremoveslevelsofhierarchy.uniquifycommandtocopyandr32OptimizingRandomLogicIfthedefaultcompiledoesnotgivethedesiredresultforyourrandomlogicdesign,trythefollowingtechniques.Ifthefirsttechniquedoesnotgivethedesiredresults,usethesecondtechnique,andsoon,untilyouobtainthedesiredresults.Flattenthedesignbeforestructuring:

dc_shell>set_flattentrue dc_shell>set_structuretrue dc_shell>compile Increasetheflatteningeffort: dc_shell>set_flattentrue-effortmedium dc_shell>compileOptimizingRandomLogicIfthe33OptimizingStructuredLogicIfthedefaultcompiledoesnotgivethedesiredresultforyourstructuredlogicdesign,trythefollowingtechniques.Ifthefirsttechniquedoesnotgivethedesiredresults,trythesecondone.Mapthedesignwithnoflatteningorstructuring.Enter

dc_shell>set_structurefalse dc_shell>compileFlattenwithstructuring.Enter

dc_shell>set_flattentrue dc_shell>set_structuretrue dc_shell>compileOptimizingStructuredLogicIf34例：Adder16.v/*16-BitAdderModule*/moduleAdder16(ain,bin,cin,sout,cout,clk);output[15:0]sout;outputcout;input[15:0]ain,bin;inputcin,clk;wire[15:0]sout_tmp,ain,bin;wirecout_tmp;reg[15:0]sout,ain_tmp,bin_tmp;regcout,cin_tmp;always@(posedgeclk)begincout=cout_tmp;sout=sout_tmp;ain_tmp=ain;bin_tmp=bin;cin_tmp=cin;endassign{cout_tmp,sout_tmp}=ain_tmp+bin_tmp+cin_tmp;endmodule例：Adder16.v/*16-BitAdderM35约束文件实例（run.scr）

一个约束文件，采用自顶向下的编译策略，对Adder16.v进行优化/*specifythelibraries*/指定库target_library=my_lib.dbsymbol_library=my_lib.sdblink_library="*"+target_library/*readthedesign*/读入设计read-formatverilogAdder16.v/*definethedesignenvironment*/定义设计环境set_operating_conditionsWCCOMset_wire_load"10x10"set_load2.2soutset_load1.5coutset_driving_cell-cellFD1all_inputs()set_drive0clk约束文件实例（run.scr）

一个约束文件，采用自顶向下的36约束文件实例（Cont）/*settheoptimizationconstraints*/设置优化约束create_clockclk-period10set_input_delay-max1.35-clockclk{ain,bin}set_input_delay-max3.5-clockclkcinset_output_delay-max2.4-clockclkcoutset_max_area0/*mapandoptimizethedesign*/映射并优化设计Uniquify //为每个例化元件映射一个设计Compile //执行综合并优化/*analyzeanddebugthedesign*/分析并调试设计report_constraint-all_violatorsreport_area/*savethedesigndatabase*/保存设计数据write-formatdb-hierarchy-outputAdder16.db约束文件实例（Cont）/*settheoptimiz37约束的运行方式用户可以采用如下几种方法执行命令：a)

进入dc_shell，并逐个键入命令b)

进入dc_shell，并执行脚本文件，采用include命令（dcsh模式）或source命令（Tcl模式）。如假设上面的脚本文件称作run.scr，则在dcsh模式下运行dc_shell>

includerun.scrc)

在UNIX命令行模式下运行脚本，如%

dc_shell-frun.scr约束的运行方式用户可以采用如下几种方法执行命令：38DesignAnalyzer图形界面DesignAnalyzer图形界面39读入设计读入设计40时钟约束时钟约束41时钟约束时钟约束42优化优化43优化优化44输出报告输出报告45输出报告输出报告46Thankyou!电子设计自动化基础-7综合基础知识课件47综合基本知识李晓明综合基本知识李晓明48内容模块综合过程关键约束介绍约束文件实例DC图形界面内容模块综合过程49综合的过程Synthesis=residue=16’h0000;if(high_bits==2’b10)residue=state_table[index];elsestate_table[index]=16’h0000;HDLSourceGenericBoolean(GTECH)TranslateTargetTechnologyOptimize+MapTranslation+Optimization+Mapping综合的过程Synthesis=residue=16’50SynthesisIsConstraint-DrivenDesignCompiler对设计进行优化，以达到你的设计目标LargeAreaSmallShort

Delay

High••••••设计者设定目标(throughconstraints)SynthesisIsConstraint-Driven51电子设计自动化基础-7综合基础知识课件52write模块综合过程gtech.dbGTECH

my_chip.v(hd)writeOPTIMIZATION+MAPPINGsourceDC_MEMORYTRANSLATIONscriptsconstraints.tclmappedmy_chip.dbmy_chip.edifcompileDC_MEMORYMY_CHIPcore_slow.dbtarget_libraryHDLsourceunmappedmy_chip.dbread_dbanalyze/elaborateY=A+BMY_CHIPread_vhdlread_verilogwrite模块综合过程gtech.dbGTECHmy_ch53工艺库cell(OR2_3){area:8.000;pin(Y){direction:output;timing(){related_pin:"A";timing_sense:positive_unate;rise_propagation(drive_3_table_1){values("0.2616,0.2608,0.2831,..)}rise_transition(drive_3_table_2){values("0.0223,0.0254,...) ....function:"(A|B)";max_capacitance:1.14810;min_capacitance:0.00220;}pin(A){direction:input;capacitance:0.012000; ....CellnameCellAreaPinA->PinYnominaldelays(look-uptable)DesignRulesforOutputPinElectricalCharacteristicsofInputPinsPinYfunctionalityY=A|BtABYExampleofacelldescriptionin.libFormat工艺库cell(OR2_3){CellnameCe54moduleTOP(A,B,C,D,CLK,OUT1);inputA,B,C,D,CLK;output[1:0]OUT1;wireINV1,INV0,bus1,bus0;

ENCODERU1(.AIN(A),....Q1(bus1));

INV U2(.A(BUS0),.Z(INV0)),

U3(.A(BUS1),.Z(INV1));

REGFILEU4(.D0(INV0),.D1(INV1),.CLK(CLK));

endmodule设计目标PinCellReferencePortDesignClockNetmoduleTOP(A,B,C,D,CLK,OUT1);55D0Q[1:0]D1REGFILEU4OUT[1:0]INV0INV1AINBINCINDINQ0Q1ENCODERINVINVU1U2ABCDCLKBUS0BUS1ABCDCLKU3TOPPinCLK设计目标ClockReferenceandDesignDesignCellNetPortDesigns:

{TOP,ENCODER,REGFILE}References:{ENCODER,REGFILE,INV}Cells:{U1,U2,U3,U4}D0Q[1:0]REGFILEU4OUT[1:0]INV56SettingDesignRuleConstraintsthemostcommonlyspecifieddesignruleconstraints:TransitiontimeFanoutloadCapacitanceSettingDesignRuleConstraint57SettingTransitionTimeConstraintsThetransitiontimeofanetisthetimerequiredforitsdrivingpintochangelogicvalues.DesignCompilercalculatesthetransitiontimeforeachnetbymultiplyingthedriveresistanceofthedrivingpinbythesumofthecapacitiveloadsconnectedtothedrivingpin.SettingTransitionTimeConstr58SettingFanoutLoadConstraintsThemaximumfanoutloadforanetisthemaximumnumberofloadsthenetcandrive.Thefanoutloadvaluedoesnotrepresentcapacitance;itrepresentstheweightednumericalcontributiontothetotalfanoutload.SettingFanoutLoadConstraint59SettingCapacitanceConstraintsThetransitiontimeconstraintsdonotprovideadirectwaytocontroltheactualcapacitanceofnets.Theset_max_capacitancecommandsetsamaximumcapacitanceforthenetsattachedtothenamedportsortoallthenetsinadesignbysettingthemax_capacitanceattributeonthespecifiedobjects.SettingCapacitanceConstraint60同步设计（SynchronousDesign）D

Q

QBD

Q

QBD

Q

QBD

Q

QBClk

TO_BE_SYNTHESIZEDFF1FF2FF3FF4MNXSTWhatinformationmustyouprovidetoconstrainalltheregister-to-registerpathsinyourdesign?同步设计（SynchronousDesign）DQ61定义时钟UserMUSTDefine:ClockSource(portorpin)ClockPeriodPeriodClkNX

S

DQDQ

TO_BE_SYNTHESIZEDFF2FF3Usermayalsodefine:DutyCycleOffset/SkewClockNameClk1ClockCycle定义时钟UserMUSTDefine:PeriodClk62CommandstoSetTimingConstraintsCommandstoSetTimingConstra63SetTimingConstraintsMultipleclocks:

paycloseattentiontothecommonbaseperiodoftheclocks.Thecommonbaseperiodistheleastcommonmultipleofalltheclockperiods.

Forexample,ifyouhaveclockperiodsof10,15,and20,thecommonbaseperiodis60.VirtualClock:

Insomecases,asystemclockmightnotexistinablock.Youcanusethecreate_clock-namecommandtocreateavirtualclockformodelingclocksignalspresentinthesystembutnotintheblock.Bycreatingavirtualclock,youcanrepresentdelaysthatarerelativetoclocksoutsidetheblock.SetTimingConstraintsMultiple64ClockNetworkDelayClockNetworkDelayBydefault,DesignCompilerassumesthatclocknetworkshavenodelay(idealclocks).Usetheset_clock_skewcommandtospecifytiminginformationabouttheclocknetworkdelay(eitherestimatedoractualdelay)Usethe-propagatedoption:specifythatyouwantDesignCompilertocalculateclocknetworkdelaybypropagatingtimesthroughtheclocknetwork.Usethe-plus_uncertainty(-minus_uncertainty)options:toaddsomemarginoferrorintothesystemtoaccountforvariancesintheclocknetworkresultingfromlayout.ClockNetworkDelayClockNetwo65set_input_delayTO_BE_SYNTHESIZEDAClk(50MHz)EXTERNALCIRCUITcreate_clock-period20[get_portsClk]set_dont_touch_network[get_clocksClk]set_input_delay-max7.4-clockClk[get_portsA]DQNClkCLK-OUTPUT7.4ns(worst)U1set_input_delayTO_BE_SYNTHESIZ66set_output_delaycreate_clock-period20[get_portsClk]set_dont_touch_network[get_clocksClk]set_output_delay-max7.0-clockClk[get_portsB]ClkSDQTO_BE_SYNTHESIZEDBEXTERNALCIRCUITSetupRequirement:7.0nsClock(50MHz)U3set_output_delaycreate_clock-67SpecifyingCombinationalPathDelayForpurelycombinationaldelaysthatarenotboundedbyaclockperiodusetheset_max_delayandset_min_delaycommandstodefinethemaximumandminimumdelaysforthespecifiedpaths.AcommonwaytoproducethistypeofasynchronouslogicinHDLcodeistouseasynchronoussetsorresetsonlatchesandflip-flops.Becausetheresetsignalcrossesseveralblocks,constrainthissignalatthetoplevel.SpecifyingCombinationalPath68SpecifyingTimingExceptionsUsetimingexceptionstoconstrainordisableasynchronouspathsorpathsthatdonotfollowthedefaultsingle-cyclebehavior.Beawarethatspecifyingnumeroustimingexceptionscanincreasethecompileruntime.Youcanspecifythefollowingconditionsbyusingtimingexceptioncommands:Falsepaths(set_false_path)Minimumdelayrequirements(set_min_delay)Maximumdelayrequirements(set_max_delay)Multicyclepaths(set_multicycle_path)SpecifyingTimingExceptionsUs69Thefifthpath(U1/GtoU1/D)isafunctionalfalsepathbecausenormaloperationneverrequiressimultaneouswritingandreadingoftheconfigurationregister.Thefifthpath(U1/GtoU1/D)70SettingAreaConstraintsDesignareaconsistsoftheareasofeachcomponentandnet.ThefollowingcomponentsareignoredwhenDesignCompilercalculatesdesignarea:UnknowncomponentsComponentswithunknownareasTechnology-independentgenericcellsSettingAreaConstraintsDesign71描述环境属性set_driving_cellset_loadset_operating_conditionsset_wire_load_model描述环境属性set_driving_cellset_load72

TO_BE_SYNTHESIZED估计电容负载为了精确计算输出电路的时序，DC需要知道输出元件驱动的总电容set_load

命令可定义端口外部电容负载:缺省情况下,DC假定端口外部电容负载为0set_load[expr[load_ofmy_lib/inv1a0/A]*3]OUT1AOUT1AAOUT1AN2Aset_load[load_ofmy_lib/and2a0/A][get_portsOUT1]BTO_BE_SYNTHESIZED估计电容负载为了精确计73估计输入端驱动强度为了精确计算输出电路的时序，DC需要知道信号到达输入端的转换时间set_driving_cell命令可定义驱动输入端的外部元件

:缺省值为0dc_shell-t>set_driving_cell-lib_celland2a0\ [get_portsIN1]ND2IN1

TO_BE_SYNTHESIZED估计输入端驱动强度为了精确计算输出电路的时序，DC需要知道信74OperatingConditions:NameLibraryProcessTempVolt----------------------------------------------------typ_25_1.80my_lib1.0025.001.80slow_125_1.62my_lib1.00125.001.62fast_0_1.98my_lib1.000.001.98设置工作环境缺省：对于一个设计，没有指定的工作环境（operatingconditions）使用

report_liblibname

查看vendor-supplied工作环境dc_shell-t>set_operating_conditions-max“slow_125_1.62”quotesareoptional设置工作环境，键入:OperatingConditions:设置工作环境缺省：75线负载模型（

WireLoadModel）线负载模型(WLM)是对连线的RC寄生参数的估计，基于连线的扇出（fanout）:模型由vendor提供vendor采用该工艺制造其他芯片时，得到统计值，由此得到线负载模型的估计值线负载模型（WireLoadModel）线负载模型(W76WireLoadModel:标准格式Name:160KGATESLocation:ssc_core_slowResistance:0.000271Capacitance:0.00017Area:0Slope:50.3104FanoutLength---------------------------------131.44281.753132.074182.385232.68

Example:StandardFormatRperunitlengthCperunitlengthExtrapolationslopeTimeUnit:1nsCapacitiveLoadUnit:1.000000pfPullingResistanceUnit:1kilo-ohmWireLoadModel:标准格式Name77OptimizingYourDesignResolvingMultipleInstances Ifyourdesignreferencesanydesignmorethanonce,youmustresolvethesemultipleinstancesbeforerunningthecompilecommand.Theuniquifymethod:Thismethodusestheuniquify

commandtocreateacopyofthedesignforeachinstance.Thecompile-once-don’t-touchmethod:Thismethodusestheset_dont_touch

commandtopreservethesubdesignduringoptimization.Theungroupmethod:Thismethodusestheungroup

commandtoremovethehierarchy.OptimizingYourDesignResolvin78uniquify

commandtocopyandrenamethedesignforeachinstance.ungrouphasthesameeffectastheuniquifymethod(makinguniquecopiesofthedesign)butalsoremoveslevelsofhierarchy.uniquifycommandtocopyandr79OptimizingRandomLogicIfthedefaultcompiledoesnotgivethedesiredresultforyourrandomlogicdesign,trythefollowingtechniques.Ifthefirsttechniquedoesnotgivethedesiredresults,usethesecondtechnique,andsoon,untilyouobtainthedesiredresults.Flattenthed