基于FPGA的数字滤波器

学士学位论文论文题目: 基于FPGA的数字滤波器设计院(部)名称:电气信息工程学院学生姓名:专业:测控技术与仪器学号:指导教师姓名:68参考文献[1]田耘,徐文波，张延伟等编著.无线通信FPGA设计[M].电子工业出版社.2007.[2]李健.基于FPGA的高速FIR数字滤波器设计[D].西安理工大学,2008[3]柳秀山,韩克.Proteus在电子实践教学课程中应用的研究[J].中国校外教育(理论),2008.[4]何红军.Proteus在电子技术课程实践中的应用[J].华章,2011.[5]高工,许刚.精密基准电压源的设计思路与应用考虑(上)[J].电子产品世界,1999.[6]杨全科主编.模拟电子技术基础[M].高等教育出版社.2003.[7]焦素敏主编.数字电子技术基础(第2版)[M].人民邮电出版社.2012.8[8]高西全,丁玉美编著.数字信号处理第二版[M].西安电子科技大学出版社.2002.[9]张德丰编著.matlab数字信号处理与应用[M].清华大学出版社.2010[10]中国电子资源网http://w/r/[11]电子开发论坛[12]MEYER-BAESEU．数字信号处理的FPGA实现[M]．刘凌.译．清华大学出版社.2003．[13]徐志军,徐光辉．CPLD/FPGA的开发与应用[M].电子工业出版社.2002．[14]简弘伦．精通VerilogHDL：Ic设计核心技术实例详解[M]．电子工业出版社.2005．[15]潘松,黄继业．EDA实用教程[M].科学出版社.2002．附录1：QuartusII综合的功能结构图附录2：源程序顶层模块module fir_top( input i_50m_clk,//系统时钟50M input i_rst_n,//系统复位信号 input [7:0]i_adc_data,//ADC9280数据输入 output wire o_adc_clk,//ADC9280时钟控制信号 output wire [7:0]o_dac_data,//DAC9708数据输出 output wire o_dac_clk //DAC9708时钟控制信号 );wirelocked;//时钟稳定信号wirec0;//AD与DA时钟assigno_adc_clk =locked?c0:1'b0;//ADC采样时钟信号10Massigno_dac_clk =locked?c0:1'b0;//DAC时钟信号10M//对系统输入时钟进行处理pll u_0( .areset (!i_rst_n ),//复位信号 .inclk0 (i_50m_clk),//输入时钟 .c0 (c0 ),//AD与DA时钟 .locked(locked )//时钟稳定信号 );//FIR滤波模块例化wiresigned[7:0]i_adc_data_r;assigni_adc_data_r=i_adc_data-8'd128;//ad9208输入8’d0波谷，8‘d255波峰wire[7:0]o_dac_data_r;assigno_dac_data=o_dac_data_r+8'd128;//ad9708输出8'd128~0v，8’d0~-1v，8‘d255~1vfir u_1( .i_50m_clk (i_50m_clk ), //FIR时钟信号50M .i_rst_n (i_rst_n ), //复位信号 .i_dat (i_adc_data_r),//输入数据 .o_dat (o_dac_data_r ) //输出数据 ); endmoduleFIR功能模块modulefir( inputi_50m_clk ,//FIR工作时钟 inputi_rst_n ,//复位信号 input [7:0]i_dat ,//输入信号 outputwire[7:0]o_dat//输出信号 );//查表位寄存器reg[3:0]dat_wei;//查表位控制always@(posedgei_50m_clkornegedgei_rst_n)if(!i_rst_n) dat_wei<=0;elseif(dat_wei==4'd9) dat_wei<=0;else dat_wei<=dat_wei+1'b1;//信号采样延迟寄存器regsigned[7:0]dat_1 ;regsigned[7:0]dat_2 ;regsigned[7:0]dat_3 ;regsigned[7:0]dat_4 ;regsigned[7:0]dat_5 ;regsigned[7:0]dat_6 ;regsigned[7:0]dat_7 ;regsigned[7:0]dat_8 ;regsigned[7:0]dat_9 ;regsigned[7:0]dat_10;regsigned[7:0]dat_11;regsigned[7:0]dat_12;regsigned[7:0]dat_13;regsigned[7:0]dat_14;regsigned[7:0]dat_15;regsigned[7:0]dat_16;regsigned[7:0]dat_17;regsigned[7:0]dat_18;regsigned[7:0]dat_19;regsigned[7:0]dat_20;regsigned[7:0]dat_21;regsigned[7:0]dat_22;regsigned[7:0]dat_23;regsigned[7:0]dat_24;regsigned[7:0]dat_25;regsigned[7:0]dat_26;regsigned[7:0]dat_27;regsigned[7:0]dat_28;regsigned[7:0]dat_29;regsigned[7:0]dat_30;regsigned[7:0]dat_31;regsigned[7:0]dat_32;//信号延迟连采样always@(posedgei_50m_clk)if(dat_wei==4'd8)begin dat_1 <=i_dat; dat_2 <=dat_1 ; dat_3 <=dat_2 ; dat_4 <=dat_3 ; dat_5 <=dat_4 ; dat_6 <=dat_5 ; dat_7 <=dat_6 ; dat_8 <=dat_7 ; dat_9 <=dat_8 ; dat_10<=dat_9 ; dat_11<=dat_10; dat_12<=dat_11; dat_13<=dat_12; dat_14<=dat_13; dat_15<=dat_14; dat_16<=dat_15; dat_17<=dat_16; dat_18<=dat_17; dat_19<=dat_18; dat_20<=dat_19; dat_21<=dat_20; dat_22<=dat_21; dat_23<=dat_22; dat_24<=dat_23; dat_25<=dat_24; dat_26<=dat_25; dat_27<=dat_26; dat_28<=dat_27; dat_29<=dat_28; dat_30<=dat_29; dat_31<=dat_30; dat_32<=dat_31;end//对称位相加寄存器regsigned[8:0]dat_1_r ;regsigned[8:0]dat_2_r ;regsigned[8:0]dat_3_r ;regsigned[8:0]dat_4_r ;regsigned[8:0]dat_5_r ;regsigned[8:0]dat_6_r ;regsigned[8:0]dat_7_r ;regsigned[8:0]dat_8_r ;regsigned[8:0]dat_9_r;regsigned[8:0]dat_10_r;regsigned[8:0]dat_11_r;regsigned[8:0]dat_12_r;regsigned[8:0]dat_13_r;regsigned[8:0]dat_14_r;regsigned[8:0]dat_15_r;regsigned[8:0]dat_16_r;//对称位相加always@(posedgei_50m_clkornegedgei_rst_n)if(!i_rst_n)begin dat_1_r <=0; dat_2_r <=0; dat_3_r <=0; dat_4_r <=0; dat_5_r <=0; dat_6_r <=0; dat_7_r <=0; dat_8_r <=0; dat_9_r<=0; dat_10_r<=0; dat_11_r<=0; dat_12_r<=0; dat_13_r<=0; dat_14_r<=0; dat_15_r<=0; dat_16_r<=0; endelsebegin dat_1_r <=dat_1 +dat_32; dat_2_r <=dat_2 +dat_31 ; dat_3_r <=dat_3 +dat_30 ; dat_4_r <=dat_4 +dat_29 ; dat_5_r <=dat_5 +dat_28 ; dat_6_r <=dat_6 +dat_27 ; dat_7_r <=dat_7 +dat_26 ; dat_8_r <=dat_8 +dat_25 ; dat_9_r<=dat_9 +dat_24 ; dat_10_r<=dat_10+dat_23; dat_11_r<=dat_11+dat_22; dat_12_r<=dat_12+dat_21; dat_13_r<=dat_13+dat_20; dat_14_r<=dat_14+dat_19; dat_15_r<=dat_15+dat_18; dat_16_r<=dat_16+dat_17;end//查表地址wire[3:0]addr_1;wire[3:0]addr_2;wire[3:0]addr_3;wire[3:0]addr_4;assignaddr_1={dat_4_r[dat_wei],dat_3_r[dat_wei],dat_2_r[dat_wei],dat_1_r[dat_wei]};assignaddr_2={dat_8_r[dat_wei],dat_7_r[dat_wei],dat_6_r[dat_wei],dat_5_r[dat_wei]};assignaddr_3={dat_12_r[dat_wei],dat_11_r[dat_wei],dat_10_r[dat_wei],dat_9_r[dat_wei]};assignaddr_4={dat_16_r[dat_wei],dat_15_r[dat_wei],dat_14_r[dat_wei],dat_13_r[dat_wei]};//查表输出数据wiresigned[17:0]t_dat_1;wiresigned[17:0]t_dat_2;wiresigned[17:0]t_dat_3;wiresigned[17:0]t_dat_4;//查表模块table_1 u_0( .addr_1(addr_1 ), .addr_2(addr_2 ), .addr_3(addr_3 ), .addr_4(addr_4 ), .t_dat_1(t_dat_1), .t_dat_2(t_dat_2), .t_dat_3(t_dat_3), .t_dat_4(t_dat_4) );//查表结果数据处理wire[26:0]wei_dat_1;wire[26:0]wei_dat_2;wire[26:0]wei_dat_3;wire[26:0]wei_dat_4;assignwei_dat_1=t_dat_1<<dat_wei;assignwei_dat_2=t_dat_2<<dat_wei;assignwei_dat_3=t_dat_3<<dat_wei;assignwei_dat_4=t_dat_4<<dat_wei;//查表结果累加寄存器regsigned[27:0]add_shift_1;regsigned[27:0]add_shift_2;regsigned[27:0]add_shift_3;regsigned[27:0]add_shift_4;//第一部分查表结果累加always@(posedgei_50m_clkornegedgei_rst_n)if(!i_rst_n)add_shift_1<=0;elseif(dat_wei==4'd9)add_shift_1<=0;elseif(dat_wei==4'd8)add_shift_1<=add_shift_1-wei_dat_1;//符号位处理elseadd_shift_1<=add_shift_1+wei_dat_1;//第二部分查表结果累加always@(posedgei_50m_clkornegedgei_rst_n)if(!i_rst_n)add_shift_2<=0;elseif(dat_wei==4'd9)add_shift_2<=0;elseif(dat_wei==4'd8)add_shift_2<=add_shift_2-wei_dat_2;//符号位处理elseadd_shift_2<=add_shift_2+wei_dat_2;//第三部分查表结果累加always@(posedgei_50m_clkornegedgei_rst_n)if(!i_rst_n)add_shift_3<=0;elseif(dat_wei==4'd9)add_shift_3<=0;elseif(dat_wei==4'd8)add_shift_3<=add_shift_3-wei_dat_3;//符号位处理elseadd_shift_3<=add_shift_3+wei_dat_3;//第四部分查表结果累加always@(posedgei_50m_clkornegedgei_rst_n)if(!i_rst_n)add_shift_4<=0;elseif(dat_wei==4'd9)add_shift_4<=0;elseif(dat_wei==4'd8)add_shift_4<=add_shift_4-wei_dat_4;//符号位处理elseadd_shift_4<=add_shift_4+wei_dat_4;//一级加法模块regsigned[28:0]o_dat_1;always@(posedgei_50m_clkornegedgei_rst_n)if(!i_rst_n)o_dat_1<=0;elseif(dat_wei==4'd9)o_dat_1<=add_shift_1+add_shift_4;regsigned[28:0]o_dat_2;always@(posedgei_50m_clkornegedgei_rst_n)if(!i_rst_n)o_dat_2<=0;elseif(dat_wei==4'd9)o_dat_2<=add_shift_2+add_shift_3;//二级加法模块regsigned[29:0]o_dat_r;always@(posedgei_50m_clkornegedgei_rst_n)if(!i_rst_n)o_dat_r<=0;elseo_dat_r<=o_dat_1+o_dat_2;//八位数据输出assigno_dat=((o_dat_r+{!o_dat_r[29],{5'd14{o_dat_r[29]}}})>>5'd15);//对输出数据四舍五入endmodule查表模块moduletable_1( input[3:0]addr_1, input[3:0]addr_2, input[3:0]addr_3, input[3:0]addr_4, outputregsigned[17:0]t_dat_1, outputregsigned[17:0]t_dat_2, outputregsigned[17:0]t_dat_3, outputregsigned[17:0]t_dat_4 );parameter signedh_1=16'd50;parameter signedh_2=16'd62;parameter signedh_3=16'd90;parameter signedh_4=16'd136;parameter signedh_5=16'd201;parameter signedh_6=16'd285;parameter signedh_7=16'd388;parameter signedh_8=16'd506;parameter signedh_9=16'd634;parameter signedh_10=16'd767;parameter signedh_11=16'd898;parameter signedh_12=16'd1020;parameter signedh_13=16'd1128;parameter signedh_14=16'd1215;parameter signedh_15=16'd1275;parameter signedh_16=16'd1307;//地址always@(*)case(addr_1) 4'b0000:t_dat_1<=0; 4'b0001:t_dat_1<=h_1; 4'b0010:t_dat_1<=h_2; 4'b0011:t_dat_1<=h_1+h_2; 4'b0100:t_dat_1<=h_3; 4'b0101:t_dat_1<=h_3+h_1; 4'b0110:t_dat_1<=h_3+h_2; 4'b0111:t_dat_1<=h_3+h_2+h_1; 4'b1000:t_dat_1<=h_4; 4'b1001:t_dat_1<=h_4+h_1; 4'b1010:t_dat_1<=h_4+h_2; 4'b1011:t_dat_1<=h_4+h_2+h_1; 4'b1100:t_dat_1<=h_4+h_3; 4'b1101:t_dat_1<=h_4+h_3+h_1; 4'b1110:t_dat_1<=h_4+h_3+h_2; 4'b1111:t_dat_1<=h_4+h_3+h_2+h_1; default:t_dat_1<=0;endcase//地址always@(*)case(addr_2) 4'b0000:t_dat_2<=0; 4'b0001:t_dat_2<=h_5; 4'b0010:t_dat_2<=h_6; 4'b0011:t_dat_2<=h_6+h_5; 4'b0100:t_dat_2<=h_7; 4'b0101:t_dat_2<=h_7+h_5; 4'b0110:t_dat_2<=h_7+h_6; 4'b0111:t_dat_2<=h_7+h_6+h_5; 4'b1000:t_dat_2<=h_8; 4'b1001:t_dat_2<=h_8+h_5; 4'b1010:t_dat_2<=h_8+h_6; 4'b1011:t_dat_2<=h_8+h_6+h_5; 4'b1100:t_dat_2<=h_8+h_7; 4'b1101:t_dat_2<=h_8+h_7+h_5; 4'b1110:t_dat_2<=h_8+h_7+h_6; 4'b1111:t_dat_2<=h_8+h_7+h_6+h_5; default:t_dat_2<=0;endcase//地址always@(*)case(addr_3) 4'b0000:t_dat_3<=0; 4'b0001:t_dat_3<=h_9; 4'b0010:t_dat_3<=h_10; 4'b0011:t_dat_3<=h_9+h_10; 4'b0100:t_dat_3<=h_11; 4'b0101:t_dat_3<=h_11+h_9; 4'b0110:t_dat_3<=h_11+h_10; 4'b0111:t_dat_3<=h_11+h_10+h_9; 4'b1000:t_dat_3<=h_12; 4'b1001:t_dat_3<=h_12+h_9; 4'b1010:t_dat_3<=h_12+h_10; 4'b1011:t_dat_3<=h_12+h_10+h_9; 4'b1100:t_dat_3<=h_12+h_11; 4'b1101:t_dat_3<=h_12+h_11+h_9; 4'b1110:t_dat_3<=h_12+h_11+h_10; 4'b1111:t_dat_3<=h_12+h_11+h_10+h_9; default:t_dat_3<=0;endcase//地址always@(*)case(addr_4) 4'b0000:t_dat_4<=0; 4'b0001:t_dat_4<=h_13; 4'b0010:t_dat_4<=h_14; 4'b0011:t_dat_4<=h_13+h_14; 4'b0100:t_dat_4<=h_15; 4'b0101:t_dat_4<=h_15+h_13; 4'b0110:t_dat_4<=h_15+h_14; 4'b0111:t_dat_4<=h_15+h_14+h_13; 4'b1000:t_dat_4<=h_16; 4'b1001:t_dat_4<=h_16+h_13; 4'b1010:t_dat_4<=h_16+h_14; 4'b1011:t_dat_4<=h_16+h_14+h_13; 4'b1100:t_dat_4<=h_16+h_15; 4'b1101:t_dat_4<=h_16+h_15+h_13; 4'b1110:t_dat_4<=h_16+h_15+h_14; 4'b1111:t_dat_4<=h_16+h_15+h_14+h_13; default:t_dat_4<=0;endcaseendmoduleModelsim仿真测试文件`timescale 10ns/10nsmodule fir_tb;reg i_50m_clk;//系统时钟50Mreg i_rst_n;//系统复位信号wire[7:0]i_adc_data;//数据输入wire[7:0]o_dac_data;//数据输出 always #1 i_50m_clk=~i_50m_clk;//FIR模块时钟信号产生initialbegin #1i_50m_clk<=0;//FIR模块时钟信号初始化 #1i_rst_n<=0;//复位信号初始化 #5i_rst_n<=1'b1;end//FIR滤波模块例化fir u_0( .i_50m_clk(i_50m_clk), .i_rst_n(i_rst_n), .i_dat (i_adc_data), .o_dat(o_dac_data) );regi_10m_clk;initialbegin i_10m_clk<=0;//函数模块时钟信号初始化endalways#10i_10m_clk<=~i_10m_clk;//函数模块时钟信号产生//函数信号产生模块例化cos_wave u_1( .i_clk_n(i_10m_clk), .i_rst_n(i_rst_n), .cos_dat (i_adc_data) );endmodule测试波形发生模块module cos_wave( input i_clk_n,//时钟信号 input i_rst_n,//复位信号 outputreg[7:0]cos_dat//数据输出 );integer i=0;//控制输出数据变量reg[7:0]read_dat[1000:0];//读取MATLAB的采样点数寄存器initial $readmemh("cos.txt",read_dat);//加载MATLAB的采样数据//控制输出数据模块always@(posedgei_clk_nornegedgei_rst_n)if(!i_rst_n)i<=0;elseif(i<999)i<=i+1;elsei<=0;//数据输出模块always@(posedgei_clk_nornegedgei_rst_n)if(!i_rst_n)cos_dat<=0;elsecos_dat<=read_dat[i];endmodule6、MATLAB量化系数代码如下：clc;clearall;loadh.txt;%加载系数文件dat=h(1:1:length(h));width=16;%量化宽度16hh=round(dat.*(2^(width-1)-1));%量化取整%补码表示第十六位为符号位fori=1:1:length(h)ifhh(i)>0hh(i)=hh(i);elsehh(i)=hh(i)+2^width;endend7、使用MATLAB的产生波形的代码如下：clc;clearall;fs=5e6;%5M的采样率fc=0.1e6;%所要产生的信号频率fc2=0.35e6;%所要产生的信号频率ts=1/fs;%采样周期m=1000;%采样点数t=ts:ts:m*ts;%采样时间范围cos_wave=0.5*cos(2*pi*fc*t)+0.5*cos(2*pi*fc2*t);%混合信号的频率cos_wave=round(cos_wave*(2^7-1));%量化取整cos_dat=zeros(1,length(cos_wave));%产生同样长度的数组%符号的表示fori=1:length(cos_wave);ifcos_wave(i)>=0;%正数不变cos_dat(i)=cos_wave(i);elsecos_dat(i)=cos_wave(i)+2^8;%负数补码表示endend附录3：英文原文BuildingProgrammableAutomationControllerswithLabVIEWFPGAOverviewProgrammableAutomationControllers(PACs)aregainingacceptancewithintheindustrialcontrolmarketastheidealsolutionforapplicationsthatrequirehighlyintegratedanaloganddigitalI/O,floating-pointprocessing,andseamlessconnectivitytomultipleprocessingnodes.NationalInstrumentsoffersavarietyofPACsolutionspoweredbyonecommonsoftwaredevelopmentenvironment,NILabVIEW.WithLabVIEW,youcanbuildcustomI/Ointerfacesforindustrialapplicationsusingadd-onsoftware,suchastheNILabVIEWFPGAModule.WiththeLabVIEWFPGAModuleandreconfigurableI/O(RIO)hardware,NationalInstrumentsdeliversanintuitive,accessiblesolutionforincorporatingtheflexibilityandcustomizabilityofFPGAtechnologyintoindustrialPACsystems.YoucandefinethelogicembeddedinFPGAchipsacrossthefamilyofRIOhardwaretargetswithoutknowinglow-levelhardwaredescriptionlanguages(HDLs)orboard-levelhardwaredesigndetails,aswellasquicklydefinehardwareforultrahigh-speedcontrol,customizedtimingandsynchronization,low-levelsignalprocessing,andcustomI/Owithanalog,digital,andcounterswithinasingledevice.YoualsocanintegrateyourcustomNIRIOhardwarewithimageacquisitionandanalysis,motioncontrol,andindustrialprotocols,suchasCANandRS232,torapidlyprototypeandimplementacompletePACsystem.TableofContents\l"toc0"Introduction\l"toc1"NIRIOHardwareforPACs\l"toc2"BuildingPACswithLabVIEWandtheLabVIEWFPGAModule\l"toc3"FPGADevelopmentFlow\l"toc4"UsingNISoftMotiontoCreateCustomMotionControllers\l"toc5"Applications\l"toc6"ConclusionIntroductionYoucanusegraphicalprogramminginLabVIEWandtheLabVIEWFPGAModuletoconfiguretheFPGA(field-programmablegatearray)onNIRIOdevices.RIOtechnology,themergingofLabVIEWgraphicalprogrammingwithFPGAsonNIRIOhardware,providesaflexibleplatformforcreatingsophisticatedmeasurementandcontrolsystemsthatyoucouldpreviouslycreateonlywithcustom-designedhardware.AnFPGAisachipthatconsistsofmanyunconfiguredlogicgates.Unlikethefixed,vendor-definedfunctionalityofanASIC(application-specificintegratedcircuit)chip,youcanconfigureandreconfigurethelogiconFPGAsforyourspecificapplication.FPGAsareusedinapplicationswhereeitherthecostofdevelopingandfabricatinganASICisprohibitive,orthehardwaremustbereconfiguredafterbeingplacedintoservice.Theflexible,software-programmablearchitectureofFPGAsofferbenefitssuchashigh-performanceexecutionofcustomalgorithms,precisetimingandsynchronization,rapiddecisionmaking,andsimultaneousexecutionofparalleltasks.Today,FPGAsappearinsuchdevicesasinstruments,consumerelectronics,automobiles,aircraft,copymachines,andapplication-specificcomputerhardware.WhileFPGAsareoftenusedinindustrialcontrolproducts,FPGAfunctionalityhasnotpreviouslybeenmadeaccessibletoindustrialcontrolengineers.DefiningFPGAshashistoricallyrequiredexpertiseusingHDLprogrammingorcomplexdesigntoolsusedmorebyhardwaredesignengineersthanbycontrolengineers.WiththeLabVIEWFPGAModuleandNIRIOhardware,younowcanuseLabVIEW,ahigh-levelgraphicaldevelopmentenvironmentdesignedspecificallyformeasurementandcontrolapplications,tocreatePACsthathavethecustomization,flexibility,andhigh-performanceofFPGAs.BecausetheLabVIEWFPGAModuleconfigurescustomcircuitryinhardware,yoursystemcanprocessandgeneratesynchronizedanaloganddigitalsignalsrapidlyanddeterministically.Figure1illustratesmanyoftheNIRIOdevicesthatyoucanconfigureusingtheLabVIEWFPGAModule.Figure1.LabVIEWFPGAVIBlockDiagramandRIOHardwarePlatformsNIRIOHardwareforPACsHistorically,programmingFPGAshasbeenlimitedtoengineerswhohavein-depthknowledgeofVHDLorotherlow-leveldesigntools,whichrequireovercomingaverysteeplearningcurve.WiththeLabVIEWFPGAModule,NIhasopenedFPGAtechnologytoabroadersetofengineerswhocannowdefineFPGAlogicusingLabVIEWgraphicaldevelopment.Measurementandcontrolengineerscanfocusprimarilyontheirtestandcontrolapplication,wheretheirexpertiselies,ratherthanthelow-levelsemanticsoftransferringlogicintothecellsofthechip.TheLabVIEWFPGAModulemodelworksbecauseofthetightintegrationbetweentheLabVIEWFPGAModuleandthecommercialoff-the-shelf(COTS)hardwarearchitectureoftheFPGAandsurroundingI/Ocomponents.NationalInstrumentsPACsprovidemodular,off-the-shelfplatformsforyourindustrialcontrolapplications.WiththeimplementationofRIOtechnologyonPCI,PXI,andCompactVisionSystemplatformsandtheintroductionofRIO-basedCompactRIO,engineersnowhavethebenefitsofaCOTSplatformwiththehigh-performance,flexibility,andcustomizationbenefitsofFPGAsattheirdisposaltobuildPACs.NationalInstrumentsPCIandPXIRSeriesplug-indevicesprovideanaloganddigitaldataacquisitionandcontrolforhigh-performance,user-configurabletimingandsynchronization,aswellasonboarddecisionmakingonasingledevice.Usingtheseoff-the-shelfdevices,youcanextendyourNIPXIorPCIindustrialcontrolsystemtoincludehigh-speeddiscreteandanalogcontrol,customsensorinterfaces,andprecisetimingandcontrol.NICompactRIO,aplatformcenteredonRIOtechnology,providesasmall,industriallyrugged,modularPACplatformthatgivesyouhigh-performanceI/Oandunprecedentedflexibilityinsystemtiming.YoucanuseNICompactRIOtobuildanembeddedsystemforapplicationssuchasin-vehicledataacquisition,mobileNVHtesting,andembeddedmachinecontrolsystems.TheruggedNICompactRIOsystemisindustriallyratedandcertified,anditisdesignedforgreaterthan50gofshockatatemperaturerangeof-40to70°C.NICompactVisionSystemisaruggedmachinevisionpackagethatwithstandstheharshenvironmentscommoninrobotics,automatedtest,andindustrialinspectionsystems.NICVS-145xdevicesofferunprecedentedI/Ocapabilitiesandnetworkconnectivityfordistributedmachinevisionapplications.NICVS-145xsystemsuseIEEE1394(FireWire)technology,compatiblewithmorethan40cameraswithawiderangeoffunctionality,performance,andprice.NICVS-1455andNICVS-1456devicescontainconfigurableFPGAssoyoucanimplementcustomcounters,timing,ormotorcontrolinyourmachinevisionapplication.BuildingPACswithLabVIEWandtheLabVIEWFPGAModuleWithLabVIEWandtheLabVIEWFPGAModule,youaddsignificantflexibilityandcustomizationtoyourindustrialcontrolhardware.BecausemanyPACsarealreadyprogrammedusingLabVIEW,programmingFPGAswithLabVIEWiseasybecauseitusesthesameLabVIEWdevelopmentenvironment.WhenyoutargettheFPGAonanNIRIOdevice,LabVIEWdisplaysonlythefunctionsthatcanbeimplementedintheFPGA,furthereasingtheuseofLabVIEWtoprogramFPGAs.TheLabVIEWFPGAModuleFunctionspaletteincludestypicalLabVIEWstructuresandfunctions,suchasWhileLoops,ForLoops,CaseStructures,andSequenceStructuresaswellasadedicatedsetofLabVIEWFPGA-specificfunctionsformath,signalgenerationandanalysis,linearandnonlinearcontrol,comparisonlogic,arrayandclustermanipulation,occurrences,analoganddigitalI/O,andtiming.YoucanuseacombinationofthesefunctionstodefinelogicandembedintelligenceontoyourNIRIOdevice.Figure2showsanFPGAapplicationthatimplementsaPIDcontrolalgorithmontheNIRIOhardwareandahostapplicationonaWindowsmachineoranRTtargetthatcommunicateswiththeNIRIOhardware.Thisapplicationreadsfromanaloginput0(AI0),performsthePIDcalculation,andoutputstheresultingdataonanalogoutput0(AO0).WhiletheFPGAclockrunsat40MHztheloopinthisexamplerunsmuchslowerbecauseeachcomponenttakeslongerthanone-clockcycletoexecute.AnalogcontrolloopscanrunonanFPGAatarateofabout200kHz.Youcanspecifytheclockrateatcompiletime.ThisexampleshowsonlyonePIDloop;however,creatingadditionalfunctionalityontheNIRIOdeviceismerelyamatterofaddinganotherWhileLoop.UnliketraditionalPCprocessors,FPGAsareparallelprocessors.AddingadditionalloopstoyourapplicationdoesnotaffecttheperformanceofyourPIDloop.Figure2.PIDControlUsinganEmbeddedLabVIEWFPGAVIwithCorrespondingLabVIEWHostVI.FPGADevelopmentFlowAfteryoucreatetheLabVIEWFPGAVI,youcompilethecodetorunontheNIRIOhardware.Dependingonthecomplexityofyourcodeandthespecificationsofyourdevelopmentsystem,compiletimeforanFPGAVIcanrangefromminutestoseveralhours.Tomaximizedevelopmentproductivity,withtheRSeriesRIOdevicesyoucanuseabit-accurateemulationmodesoyoucanverifythelogicofyourdesignbeforeinitiatingthecompileprocess.WhenyoutargettheFPGADeviceEmulator,LabVIEWaccessesI/OfromthedeviceandexecutestheVIlogicontheWindowsdevelopmentcomputer.Inthismode,youcanusethesamedebuggingtoolsavailableinLabVIEWforWindows,suchasexecutionhighlighting,probes,andbreakpoints.OncetheLabVIEWFPGAcodeiscompiled,youcreateaLabVIEWhostVItointegrateyourNIRIOhardwareintotherestofyourPACsystem.Figure3illustratesthedevelopmentprocessforcreatinganFPGAapplication.ThehostVIusescontrolsandindicatorsontheFPGAVIfrontpaneltotransferdatabetweentheFPGAontheRIOdeviceandthehostprocessingengine.ThesefrontpanelobjectsarerepresentedasdataregisterswithintheFPGA.ThehostcomputercanbeeitheraPCorPXIcontrollerrunningWindowsoraPC,PXIcontroller,CompactVisionSystem,orCompactRIOcontrollerrunningareal-timeoperatingsystem(RTOS).Intheaboveexample,weexchangethesetpoint,PIDgains,looprate,AI0,andAO0datawiththeLabVIEWhostVI.Figure3.LabVIEWFPGADevelopmentFlowTheNIRIOdevicedriverincludesasetoffunctionstodevelopacommunicationinterfacetotheFPGA.ThefirststepinbuildingahostVIistoopenareferencetotheFPGAVIandRIOdevice.TheOpenFPGAVIReferencefunction,asseeninFigure2,alsodownloadsandrunsthecompiledFPGAcodeduringexecution.Afteropeningthereference,y