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1、VCA810 翻译FEATURES_ HIGH GAIN ADJUST RANGE: _40dB_ DIFFERENTIAL IN/SINGLE-ENDED OUT_ LOW INPUT NOISE VOLTAGE: 2.4nV/_Hz_ CONSTANT BANDWIDTH vs GAIN: 35MHz_ HIGH dB/V GAIN LINEARITY: _0.3dB_ GAIN CONTROL BANDWIDTH: 25MHz_ LOW OUTPUT DC ERROR: 80dB. Signal bandwidndslew rate remain constant over the en

2、tire gain adjust range. This 40dB/V gain control is accurate within 1.5dB (0.9dB for High Grade), allowing the gain control voltage in an AGC application to be used as a Received Signal Strength Indicator (RSSI) with 1.5dB accuracy.Excellent common-mode rejection and common-mode input range at the t

3、wo high-impedance inputs allow the VCA810 to provide a differential receiver operation with gain adjust. Theoutput signal is referenced to ground. Zero differential inputvoltage gives a 0V output wismall DC offset error. Lowinput noise voltage ensures good output SNR at the highest gain settings.In

4、applications where pulse edge information is critical, andthe VCA810 is being used to equalize varying channel loss,minimal change in group delay over gain setting will retain excellent pulse edge information.An improved output stage provides adequate outpurrentto drive the most demanding loads. Whi

5、le principallyendedto driveog-to-digital converters (A) or 2nd-stagelifiers, the 60mA outp doubly-terminated 50 lines orover the 1.7V output voltage range.urrent will easily drivesivet filter stageThe VCA810 is a high gain adjust range, wideband,voltagelifier wivoltage-controlled gain, as shownin Fi

6、gure 1. The circuits basic voltagelifier respondslifier. At itsto the control of aninput, the voltageernal gain-controllifiresents the high impedance ofa differential stage, permitting flexible input impedancematching. To preserve termination options, noernalcircuitry connects to the input bases of

7、this differential stage. For this reason, the user must provide DC paths for the input base currents from a signal source, either through a grounded termination resistor or by a direct connectionto ground. The differential input stage also permitsrejection of common-mode signals. At its output, thev

8、oltagelifiresents a low impedance, simplifyingimpedance matching. An open-loop design produwidebandwidt all gain settings. A ground-referenceddifferential to single-ended converthe low output offset voltage.at the output retainsA gain control voltage, VC, controls thelifier gainmagnitude through a h

9、igh-speed control circuit. Gainpolarity can be either inverting or non-inverting, dependingupon thelifier input driven by the input signal. The gaincontrol circuit presents the high-input impedance of anon-inverting opconnection. The control voltagnis referred to ground as shown in Figure 1. The con

10、trolvoltage VC varies thelifier gain according to theexponential relationship G_V_V_ _ 10_2(VC_1).This translates to the log gain relationshipG(dB) 40 _ _VC_1_ dB. Thus, G(dB) varies linearlyover the specified 40dB to +40dB range as VC varies from0V to 2V. Optionally, making VC slightlyitive (+0.15V

11、) effectively disables thelifier, giving 80dB ofsignal pattenuationow frequencies.ernally, the gain-control circuit varies thelifier gainby varying the transconductance, gm, of aolartransistor using the transistor bias current. Varying the bias currents of differential stages varies gm to control th

12、e voltage gain of the VCA810. A gm-based gain adjust normally suffers poor thermal stability. The VCA810 includes circuitry to minimize this effect.Figure 2 shows the circuit configuration used as the basisof the Electrical Characteristics and TypicalCharacteristics. Voltage swings reportedhespecifi

13、cations are taken directly at the input and outputpins. For test pures, the input impedance is set to 50to ground. A 25wi(RT) isincluded on the V input to get bias current cancellation. Proper supply bypassing is shown in Figure 2, andconsists of two capacitors on each supply pin: one largeelectroly

14、tic capacitor (2.2F to 6.8F), effectiveowerfrequencies, and one small ceramic capacitor (0.1F) forhigh frequency decoupling. For more information ondecoupling, refer to thLayout section.The voltage-controlled gain feature of the VCA810 makesthislifier ideal for preciAGC applications withcontrol rang

15、es as large as 60dB. The AGC circuit ofFigure 4 adds an opand diode forlitudedetection, a hold capacitor to store the control voltage andresistors R1 through R3t determine attack and releasetimes. Resistor R4 and capacitor the AGC feedback loop. The opitive peaks of output VO wihase compensate compa

16、res theDC reference voltage,VR. Whenever a VO peak exceeds VR, the OPA820 outputswingsitive, forward-biasing the diode and chargingthe holding capacitor. This charge drives the capacitorvoltage in aitive direction, reducing thelifier gain.R3 and the CH largely determine the attack time of this AGC c

17、orrection.特点:高增益的调整范围: 40dB差分输入/单端输出输入噪声电压:2.4nV/_Hz稳定的增益带宽:35MHz高分贝增益线性: 0.3dB / V增益控制带宽: 25MHz低产出的直流误差: 80dB。信号带宽和压摆率保持在整个增益调节范围内保持恒定。这 40db/ V 增益控制在1.5 db(最高误差范围0.9 db),让应用程序在一个 AGC 增益控制电压精确到作为接收信号强度指示器(RSSI)的使用精度为1.5 db。出色的共模抑制和两个高阻抗输入的共模输入范围允许 VCA810 提供一个增益调节差分接收器的操作。输出信号是相对于地面。零差分输入电压提供了一个带有小的

18、直流偏移误差 0V 输出。低输入噪声电压,确保在最高增益设置好输出信噪比。在应用脉冲边缘信息是 的,正在使用的 VCA810 变信道损失,以平衡,最小增益设置的变动将在留住优秀延迟脉冲的边缘信息。一种改进的输出级提供了足够的输出电流来驱动最苛刻的负载。而主要用于驱动模拟到数字转换器(ADC)或第二级放大器, 60mA 的输出电流将轻松驱动双端 50 或 后在 1.7V的输出电压范围筛选阶段。电源 6.5VDC功耗见热分析组差分输入电压Vs输入共模电压范围Vs温度范围.-40 C 至+125 C引线温度(焊接,10 秒)+300 C结温+150的额定 ESD( 模型)V(电荷器件模型)V(机器模

19、型)V以上这些等级,就可能造成性。长时间在绝对最大条件可能会降低器件的可靠性。这些仅仅是极限参数,以及设备的功能操作在这些或超出规定的,并不意味着在任何其他条件者。静电放电敏感度这可能会损坏集成电路的静电放电。德州仪器建议所有集成电路用适当的预防措施处理。如果正确的搬运和安装程序,可以造成损坏。ESD 损害的范围可以从细微的性能下降,完成设备故障。精密集成电路可能更容易受到,因为很小的参数变化可能导致设备不能满足其的规格。应用信息电路描述该 VCA810 是一种高增益调整了电压控制增益,如图 1 所示,范围,宽带,电压放大器。该电路的基本电压放大器响应了增益控制放大器控制。在它的输入,电压放大

20、器介绍了高阻抗的差分阶段,允许灵活的输入阻抗匹配。为了终端的选择,没有电路连接到这个阶段的差分输入。出于这个原因,用户必须为从信号源输入基本直流电流路径,通过一个终端电阻接地或直接连接到地。差分输入级也允许共模信号的抑制。在其输出端,电压放大器提出一个低阻抗,从而简化了阻抗匹配。开环设计生产在所有增益设置宽的带宽。以地为参考的差分至单端输出的转换会保留在低输出失调电压。一个增益控制电压 VC,控制通过一个高速控制电路放大器增益的大小。增益可以是极性反相或非反相,经输入信号驱动放大器的输入而定。增益控制电路提出了一个非反相运算放大器连接高输入阻抗。控制电压引脚被称为接地。这关系到增益与 db 的关系式: Gdb=-40(Vg+1)db。因此,db 线性变化在指定的- 40dB至+40 dB

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