大二数字电路chapter6

1、Digital integrated circuitsChapter Transistor-transistor logicTransistor-Transistor logicN P N c : Collector b : Base e : emitterCollector-to-base junctionEmitter-to-base junctionTransistor-Transistor logice (emitter)VCC=+5vRbIbIcRcVINVOUTVcec (collector)b (Base)VbeHFE=IC/IBWhen Vb0.5v (logic 0), Th

2、e e-b junction is reverse biasedIb=0mA, Vbe=0v, The c-b junction is reverse biased Ic=0mA ,Vce=Vcc; the transistor is cutoff VcVcc.Transistor-Transistor logicVCC=+5vRbIbIcRcVcVceVbeVbVeVINWhen VbVc The e-b junction is forward biasedVbe=Vbe(SAT)=0.7v ; Ib=Ib(SAT)=(VIN-Vb)/Rb ; The c-b junction is for

3、ward biasedVce= VCE(SAT);Ic= Ic(SAT)=(Vcc-Vce)/Rc ; the transistor is in saturation.Vc= VCE(SAT)=0.3v;Transistor-Transistor logicVCC=+5vRbIbIcRcVcVceVbeVbVeVINWhen VbVc The c-b junction is forward biasedVbe=Vbe(SAT)=0.7v ; Ib=Ib(SAT)=(VIN-Vbe)/Rb ; The e-b junction is forward biasedVce= VCE(SAT);Ic=

4、 Ic(SAT)=(Vcc-Vce)/Rc ; the transistor is in saturation.Vc= VCE(SAT)=0.3v;Transistor-Transistor logicVCCswitchVc=VceTotem-pole output stageThe constant impedance reduced signal glitches and provided increased ability to drive capacitance loads.Q1 and Q2 form the output stage.The output is a logic 0

5、when Q2 is saturated and Q1 is cut off.The output impedance is low independent of the logic state because one transistor (either Q1 or Q2 )is on independent of logic state.Transistor-Transistor logicRQ1Q2D1VoutVccTransistor-Transistor logicTotem-pole output being driven by a phase splitter stageThe

6、two transistors (Q1 and Q2 ) of the totem-pole output stage must switch oppositely one from the other.The base input signal of each must be 180 degree out of phase.This is plished by using a phase circuit.RQ1Q2D1VoutVccphase splitterTotem poleQ3VinTransistor-Transistor logicTotem-pole output being d

7、riven by a phase splitter stageVin=0, Q3 is cut offA high voltage at the collectorQ1 is saturated.A lower voltage at the emitterQ2 is cutoff.Vout=1RQ1Q2D1“1”Vccphase splitterTotem poleQ3“0”“1”“0”Transistor-Transistor logicVin=1RQ1Q2D1Vcc(+5v)phase splitterTotem poleQ33.2v2.8vVbes=Vb-Ve = 0.7v2.5vVce

8、s= Vc-Ve=0.3vTransistor-Transistor logic3.2vRQ1Q2D1“0”Vcc(+5v)phase splitterTotem poleQ32.8v2.5vD2.8v VD Q1 is cut offQ2 is saturatedTransistor-Transistor logicTotem-pole output being driven by a phase splitter stageVin=1, Q3 is saturatedVbes=Vb-Ve = 0.7v, Vces= Vc-Ve=0.3vVb2=Ve3=3.2-0.7=2.5v Vb1=Vc

9、3=2.5+0.3=2.8vQ1 is cut off.Q2 is saturated.Vout=0RQ1Q2D1“0”Vcc(+5v)phase splitterTotem poleQ33.2v“0”2.5vTwo-input TTL NAND gateMultiple-emitter transistorD1 D2 Dx Dy VccA B X Q1 VccebcTotem polephase splitterTwo-input TTL NAND gateR4Q1Q2D1 CVccQ3A B R2R1R34k1.6k1301kQ4Two-input TTL NAND gateA=B=1Bo

10、th input emitter-base junctions are reverse biased and act as open switch.R4Q4Q3D1 CVccTotem poleQ2A B R2R1R34k1.6k1301kQ1phase splitterVinTwo-input TTL NAND gateA B Q1 VccebcVinD1 D2 VccVinVin=Vcc=1A=B=1, both diodes are reverse biased and act as open switchTwo-input TTL NAND gateR4Q4Q3D1 CVccTotem

11、 poleQ2A B R2R1R34k1.6k1301kQ1Vinphase splitterA=B=1 Q1 is cut offVin=Vcollector=1Q2 is saturated.Q4 is cut off.Q3 is saturated. C=0Two-input TTL NAND gateR4Q4Q3D1 CVccTotem poleQ21 1 R2R1R34k1.6k1301kQ1Vinphase splitterVbTwo-input TTL NAND gateA=B=1Both input emitter-base junctions are reverse bias

12、ed and act as open switch.Q1 is cut offVin=Vcollector=1Q2 is saturated.Q4 is cut off.Q3 is saturated.C=0R4Q4Q3D1 CVccTotem poleQ2A B R2R1R34k1.6k1301kQ1Vinphase splitterTwo-input TTL NAND gateA=B=1Both input emitter-base junctions are reverse biased and act as open switch.Q1 is cut offVin=Vcollector

13、=1Q2 is saturated.Q4 is cut off.Q3 is saturated.C=0R14kQ1 Q1 A=1 B=1 e1e2bVcc=+5vQ1 Q2 Q3 bcbbebeC=0: off: onA=0Input emitter-base junctions A is forward biased and act as close switch.Two-input TTL NAND gateR4Q4Q3D1 CVccTotem poleQ2A B R2R1R34k1.6k1301kQ1Vinphase splitterTwo-input TTL NAND gateA=0.

14、4v=Ve R4Q4Q3D1 CVccTotem poleQ2B R2R1R34k1.6k1301kQ1Vinphase splitterQ1: Vb= Ve+Vbe=1.1vVOL=0.4Q1 is saturated Vin=Vc = Ve+Vces=0.4+0.3=0.7A=0Input emitter-base junctions A is forward biased and act as close switch.Q1 is saturatedVin= =Vcollector= 0Q2 is cut offQ4 is saturated.Q3 is cut off. C=1Two-

15、input TTL NAND gateR4Q4Q3D1 CVccTotem poleQ2A B R2R1R34k1.6k1301kQ1Vinphase splitter0.4+0.7A=0Input emitter-base junctions A is forward biased and act as close switch.Q1 is saturatedVin= =Vcollector= 0Q2 is cut offQ4 is saturated.Q3 is cut off. C=1Two-input TTL NAND gateQ1 Q1 A=0 B=1 e1e2bVcc=+5vQ4

16、D1 Q3 bcbcbC=1: off: onR21.6kQ1 be 2vO/V 5 4 3 2 1 0 3.6V .48V 0.2V 1 2 E c b a A 0.4V 1.1V 1.2V vI/V VOR4Q4Q3D1VccQ2R2R1R34k1.6k1301kQ1 VITTL voltage transfer curveTransistor-Transistor logicStandard TTLLow-power TTLHigh-speed TTLLow-power SchottkySchottkyAdvanced low-power schottkyAdvanced Schottk

17、yTTL circuit parameters (P169)IOL, output current low This is the maximum output terminal sink current, when the output voltage is a logical 0, that will guarantee a logical 0 output.The value of this parameter is dependent on the logic family.IOH, output current high This is the maximum output sour

18、ce current, when the output voltage is a logical 1, that will guarantee a logical 1 output.The value of this parameter is dependent on the logic family.TTL circuit parameters (P169)IIL, current input low This is the maximum input current, when the input voltage represent a logical 0. The value of th

19、is parameter is dependent on the TTL subfamily.IIH, current input high This is the maximum at the input terminal when the input voltage represent a logical 1.The value of this parameter is dependent on the TTL subfamily.TTL circuit parameters (P169)VOL, voltage output low This is the maximum allowab

20、le output voltage that can represent a logic 0.The value of this parameter is dependent on the TTL subfamily.VOH, voltage output highThis is the minimum allowable output voltage that can represent a logic 1.The value of this parameter is dependent on the TTL subfamily.TTL circuit parametersVIL, volt

21、age input low This is the maximum logic 0 input voltage.VIL=0.8vVIH, voltage input highThis is the minimum logic 1 input voltage.VIH=2.0vFan-outThe number of gate inputs that a single gate output can drive and still maintain voltage and current specifications.TTL circuit parameterstpLH , propagation

22、 delay time from output low to highThis is the delay between the input and output voltage levels as the output changes (propagates) from a logical 0 to a logical 1.tpHL , propagation delay time from output high to lowThis is the delay between the input and output voltage levels as the output changes

23、 (propagates) from a logical 1 to a logical 0.Open Collector TTL CircuitsThe output drive transistors collector is left open.An output stage requires an external pull-up resister.It is up to the user to connect the output pin of the gate to an external load that is pulled up to an external power sou

24、rce.Q3 CVccQ2A B R2R1R34k1.6k1kQ1D1D2Open Collector TTL CircuitsThe purpose of the open collector is to provide logic level shifting, drivers to relays or displays, or wired OR connection.Q3 CVccQ2A B R2R1R34k1.6k1kQ1D1D2Open Collector TTL CircuitsQ3 CVccQ2A B R2R1R34k1.6k1kQ1D1D2ABVcc+6vABOpen Coll

25、ector TTL CircuitsApplicationAct as interface circuit, providing logic level shiftingTTL : (0.3v 3.6v)CMOS : (0.3v12v)Vcc+12vTTLCMOSOpen Collector TTL CircuitsApplicationRLmax =(VCC-VOH)/(nIOH+mIIH)OUTPUT=1Vcc+6vRLPOpen Collector TTL CircuitsApplicationRLmin =(VCC-VOL)/(IOL-mIIL)OUTPUT=0Vcc+6vRLPOpe

26、n Collector TTL CircuitsApplicationWired-OR connections.( (AB)+(CD)+(EF) ) = (AB)(CD)(EF)ABCDEFVccEx. Design an open-collector to interface with another logic family that requires difference logic levels. Also perform a logical OR at the output of the open collector.Calculate the range of values for

27、 RL.A fan to eight gates is required.ABCDEFP=(X+Y+Z)VccLet the logic function beP= (X+Y+Z)XYZRLLet the other logic family (8 gates) logic values be VIL=0.8v, VIH=5vIIH=50uA, IIL=1mALet the OC logic values be VOL=0.6v, VOH=5vIOH=250uA, IOL=16mAABCDEFP=(X+Y+Z)Vcc8 gates VIL=0.8v, VIH=5vIIH=50uA, IIL=1

28、mAOC gateVOL=0.6v, VOH=5vIOH=250uA, IOL=16mAIRL=mIOH (OC) + nIIH =3*250+8*50=1150uAABCDEFP=(X+Y+Z)=1VccXYZRLRL=(VCC-VOH)/IRL=(6v-5v)/1150uA=870ohmRLmax=870ohmRL=(VCC-VOH)/IRL=(6v-0.6v)/8mA=675ohmRLmin=675ohm8 gates VIL=0.8v, VIH=5vIIH=50uA, IIL=1mAOC gateVOL=0.6v, VOH=5vIOH=250uA, IOL=16mAABCDEFP=(X

29、+Y+Z)=0VccXYZRLThe worst condition, X=1,Y=Z=0IRL=1*IOL(OC) - nIIL=16-8*1=8mATristate TTL DevicesTristate enable=0D2,D3 be forward biased.Q2 be cutoffQ3 be cutoffQ4 be cutoffHigh impedance R4Q4Q3D1 CVccTotem poleQ2A B R2R1R34k1.6k1301kQ1phase splitterTristate enableD2D3Schmitt triggerIt is built by N

30、AND gate.RS latchDiodevoltage excursionVR=Vi+0.7RSQQViG2 G1G3Vo3Schmitt triggerRSQQViG2 G1G3Vo3R-S NAND LatchR=1, S=1 Qn+1=Q; R=1, S=0 Qn+1=1; R=0, S=1 Qn+1=0; Schmitt triggerVi is a triangle-wave RSQQViG2G1G3Vo3Vi0.71.4Vi 0.7v, R = Vi+0.7 1.4v, R=0Vo3Vo3 = 1, S=1QR=0, S=1, Q=0Schmitt triggerVi is a triangle-wave Vi0.71.4Vi= 0.7v, R = Vi+0.7=1.4v, R=1QVo3Vo3 = 1, S=1R=1, S=1, Q remains on 0RSQQViG2G1G3Vo3Schmitt triggerVi is a triangle-wave Vi0.71.4Vo3Vo3 = 1, S=1QR=1, S=1, Q remains on 00.7Vi1.4v, R=1RSQQViG2G1G3Vo3Vi0.71.4Vo3Vo3 = 0, S=0QR=1, S=0, Q =1Vi=1.4vR = Vi+0.71.4v, R=1RSQQViG2G1G3