28335ECAN测试完整程序和实验记录

1、Word文档资料Word文档资料M ARSCold MiracleDsp28335实验源码库键入文档副标题letchgo/#DSP28335文库源代码系列1 :一：说明：/ FILE:DSP2833x_ECan.c/ TITLE:DSP2833x Enhanced CANInitialization & Support Functions.声明：由于百度文库不能上传代码，故将can通讯测试程序整理到 word文档，大家可以参考，并配有 实验结果，只需要简单的移植既可 以使用，请勿盗版！/DSP28335 ECAN 测试:/# # #/ $TI Release: DSP2833x/DSP2823

2、x C/C+ Header Files V1.31 $/ $Release Date: August 4, 2009 $DSP2Si2x Adc.c201/2/lS 113QJ C A+-?rn 1/3H01W7 2013/2Z18 11 力 7 2013/2/1B 11X)7/#ASM? KR#ASM文件#DSP2fl3 3x_DMA_c口 5P2日”冗ECan抵DSP24IJ Jx_ijlobalva blf De fc.cDSP2fl3x_PitiVect.cDSPZfU,ytrLrDSP38 打左 inDel ty .anb?d rnpleiiixE： l i iA_to_EJ_Xii

3、nl.c2ai3/ifl8 1150720111:422013/J/1B 11E2U1J/ZZ10 Ilf/ 3013/7/18 ll：07 POM/12/5 1773/2/18 11:07上015，1图1上CM匚文件22 K&C16 KB#include DSP2833x_Device.h/：DSP2833x Headerfile Include File BKB:#include DSP2833x_Examples.h / .之弟 DSP2833x Examples Include File C立:由B KU上图为参考C文件，在官方例程中都 有，下面贴出重要 C文件的代码。二：代码部分两个

4、主要C文件的代码，其他 C文件大 家自己添加就可以了，本部分程序是AB两个can 口之间相互通讯，如果需要源 代码，可以发我：letchgo163.DSP2833x_ECan :/ TI File $Revision: /main/8 $/ Checkin $Date: June 25, 200815:19:07 $/ InitECan:/ This function initializes the eCAN module to a known state./void InitECan(void)InitECana();#if DSP28_ECANBInitECanb();ECanaShado

5、w.CANRIOC.bit.RXFUNC#endif if DSP28_ECANB=1；ECanaRegs.CANRIOC.all =ECanaShadow.CANRIOC.all;void InitECana(void)/InitializeeCAN-A module/* Create a shadow register structure for the CAN control registers. This isneeded, since only 32-bit access is allowed to these registers. 16-bit accessto these reg

6、isters could potentially corrupt the register contents or returnfalse data. This is especially true while writing to/reading from a bit(or group of bits) among bits 16 - 31 */* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */ HECCmode also enables time-stampingfeature 事件抽样特征EC

7、anaShadow.CANMC.all = ECanaRegs.CANMC.all;ECanaShadow.CANMC.bit.SCB = 1;ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;struct ECAN_REGS ECanaShadow;EALLOW;/EALLOW enables access to protected bits/* Initialize all bits of Master Control Field to zero */ Some bits of MSGCTRL register come up in an unknow

8、n state. For proper operation,/ all bits (including reserved bits) of MSGCTRL must be initialized to zero/* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all，配置 GPIO 引脚为CAN通讯ECanaShadow.CANTIOC.bit.TXFUNC = 1;ECanaRegs.CANTIOC.all = ECan

9、aShadow.CANTIOC.all;ECanaShadow.CANRIOC.all =ECanaRegs.CANRIOC.all;ECanaMboxes.MBOX0.MSGCTRL.all = 0 x00000000;ECanaMboxes.MBOX1.MSGCTRL.all = 0 x00000000;ECanaMboxes.MBOX2.MSGCTRL.all = 0 x00000000;ECanaMboxes.MBOX3.MSGCTRL.all = 0 x00000000;ECanaMboxes.MBOX4.MSGCTRL.all = 0 x00000000;ECanaMboxes.M

10、BOX5.MSGCTRL.all = 0 x00000000;ECanaMboxes.MBOX6.MSGCTRL.all = 0 x00000000;ECanaMboxes.MBOX7.MSGCTRL.all = 0 x00000000;ECanaMboxes.MBOX8.MSGCTRL.all = 0 x00000000;ECanaMboxes.MBOX9.MSGCTRL.all = 0 x00000000;ECanaMboxes.MBOX10.MSGCTRL.all = 0 x00000000;ECanaMboxes.MBOX11.MSGCTRL.all = 0 x00000000;ECa

11、naMboxes.MBOX12.MSGCTRL.all = 0 x00000000;ECanaMboxes.MBOX13.MSGCTRL.all = 0 x00000000;ECanaMboxes.MBOX14.MSGCTRL.all = 0 x00000000;ECanaMboxes.MBOX15.MSGCTRL.all = 0 x00000000;ECanaMboxes.MBOX16.MSGCTRL.all = 0 x00000000;ECanaMboxes.MBOX17.MSGCTRL.all = 0 x00000000;ECanaMboxes.MBOX18.MSGCTRL.all =

12、0 x00000000;ECanaMboxes.MBOX19.MSGCTRL.all = 0 x00000000;ECanaMboxes.MBOX20.MSGCTRL.all = 0 x00000000;ECanaMboxes.MBOX21.MSGCTRL.all = 0 x00000000;ECanaMboxes.MBOX22.MSGCTRL.all = 0 x00000000;ECanaMboxes.MBOX23.MSGCTRL.all = 0 x00000000;ECanaMboxes.MBOX24.MSGCTRL.all = 0 x00000000;ECanaMboxes.MBOX25

13、.MSGCTRL.all = 0 x00000000;ECanaMboxes.MBOX26.MSGCTRL.all = 0 x00000000;ECanaMboxes.MBOX27.MSGCTRL.all = 0 x00000000;ECanaMboxes.MBOX28.MSGCTRL.all = 0 x00000000;ECanaMboxes.MBOX29.MSGCTRL.all = 0 x00000000;ECanaMboxes.MBOX30.MSGCTRL.all = 0 x00000000;ECanaMboxes.MBOX31.MSGCTRL.all = 0 x00000000;/ T

14、An, RMPn, GIFn bits are all zero upon reset and are cleared again/ as a matter of precaution.ECanaRegs.CANTA.all =0 xFFFFFFFF; /* Clear all TAn bits */ECanaRegs.CANRMP.all =0 xFFFFFFFF; /* Clear all RMPn bits */ECanaRegs.CANGIF0.all = 0 xFFFFFFFF; /* Clear all interrupt flag bits */ECanaRegs.CANGIF1

15、.all = 0 xFFFFFFFF;/* Configure bit timing parameters for eCANA*/ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;ECanaShadow.CANMC.bit.CCR =1 ;/ Set CCR = 1ECanaRegs.CANMC.all =ECanaShadow.CANMC.all;ECanaShadow.CANBTC.bit.BRPREG = 4;ECanaShadow.CANES.all =ECanaRegs.CANES.all;ECanaShadow.CANBTC.bit.TSEG2

16、REG = 1;doECanaShadow.CANBTC.bit.TSEG1R EG = 6;#endifECanaShadow.CANES.all = ECanaRegs.CANES.all;while(ECanaShadow.CANES.bit.CCE != 1 );/ Wait for CCE bit to beECanaShadow.CANBTC.bit.SAM = 1;ECanaRegs.CANBTC.all =ECanaShadow.CANBTC.all;set.ECanaShadow.CANBTC.all = 0;#if (CPU_FRQ_150MHZ)/CPU_FRQ_150M

17、Hz is defined in DSP2833x_Examples.h/* The following block for all 150 MHz SYSCLKOUT (75 MHz CAN clock) - default. Bit rate = 1 MbpsSee Note at End of File */ECanaShadow.CANBTC.bit.BRPRE G = 4;ECanaShadow.CANBTC.bit.TSEG2R EG = 2;ECanaShadow.CANBTC.bit.TSEG1R EG = 10;#endif#if (CPU_FRQ_100MHZ)/ CPU_

18、FRQ_100MHz is defined in DSP2833x_Examples.h/* The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock). Bit rate = 1 MbpsSee Note at End of File */ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;ECanaShadow.CANMC.bit.CCR = 0 ;/ Set CCR = 0ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;ECanaSha

19、dow.CANES.all = ECanaRegs.CANES.all;doECanaShadow.CANES.all = ECanaRegs.CANES.all;while(ECanaShadow.CANES.bit.CCE != 0 );/ Wait for CCE bit to becleared./* Disable all Mailboxes */ECanaRegs.CANME.all = 0;/ Required before writing the MSGIDsECanbShadow.CANRIOC.bit.RXFUNC=1；EDIS;ECanbRegs.CANRIOC.all

20、=ECanbShadow.CANRIOC.all;#if (DSP28_ECANB)void InitECanb(void)/InitializeeCAN-B module/* Create a shadow register structure forthe CAN control registers. This isneeded, since only 32-bit access isallowed to these registers. 16-bit accessto these registers could potentially corrupt the register conte

21、nts or returnfalse data. This is especially true while writing to/reading from a bit(or group of bits) among bits 16 - 31 */* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;ECanbShadow.CANMC.bit.SCB = 1;ECanbRegs.CANMC.all = ECanbSh

22、adow.CANMC.all;/* Initialize all bits of Master Control Field to zero */ Some bits of MSGCTRL register come up in an unknown state. For proper operation,/ all bits (including reserved bits) of MSGCTRL must be initialized to zerostruct ECAN_REGS ECanbShadow;EALLOW;/ EALLOWenables access to protected

23、bits/* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/ECanbShadow.CANTIOC.all = ECanbRegs.CANTIOC.all;ECanbShadow.CANTIOC.bit.TXFUNC = 1;ECanbRegs.CANTIOC.all = ECanbShadow.CANTIOC.all;ECanbShadow.CANRIOC.all =ECanbRegs.CANRIOC.all;ECanbMboxes.MBOX0.MSGCTRL.all = 0 x00000000;ECanbM

24、boxes.MBOX1.MSGCTRL.all = 0 x00000000;ECanbMboxes.MBOX2.MSGCTRL.all = 0 x00000000;ECanbMboxes.MBOX3.MSGCTRL.all = 0 x00000000;ECanbMboxes.MBOX4.MSGCTRL.all = 0 x00000000;ECanbMboxes.MBOX5.MSGCTRL.all = 0 x00000000;ECanbMboxes.MBOX6.MSGCTRL.all = 0 x00000000;ECanbMboxes.MBOX7.MSGCTRL.all = 0 x0000000

25、0;ECanbMboxes.MBOX8.MSGCTRL.all = 0 x00000000;ECanbMboxes.MBOX9.MSGCTRL.all = 0 x00000000;ECanbMboxes.MBOX10.MSGCTRL.all = 0 x00000000;ECanbMboxes.MBOX11.MSGCTRL.all = 0 x00000000;ECanbMboxes.MBOX12.MSGCTRL.all = 0 x00000000;ECanbMboxes.MBOX13.MSGCTRL.all = 0 x00000000;ECanbMboxes.MBOX14.MSGCTRL.all

26、 = 0 x00000000;ECanbMboxes.MBOX15.MSGCTRL.all = 0 x00000000;ECanbMboxes.MBOX16.MSGCTRL.all = 0 x00000000;ECanbMboxes.MBOX17.MSGCTRL.all = 0 x00000000;ECanbMboxes.MBOX18.MSGCTRL.all = 0 x00000000;ECanbMboxes.MBOX19.MSGCTRL.all = 0 x00000000;ECanbMboxes.MBOX20.MSGCTRL.all = 0 x00000000;ECanbMboxes.MBO

27、X21.MSGCTRL.all = 0 x00000000;ECanbMboxes.MBOX22.MSGCTRL.all = 0 x00000000;ECanbMboxes.MBOX23.MSGCTRL.all = 0 x00000000;ECanbMboxes.MBOX24.MSGCTRL.all = 0 x00000000;ECanbMboxes.MBOX25.MSGCTRL.all = 0 x00000000;ECanbMboxes.MBOX26.MSGCTRL.all = 0 x00000000;ECanbMboxes.MBOX27.MSGCTRL.all = 0 x00000000;

28、ECanbMboxes.MBOX28.MSGCTRL.all = 0 x00000000;ECanbMboxes.MBOX29.MSGCTRL.all = 0 x00000000;ECanbMboxes.MBOX30.MSGCTRL.all = 0 x00000000;ECanbMboxes.MBOX31.MSGCTRL.all = 0 x00000000;/ TAn, RMPn, GIFn bits are all zero upon reset and are cleared again/ as a matter of precaution.ECanbRegs.CANTA.all =0 x

29、FFFFFFFF; /* Clear all TAn bits */ECanbRegs.CANRMP.all =0 xFFFFFFFF; /* Clear all RMPn bits */ECanbRegs.CANGIF0.all = 0 xFFFFFFFF; /* Clear all interrupt flag bits */ECanbRegs.CANGIF1.all = 0 xFFFFFFFF;/* Configure bit timing parameters for eCANB*/ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;ECanbSha

30、dow.CANMC.bit.CCR =1 ;/ Set CCR = 1ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;ECanbShadow.CANES.all = ECanbRegs.CANES.all;doECanbShadow.CANES.all = ECanbRegs.CANES.all;while(ECanbShadow.CANES.bit.CCE != 1 );/ Wait for CCE bit to becleared.ECanbShadow.CANBTC.bit.BRPREG = 4;ECanbShadow.CANBTC.bit.TSE

31、G2REG = 1;ECanbShadow.CANBTC.bit.TSEG1R EG = 6;#endifECanbShadow.CANBTC.bit.SAM = 1;ECanbRegs.CANBTC.all =ECanbShadow.CANBTC.all;ECanbShadow.CANBTC.all = 0;#if (CPU_FRQ_150MHZ)/CPU_FRQ_150MHz is defined in DSP2833x_Examples.h/* The following block for all 150 MHz SYSCLKOUT (75 MHz CAN clock)- defaul

32、t. Bit rate = 1 MbpsSee Note at end of file */ECanbShadow.CANBTC.bit.BRPRE G = 4;ECanbShadow.CANBTC.bit.TSEG2R EG = 2;ECanbShadow.CANBTC.bit.TSEG1R EG = 10;#endif#if (CPU_FRQ_100MHZ)/ CPU_FRQ_100MHz is defined in DSP2833x_Examples.h/* The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clo

33、ck). Bit rate = 1 MbpsSee Note at end of file */ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;ECanbShadow.CANMC.bit.CCR = 0 ;/ Set CCR = 0ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;ECanbShadow.CANES.all = ECanbRegs.CANES.all;doECanbShadow.CANES.all = ECanbRegs.CANES.all;while(ECanbShadow.CANES.bit.CC

34、E != 0 );/ Wait for CCE bit to becleared./* Disable all Mailboxes */ECanbRegs.CANME.all = 0;/ Required before writing the MSGIDsEDIS;#endif if DSP28_ECANB/ Example: InitECanGpio:/ This function initializes GPIO pins to function as eCAN pins/ Each GPIO pin can be configured as a GPIO pin or up to 3 d

35、ifferent/ peripheral functional pins. By default all pins come up as GPIO/ inputs after reset./ Caution:/ Only one GPIO pin should be enabled for CANTXA/B operation./ Only one GPIO pin shoudl be enabled for CANRXA/B operation./ Comment out other unwanted lines.#endif / if DSP28_ECANBvoid InitECanaGp

36、io(void)EALLOW;/* Enable internal pull-up for the selected CAN pins */ Pull-ups can be enabled or disabled by the user./ This will enable the pullups for the specified pins./ Comment out other unwanted lines.GpioCtrlRegs.GPAPUD.bit.GPIO3 0 = 0;/ Enable pull-up for GPIO30(CANRXA)GpioCtrlRegs.GPAPUD.b

37、it.GPIO18 =0;/ Enable pull-up for GPIO18(CANRXA)/GpioCtrlRegs.GPAPUD.bit.GPIO3 1 = 0;/ Enable pull-up for GPIO31(CANTXA)GpioCtrlRegs.GPAPUD.bit.GPIO19 =0;/ Enable pull-up for GPIO19void InitECanGpio(void)InitECanaGpio();InitECanbGpio();#if (DSP28_ECANB)InitECanbGpio();/* Set qualification for select

38、ed CAN pins to asynch only */ Inputs are synchronized to SYSCLKOUT by default./ This will select asynch (no qualification) for the selected pins.(CANTXA)GpioCtrlRegs.GPAQSEL2.bit.GPIO30=3; / Asynch qual for GPIO30 (CANRXA)GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3;/ Asynch qual for GPIO18 (CANRXA)/ This w

39、ill enable the pullups for the specified pins./ Comment out other unwanted lines./* Configure eCAN-A pins using GPIO regs*/ This specifies which of the possible GPIO pins will be eCAN functional pins.GpioCtrlRegs.GPAMUX2.bit.GPIO 30 = 1;/ Configure GPIO30 forCANRXA operationGpioCtrlRegs.GPAMUX2.bit.

40、GPIO18 = 3;/ Configure GPIO18 for CANRXA operation/GpioCtrlRegs.GPAMUX2.bit.GPIO 31 = 1;/ Configure GPIO31 forCANTXA operationGpioCtrlRegs.GPAMUX2.bit.GPIO19 = 3;/ Configure GPIO19 for CANTXA operation/GpioCtrlRegs.GPAPUD.bit.GPIO8=0;/ Enable pull-up for GPIO8(CANTXB)/ GpioCtrlRegs.GPAPUD.bit.GPIO12

41、 = 0;/ Enable pull-up for GPIO12 (CANTXB)GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0;/ Enable pull-up for GPIO16 (CANTXB)/ GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0;/ Enable pull-up for GPIO20 (CANTXB)/GpioCtrlRegs.GPAPUD.bit.GPIO1 0 = 0; / Enable pull-up for GPIO10 (CANRXB)/ GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; / E

42、nable pull-up for GPIO13 (CANRXB)GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0;/ Enable pull-up for GPIO17 (CANRXB)/ GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; / Enable pull-up for GPIO21 (CANRXB)EDIS;#if (DSP28_ECANB)void InitECanbGpio(void)EALLOW;/* Enable internal pull-up for the selected CAN pins */ Pull-ups can

43、be enabled or disabled by the user./* Set qualification for selected CAN pins to asynch only */ Inputs are synchronized to SYSCLKOUT by default./ This will select asynch (no qualification) for the selected pins./ Comment out other unwanted lines./ GpioCtrlRegs.GPAQSEL1.bit.GPIO10=3; / Asynch qual fo

44、r GPIO10 (CANRXB)/ GpioCtrlRegs.GPAQSEL1.bit.GPIO13 =3; / Asynch qual for GPIO13 (CANRXB)GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3;/ Asynch qual for GPIO17 (CANRXB)/ GpioCtrlRegs.GPAQSEL2.bit.GPIO21 =3; Asynch qual for GPIO21 (CANRXB)/* Configure eCAN-B pins using GPIO regs*/ This specifies which of the

45、possible GPIO pins will be eCAN functional pins.GpioCtrlRegs.GPAMUX1.bit.GPIO 8 = 2; / Configure GPIO8 for CANTXB operation/ GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 2; / Configure GPIO12 for CANTXB operationGpioCtrlRegs.GPAMUX2.bit.GPIO16 = 2;/ Configure GPIO16 for CANTXB operation/ GpioCtrlRegs.GPAMUX2.b

46、it.GPIO20 = 3; / Configure GPIO20 for CANTXB operationNote: Bit timing parameters must be chosen based on the network parameters suchas the sampling point desired and the propagation delay of the network.The propagation delay is a function of length of the cable, delay introduced bythe transceivers

47、and opto/galvanic- isolators (if any).The parameters used in this file must be changed taking into account the abovementioned factors in order to arrive at the bit-timing parameters suitablefor a network./GpioCtrlRegs.GPAMUX1.bit.GPIO 10 = 2; / Configure GPIO10 for CANRXB operation/ GpioCtrlRegs.GPA

48、MUX1.bit.GPIO13 = 2; / Configure GPIO13 for CANRXB operationGpioCtrlRegs.GPAMUX2.bit.GPIO17 = 2; / Configure GPIO17 for CANRXB operation/ GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 3; / Configure GPIO21 for CANRXB operationEDIS;#endif / if DSP28_ECANB/*/Example 2833xEcanA to B Xmit:/ TI File $Revision: /main

49、/9 $/ Checkin $Date: April 21,2008 15:41:13 $/#/ Filename:Example_28xEcan_A_to_B_Xmit.c/ Description: eCAN-A To eCAN-B TXLOOP-Transmit loop/ ASSUMPTIONS:/ This program requires the DSP2833x header files./ Both CAN ports of the 2833x DSP need to be connected/ to each other (via CAN transceivers)/ eCA

50、NA is on GPIO31 (CANTXA) and/GPIO30 (CANRXA)/ eCANB is on GPIO8 (CANTXB) and/GPIO10 (CANRXB)/ As supplied, this project is configured for boot to SARAM/ operation. The 2833x Boot Mode table is shown below./ For information on configuring the boot mode of an eZdsp,/ please refer to the documentation

51、included with the eZdsp,/$Boot_Table:/GPIO87 GPIO86GPIO85 GPIO84/XA15XA14XA13XA12/PUPUPUPU/1111Jump to Flash/1110SCI-A boot/1101SPI-A boot/1100I2C-A boot/1011eCAN-A boot/1010McBSP-A boot/x161001Jump to XINTF/10 x32/01/01I/O boot/01boot00 Jump to XINTF11Jump to OTP10Parallel GPIO01ParallelXINTF/0100

52、Jump toSARAM - boot to SARAM/00check boot mode/00bypass ADC cal/00bypass ADC cal/00bypass ADC cal/11 Branch to10 Boot to flash,01 Boot to SARAM,00 Boot to SCI-A,Boot_Table_End$/ DESCRIPTION:/ This example TRANSMITS data to another CAN module using MAILBOX5/ This program could either loop forever or

53、transmit n # of times,/ where n is the TXCOUNT value./ This example can be used to check CAN-A and CAN-B. Since CAN-B is/ initialized in DSP2833x_ECan.c, it will acknowledge all frames/ transmitted by the node on which this code runs. Both CAN ports of/ the 2833x DSP need to be connected to each oth

54、er (via CAN transceivers)/#/ Original Author: HJ/ $TI Release: DSP2833x/DSP2823x C/C+ Header Files V1.31 $/ $Release Date: August 4, 2009 $/#include DSP28x_Project.h / Device Headerfile and Examples Include File#define TXCOUNT 100 / Transmission will take place (TXCOUNT) times./ Globals for this exa

55、mplelong i;long loopcount = 0;extern void test(void);void CanB_Config(void);void main()/* Create a shadow register structure for the CAN control registers. This isneeded, since, only 32-bit access is allowed to these registers. 16-bit accessto these registers could potentially corrupt the register c

56、ontents. This isespecially true while writing to a bit (or group of bits) among bits 16 - 31 */test();struct ECAN_REGS ECanaShadow;/ Step 1. Initialize System Control:/ PLL, WatchDog, enable Peripheral Clocks/ This example function is found in the DSP2833x_SysCtrl.c file.InitSysCtrl();/ Step 2. Init

57、alize GPIO:/ This example function is found in the DSP2833x_Gpio.c file and/ illustrates how to set the GPIO to its default state./ InitGpio(); / Skipped 1for this example/ Just initalize eCAN pins for this example/ This function is in DSP2833x_ECan.cInitECanGpio();/ Step 3. Clear all interrupts and

58、 initialize PIE vector table:/ Disable CPU interruptsDINT;/ Initialize the PIE control registers to their default state./ The default state is all PIE interrupts disabled and flags/ are cleared./ This function is found in theDSP2833x_PieCtrl.c file.InitPieCtrl();IER = 0 x0000;IFR = 0 x0000;/ Initial

59、ize the PIE vector table with pointers to the shell Interrupt/ Service Routines (ISR)./ This will populate the entire table, even if the interrupt/ is not used in this example. This is useful for debug purposes./ The shell ISR routines are found in DSP2833x_DefaultIsr.c./ This function is found inDS

60、P2833x_PieVect.c.InitPieVectTable();/ Interrupts that are used in this example are re-mapped to/ ISR functions found within this file./ No interrupts used in this example./ Step 4. Initialize all the Device Peripherals:/ This function is found inDSP2833x_InitPeripherals.c/ InitPeripherals(); / Not r