嵌入式软件系统设计：10_Processor_hazard

1、Embedded System Designlecture 10-Processor(2)_hazard_board_verificatioonJun WANG1ContentsLearnt from last test exampleHazardStructureDataArithmeticSoftware solutionNOPHardware solutionData forwardingLOADSoftware solutionNOPHardware solutionStallControlBoard verification2Example of test pattern (text

2、ure simulation)LOAD gr1, gr0, 0LOAD gr2, gr0, 1NOPNOPNOPADD gr3, gr1, gr2NOPNOPNOPSTORE gr3, gr0, 2HALT3Simulation results (texture)Please test by yourself, and analyse itLOAD gr1, gr0, 0LOAD gr2, gr0, 1NOPNOPNOPADD gr3, gr1, gr2NOPNOPNOPSTORE gr3, gr0, 2HALT4HazardsSituations that prevent starting

3、the next instruction in the next cycleStructure hazardsA required resource is busyData hazardNeed to wait for previous instruction to complete its data read/writeControl hazardDeciding on control action depends on previous instruction5Structure HazardsConflict for use of a resourceIn X86（by intel） p

4、ipeline with a single memoryLoad/store requires data accessInstruction fetch would have to stall for that cycleWould cause a pipeline “bubble”So called von Neumann structureIn ARM/MIPS pipelineseparate instruction/data cachesSo called Harvard structure6Data HazardsAn instruction depends on completio

5、n of data access by a previous instruction7SolutionSoftwareInsert 3 NOPsHardwareData forwardFor arithmetic opData forward & StallFor LOAD8Data forwardingData forwarding happens in ID stage, always check id_ir to decide reg_A/B9Cant always forwarding“LOAD” can still cause hazardsince data was accesse

6、d from data memoryafter reg_C10SolutionSoftwareInsert 3 NOPsHardwareJoint usage of Data forwarding & StallData forwarding to solve 2nd and 3rd NOPsStall to sove 1st NOP11StallStall the pipeline by keeping an instruction in the same stageStall happens in IF stage, always compare id_ir with i_datain t

7、o decide pc and id_ir 12Control HazardWhen CPU decide to branch, other instructions are still in pipeline!During the time from branch instruction fetch to branch address generate (from IF to ID to EX to IF, 3 stages), the 3 instructions followed by branch are in pipeline.The computing results by the

8、m are uselessShould be flushed or will impact the following instructions computing 13SolutionSoftwareInsert 3 NOPsInsert independent operationsHardwareFlushingI am not going to more detail1415SummaryHazardStructureDataArithmeticSoftware solutionNOPHardware solutionData forwardingLOADSoftware solutio

9、nNOPHardware solutionStallControl (optional)Software solutionNOPIndependent operationHardware solutionFlushing15Use hazard to understand test patternControl Hazard is an optional topic, you do not need to implement hazard by verilogbut your implementation is highly recommended and scoredSubmit by 8t

10、h JanData hazard (including forwarding and stall) you MUST finish by 8th Jan, and submitBoth design and testUnderstand how to write test pattern for your verilogAlways insert 3 NOPsBut please be more smart16Memory implementationWrite verilog by yourselfUse Core_Gernerate to generate IPGet the verilo

11、g built inIf you can use board evaluation in your final project, big plus can give you!17Concept behindSystem on ChipSOCFrom SOB to SOCSystem on board to system on chipSOCProcessorARM/DSP/MIPS/X86Program with C/C+MemoryFPGA/ASICYour own verilogTherefore, software and hardware division is a problemNe

12、w design methodologySW/HW Co-designKey of embedded system designLets move to next semesterSOPC: (P: programmable)Newly FPGA, the state-of-art all programmable device, can cover everything with low cost solution, and acceptable performance, TryASIC for further1819Example: Digital camera hardware block diagramEmbedded System DesignProcessorCoreMemoryInterfacePIOInterfaceUSBControllerADCDSPImageCodecSDRAMSRAMFlashSPILCDControllerRTCSoC19ReviewEvaluation10% attendance30% Lab50% Project10% ExamExamOpen bookReview20ReviewWhat we have learntHow a given speci