成功解决fpga设计时序问题的三大要点

1、 ! 21EDA #$ FPGA )*+,-./0123456789:;)?ABCDEFGH)*+IJKLDMNOPQ/0)RSTUVM?WXY 200 Z4?_abcdefghC)ij?4klmno&pq_)rsKWtFuvw?xy=)z|ma ?!x#) ?4MNRS$%m&(0)VMKg)*+.v, A-./0*+)12?3456789rs?:;)?ABC#a KFPGA QDEWFGHIFJ)KL?MNOPG I/O QR/0)STURS(DDR)mVWXY(PLL)Z_MKtFW FPGA 12_)-KLaBbJ)/0cd?efG6ghijk*+?lm TimingDesigner

2、nD)opLq?Wxr)a_BbxVMsGq)notuKvwx=yzD DDR OPQ/0*+_|=)BRS$%)a KDDR/QDR OPQ/0)*+rsDDR !RS.v(QDR)OP*34Bbm/#$!gQDuv)%,&RS? t()RSW)*+m+TUK;+?=,-m_./018?4MN./),RS2&K ! 21EDA #$%t?cd)VMm3AKLDBCtE6?DEFGH QDR II SRAM%,&/0)*+=IIJKKW,&OPQ&pKM QDR SRAM _?RSz,&)?94OPQRS)XL|= MN 90 OKtPXLMNT WGRRS(0_S18?tz QDR JEVM

3、 RS$%)Ey=*+p6(T3 2)KMU=VW_S?EF34TY:V FPGA) PLL Z_XQ)Y56ZK3 2(_S:)/RS2&K5HRSY5634JE_S:4_PaOWbmcdef)*+12?3Lg:RStkPEF12?hgi.?jkD/lOPQ)|mNOa)=KW0n?:g.obQD?_S:)*+O0|mmNOa?!C9q) ! 21EDA #$%d7 4|GRRS(0K18z FPGA ;24obK=M )3?EF|=451256)6)Ym.7+oYK8J?EF9j TimingDesigner nDTYOPQRS:L QDR SRAM 3E3:(3 ! 21EDA #$%3

4、M OPQ,GRRS(0_)mRS56a)2&K;)zM tP2&K3 4(QDR OPQGHa3 MT54W1MH18JKe3 4 34ICW FPGA )?PCB TAY,(CQ_FPGA)mRS(Q_FPGA)56A)2&KW TimingDesigner nD)BCD/$R:_9jQo)WE34FG05H PCB V)YBY3:X2)56)12KEW?EF34W./) FPGA ;R) FPGA %jKLMB_6Nm6)KaKLL2O56Bba5PKTimingDesigner nDBbop)a$43MQEm+RWEU?e_wwSwD NOTUp )KLVzKKM?WE FPGA KL

5、6)_?:WwcBCwS(0)V z=_?34TYa3_Lp 56+RYXYKtZ?EF34dtFVzTYEwvwDGF)PAe&p_?EFaQ_K34/dR3_ FPGA )KL:g-.OPQ/0*+?RSOPQb-W FPGA ;6)ghLURS56?1;WRS()iEobOWRSghYKFPGA ) PLL Abj_./)?=TQGjP3 L)eUkl,-0OQ)ghK3UTYp )m9?9 PLL )p6GHX L?Xn?Xu1J?onzpqK)*+rsKL34PcdK1;?mRSgh)6)mYX|=M ?4JE./)XLK ! 21EDA #$%GRRS(0)Y3(DlyDVW)K(

6、$43 3)DlyDVW = (DVWdata - DVWdev) / 22sI/O 0OQRS|mAm DlyDVW 3?4M DX:*+)GRRS(0(DlyRelSU)KDlyRelSU = DlyDVW + IOEsu3sxZ?eX:|mA(k5 2 &H)R3)?h*56,-0OQ)GRR S(0(ea3QE)6A)./KClk_offset = DlyRelSU - EdgeOffset%j:&?EF34M FPGA e&p_ PLL )XLE?=7_E&)6Nm6)K4.89Ul:;Y4AVW PLL?M?)|mmNO dzh3L)K:gtF !?eW FPGA ;rsK3 6(WVWm|mBNO Z?5HRSbc)a3:Kvw# ! 21EDA #$%) FPGA QD1KPG