电子表单元电路汇编

1、第四章 数字(shz)系统设计数字(shz)电子时钟单元电路分频器；延时电路；微分电路；同步计数器；消抖电路共二十页分频器用途(yngt)：计数器即是简易分频器D0D1D2Clk输出(shch)频率公式：共二十页延迟(ynch)电路用途(yngt)：产生n个CP的相位延时CPDINDCPQ#QDCPQ#QQ1Q0共二十页延迟(ynch)与微分电路时序(sh x)图：CPDINQ0Q1共二十页- *LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.AL

2、L;-*ENTITY dly1 isPORT( CP,DIN: INSTD_LOGIC; Q1: OUTSTD_LOGIC);END dly1;-*ARCHITECTURE a OF dly1 ISSIGNAL Q0 STD_LOGIC;BEGINPROCESS (CP)BEGINIF CPevent AND CP=1 THEN Q0 = Din;Q1 = Q0;END IF;END PROCESS;END a;共二十页微分电路用途：将宽脉冲转换为一个(y )CP周期的脉冲CPDINDCPQ#QDCPQ#QDOUTQ0Q1共二十页延迟(ynch)与微分电路时序(sh x)图：CPDINQ0Q1

3、DOUT共二十页LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;-*ENTITY dly1 isPORT( CP,DIN: INSTD_LOGIC; DOUT: OUTSTD_LOGIC);END dly1;-*ARCHITECTURE a OF dly1 ISSIGNAL Q0,Q1 STD_LOGIC;BEGINPROCESS (CP)BEGINIF CPevent AND CP=1 THEN Q0 = Din;Q1 = Q0;END

4、IF;END PROCESS;DOUT = Q1 AND NOT Q0;END a;共二十页同步(tngb)计数器电路用途：消除(xioch)竞争冒险；消除(xioch)延时误差CPINDCPQ#QDCPQ#QECCLKQ共二十页Free_Counter : Block Signal Q: STD_LOGIC_VECTOR(24 DOWNTO 0);Signal DLY : STD_LOGIC;BeginPROCESS (CP)BeginIF CPEvent AND CP=1 thenDLY = Q(21);Q = Q+1;END IF;END PROCESS;SEC = Q(21) AND

5、NOT DLY;-about 1Hz End Block Free_Counter;共二十页- 60进制计数器-*LIBRARY IEEE;USE IEEE.STD_LOGIC_UNSIGNED.ALL;-*ENTITY COUNTER60 ISPORT(CP : IN STD_LOGIC;BIN: OUT STD_LOGIC_VECTOR (5 DOWNTO 0);S : IN STD_LOGIC;CLR : IN STD_LOGIC;EC : IN STD_LOGIC;CY60 : OUT STD_LOGIC);END COUNTER60;共二十页- 子文件(wnjin)定义代码ARCHI

6、TECTURE a OF COUNTER60 ISSIGNAL Q : STD_LOGIC_VECTOR (5 DOWNTO 0) ;SIGNAL RST, DLY : STD_LOGIC;BEGINPROCESS (CP,RST)BEGINIF RST = 1 THENQ = 000000;ELSIF CPevent AND CP = 1 THENDLY = Q(5);IF EC = 1 THENQ = Q+1;END IF; END IF;END PROCESS;CY60 = NOT Q(5) AND DLY;RST = 1 WHEN Q=60 OR CLR=1 ELSE 0;BIN =

7、Q WHEN S = 1 ELSE 000000;END a;共二十页同步(tngb)计数器电路（有进位）CPDINECCLKQ微分器微分器CY共二十页消抖电路(dinl)用途(yngt)：消除竞争冒险；消除抖动共二十页消抖电路(dinl)CPINDCPQ#QDCPQ#QSRQ#QDOUT共二十页-*LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;-*ENTITY Debunce isPORT( test_S: OUT STD_LOGIC;

8、 CP: IN STD_LOGIC; Key : IN STD_LOGIC; DLY_OUT : OUT STD_LOGIC; DIF_OUT: OUT STD_LOGIC);END Debunce;-*ARCHITECTURE a OF Debunce IS共二十页SIGNAL SAMPLE, DLY, NDLY, DIFF: STD_LOGIC;- Binary BEGINtest_S = SAMPLE; Free_Counter : Block- 计数器 & 产生扫描(somio)信号 Signal Q: STD_LOGIC_VECTOR(14 DOWNTO 0);Signal D0 :

9、 STD_LOGIC;BeginPROCESS (CP)- 计数器计数 BeginIF CPEvent AND CP=1 thenD0 = Q(4);Q = Q+1;END IF;END PROCESS;SAMPLE = Q(4) AND NOT D0;-产生125HZ脉冲? -SAMPLE = Q(1) AND NOT D0;END Block Free_Counter;共二十页Debunce : Block- DebounceSIGNAL D0, D1, S, R : STD_LOGIC; BeginProcess (CP)BeginIF CPEVENT AND CP=1 THENIF S

10、AMPLE = 1 THEND1 = D0; D0 = KEY;- Two Stage DelayS = D0 AND D1;- Generate S、RR = NOT D0 AND NOT D1;END IF;END IF;End Process;DLY = R NOR NDLY;- Debounce O/PNDLY =S NOR DLY;DLY_OUT = DLY;End Block Debunce;共二十页Differential : Block-DifferentialSignal D1,D0 : STD_LOGIC;BEGINProcess (CP)BeginIF CPEVENT A

11、ND CP=1 THEND1 = D0; D0 = DLY;- Two State DelayEND IF;End Process;DIFF = D0 AND NOT D1;- DifferentialEND Block Differential;DIF_OUT = DIFF;- Differential O/PEND a;共二十页内容摘要第四章 数字系统设计。SIGNAL Q0 STD_LOGIC。Q1 = Q0。END a。用途：将宽脉冲转换(zhunhun)为一个CP周期的脉冲。SIGNAL Q0,Q1 STD_LOGIC。ENTITY COUNTER60 IS。DLY = Q(5)。test_S = S