16位模型机的设计(1)

1、16位CPU的设计要求：此模型机的功能是将存储区的数据块复制到另一个存储区。汇编代码如下：STARTLOADI R1, 0010H ;源操作数地址送 R1LOADI R2 0030H ;目的操作数地址送R2LOADI RG 002FH ;结束地址送 R6NEXT LOAD R3 R1;取数STORE R2, R3 ;存数BRANCHGTI START ;如果 R1R6 则车专向 STARTINC R1;修改源地址INC R2;修改目的地址BRANCHI NEXT ;转向 NEXT1 . 16位CPU勺组成结构2 .指令系统的设计一、 指令格式1）单字指令格式操作弱源操作数目的操作数Opcode

2、SRCDST15141312115432102）双字指令格式操作码源操作数目的操作数OpcodeSRCBST1514 I3 121154321016位操作数15M131211109876543210指令操作码操作 码指令功能00001LOAD装载数据到寄存器00010STORE将寄存器的数据存入到存储器00100LOADI将立即数装入到寄存器00101BRANCHI无条件转移到由立即数指定的地址00110BRANCHGTIi如果源寄存器内容大于目的寄存器的内容，则转移到由立即数指定的地址00111INC寄存器内容加1指令依据以上设计的指令系统，则完成数据块复制的程序如下:址地码机器指令功能说明

3、0002001LOADIR1 ,源操作数地址送R10H000H00100010H1HH0002002LOADIR2 ,目的操作数地址送 R22H000H00300030H3HH0002006LOADIR6 ,结束地址送R64H000H002F002FH5HH0006H080BHLOAD R3 R1取数0007H101AHSTORE R2, R3存数0008H0009H300EH0000HBRANCHGTI0000如果R1大于R6,则转向地址 0000000AH3801HINC R1修改源地址000BH3802HINC R2修改目的地址000CH000DH2800H0006HBRANCHI 00

4、06H转向00006H,实现循环3. VHD殴计一、程序包：说明运算器的功能、移动寄存器的操作、比较器的比较类型和用于CPU空制的状态类型。library ieee;use cpu_lib issubtype t_shift is unsigned (3 downto 0);constant shftpass :unsigned(3 downto 0):=0000;constant sftl :unsigned(3 downto 0):=0001;constant sftr:unsigned(3 downto 0):=0010;constant rotl :unsigned(3 downto

5、0):=0011;constant rotr :unsigned(3 downto 0):=0100;subtype t_alu is unsigned(3 downto 0);constant alupass :unsigned(3 downto 0):=0000;constant andOp :unsigned(3 downto 0):=0001;constant orOp:unsigned(3 downto 0):=0010;constant notOp :unsigned(3 downto 0):=0011;constant xorOp :unsigned(3 downto 0):=0

6、100;constant plus :unsigned(3 downto 0):=0101;constant alusub :unsigned(3 downto 0):=0110;constant inc :unsigned(3 downto 0):=0111;constant dec :unsigned(3 downto 0):=1000;constant zero:unsigned(3 downto 0):=1001;subtype t_comp is unsigned 2 downto 0);constant eq :unsigned(2 downto 0):=000;constant

7、neq :unsigned(2 downto 0):=001;constant gt:unsigned(2 downto 0):=010;constant gte :unsigned(2 downto 0):=011;constant lt :unsigned(2 downto 0):=100;constant lte :unsigned(2 downto 0):=101;subtype t_reg is std_logic_vector(2 downto 0);typestateis(reset1,reset2,reset3,reset4,reset5,reset6,execute,nop,

8、load,store,move,10ad2,load3,load4,store2,store3,store4,move2,move3,move4,incPc,incPc2,incPc3,incPc4,incPc5,incPc6,loadPc,loadPc2,loadPc3,loadPc4,bgtI2,bgtI3,bgtI4,bgtI5,bgtI6,bgtI7,bgtI8,bgtI9,bgtI10,braI2,braI3,braI4,braI5,braI6,10adi2,loadI3,loadI4,loadI5,loadI6,inc2,inc3,inc4);subtype bit16 is st

9、d_1ogic_vector(15 downto 0); end cpu_lib;、基本部件的设计1）运算器的设计 功能Sei输入操作说明0000C=A通过PASS0001C=A ANDB与0010C=A OR B或0011C=NOTA辛0100C=A XOR B异或0101C=A + B加法JoinC=A - B减法0111C=A +1加一1000C=A-1减11001c=o清。library ieee;use alu isport(a,b:in bit16;sel:in t_alu;c:out bit16);end alu;architecture rt1 of alu isbeginpr

10、ocess(a,b,sel)begincase sel iswhen alupass= c c c c c c c c c c c=b t compout=l100It （小于）若compout=l101依小于等于）若 si if a=b then compout =1 after 1ns;else compout if a/=b then compout =1 after 1ns;else compout if ab then compout =1 after 1ns;else compout if a=b then compout =1 after 1ns;else compout if

11、ab then compout =1 after 1ns;else compout if a=b then compout =1 after 1ns;else compout compout y y y y y y=0000000000000000 after 1 ns;end case;end process;end rt1;4）寄存器a15. 0q15.O：elkiins 14library ieee;use reg isport(a:in bit16;clk:in std_logic;q:out bit16);end reg;architecture rt1 of reg isbegin

12、processbeginwait until clkevent and clk=1;q=a after 1ns;end process;end rt1;5)寄存器组library ieee;use regarray isport(data:in bit16;sel:in t_reg;en,clk:in std_logic;q:out bit16);end regarray;architecture rt1 of regarray istype t_ram is array (0 to 7) of bit16;signal temp_data:bit16;beginprocess(clk,sel

13、)variable ramdata:t_ram;beginif clkevent and clk=1 then ramdata(conv_integer(sel):=data;end if;temp_data=ramdata(conv_integer(sel) after 1 ns;end process;process(en,temp_data)beginif en=1 then q=temp_data after 1 ns;else q=ZZZZZZZZZZZZZZZZ after 1 ns;end if;end process;end rt1;6)三态寄存器# I n ii rein i

14、 m ti iv I insT8； elkIin11叫5一 口 q15. 0 T;trjneg 一library ieee;use trireg isport(a:in bit16;en,clk:in std_logic;q:out bit16);end trireg;architecture rt1 of trireg issignal val:bit16;beginprocessbeginwait until clkevent and clk=1;val=a;end process;process(en,val)beginif en=1 then q=val after 1 ns;elsi

15、f en=0 then q=ZZZZZZZZZZZZZZZZ” after 1 ns;else q=XXXXXXXXXXXXXXXX after 1 ns;end if;end process;end rt1;7）控制器采用状态机实现,I -1- 一pa-3- ，.W/44HGontroH11progCnyWiI ock -firogCfiyRd伯鼎 -*hsnPeq；15.01-8mMU -I1UtRFQ7; 1m成白犯dlshift Sc (2.曰1吟训3 ,0,QcipRplRilopRe5WTinstrWregs&ip. 0 - 间母；怜酬IfiHAtLl 1iristJ一，“一一一一

16、library IEEE; use control isport( clock,reset,compout:in std_logic; instrReg:in bit16;progCntrWr,progCntrRd,addrRegWr,outRegWr,outRegRd:out std_logic; shiftSel:out t_shift; aluSel:out t_alu; compSel:out t_comp;opRegRd,opRegWr,instrWr,regRd,regWr,rw,vma:out std_logic; regSel:out t_reg );end control;a

17、rchitecture rtl of control issignal current_state, next_state : state;beginprocess( current_state, instrReg, compout)beginprogCntrWr = 0; progCntrRd = 0; addrRegWr = 0;outRegWr = 0;outRegRd = 0; shiftSel = shftpass; aluSel = alupass;compSel = eq;opRegRd = 0; opRegWr = 0; instrWr = 0; regSel = 000;re

18、gRd = 0; regWr = 0; rw = 0; vma aluSel=zero after 1 ns; shiftSel=shftpass;next_state aluSel=zero; shiftSel=shftpass; outRegWr=1; next_state outRegRd=1; next_state outRegRd=1;progCntrWr=1;addrRegWr=1;next_state vma=1; rw = 0; next_state vma=1; rw=0;instrWr=1; next_state case instrReg(15 downto 11) is

19、when 00000 = next_state regSel=instrReg(5 downto 3); regRd=1;next_state regSel=instrReg(2 downto 0); regRd=1;next_state regSel=instrReg(5 downtoaluSel=alupass;shiftSel=shftpass; next_stateshiftsel=shftpass;next_stateshiftsel=shftpass;next_stateprogcntrRd=1;progcntrRd=1;regSel=instrReg(53);regRd=1;al

20、usel=inc;alusel=inc;downto 3);regRd=1;next_state regSel=instrReg(2 downto 0); regRd=1; alusel=inc; shiftsel=shftpass; next_statenext_state regSel = instrReg(5 downto 3); regRd = 1;addrregWr = 1;next_state vma = 1; rw = 0; next_state vma = 1; rw = 0; regSel = instrReg(2 downto 0);regWr = 1;next_state

21、 regSel = instrReg(2 downto 0); regRd = 1;addrregWr = 1;next_state regSel = instrReg(5 downto 3); regRd = 1;next_state regSel = instrReg(5 downto 3); regRd = 1; rw = 1;next_state regSel = instrReg(5 downto 3); regRd = 1;aluSel =alupass;shiftsel = shftpass; outRegWr = 1; next_state outRegRd = 1; next

22、_state outRegRd = 1;regSel = instrReg(2 downto 0); regWr = 1;next_state progcntrRd = 1; alusel = inc; shiftsel = shftpass;outregWr=1;next_state outregRd = 1; next_state outregRd =1; progcntrWr=1;addrregWr=1;next_state vma = 1; rw = 0; next_state vma = 1; rw = 0;regSel = instrReg(2 downto 0);regWr =

23、1;next_state progcntrRd = 1; alusel = inc; shiftsel = shftpass;outregWr=1;next_state outregRd = 1; next_state outregRd=1;progcntrWr=1;addrregWr=1;next_state vma=1; rw=0; next_state vma = 1; rw = 0;progcntrWr = 1; next_state regSel = instrReg(5 downto 3); regRd = 1;opRegWr = 1;next_state opRegRd = 1;

24、 regSel = instrReg(2 downto 0);regRd = 1;compsel = gt; next_state opRegRd = 1 after 1 ns;regSel = instrReg(2 downto 0); regRd=1;compsel = gt;if compout = 1 then next_state = bgtI5;else next_state progcntrRd=1;alusel=inc;shiftSel=shftpass;next_state progcntrRd = 1; alusel = inc; shiftsel = shftpass;o

25、utregWr = 1; next_state outregRd = 1; next_state outregRd = 1;progcntrWr = 1; addrregWr =1; next_state vma = 1; rw = 0; next_state vma = 1; rw = 0; progcntrWr = 1; next_state regSel = instrReg(2 downto 0); regRd = 1; alusel = inc;shiftsel= shftpass; outregWr = 1; next_state outregRd = 1; next_state

26、outregRd = 1; regsel = instrReg(2 downto 0);regWr = 1;next_state progcntrRd = 1; next_state progcntrRd = 1; addrRegWr = 1; next_state vma = 1; rw = 0; next_state vma = 1; rw = 0; instrWr = 1; next_state progcntrRd=1;alusel=inc;shiftsel=shftpass;next_state progcntrRd = 1; alusel = inc; shiftsel = shf

27、tpass;outregWr = 1; next_state outregRd = 1; next_state outregRd=1; progcntrWr=1;addrregWr=1;next_state vma = 1; rw = 0; next_state vma = 1; rw = 0; instrWr = 1; next_state next_state = incPc;end case;end process;process(clock, reset)beginif reset = 1 then current_state = reset1 after 1 ns;elsif clockevent and clock = 1then current_state = next_state after 1 ns;end if;end process;end rtl;8) 存储器的设计LPM_RA陲制首先，定制初始化数据文件，建立MemoryInitialization File(.mif) 文件，