DSP傅里叶变化课程设计

1、实验五:快速傅立叶变换(FFT 算法实验一.实验目的1.掌握用窗函数法设计 FFT 快速傅里叶的原理和方法;2.熟悉 FFT 快速傅里叶特性;3.了解各种窗函数对快速傅里叶特性的影响。二.实验设备1. FFT 的原理和参数生成公式 公式(1 FFT 运算公式FFT 并不是一种新的变换, 它是离散傅立叶变换 (DFT 的一种快速算法。 由于我们在计 算 DFT 时一次复数乘法需用四次实数乘法和二次实数加法;一次复数加法则需二次实数加 法。每运算一个 X (k 需要 4N 次复数乘法及 2N+2(N-1 =2(2N-1次实数加法。所以整 个 DFT 运算总共需要 4N2 次实数乘法和 N*2(2N

2、-1=2N(2N-1次实数加法。 如此一来, 计算时 乘法次数和加法次数都是和 N2 成正比的,当 N 很大时,运算量是可观的,因而需要改进对 DFT 的算法减少运算速度。根据傅立叶变换的对称性和周期性, 我们可以将 DFT 运算中有些项合并。 我们先设序列长 度为 N=2L, L 为整数。将 N=2L 的序列 x(n(n=0,1, , N-1 ,按 N 的奇偶分成两组,也 就是说我们将一个 N 点的 DFT 分解成两个 N/2 点的 DFT , 他们又从新组合成一个如下式所表 达的 N 点 DFT :一般来说,输入被假定为连续的。当输入为纯粹的实数的时候,我们就可以利用左右对称 的 特性更好

3、的计算 DFT 。我们称这样的 RFFT 优化算法是包装算法:首先 2N 点实数的连续输入称为 “ 进包 ” 。其次 N 点的 FFT 被连续被运行。最后作为结果产生的 N 点的合成输出是 “ 打开 ” 成为最初的与 DFT 相符合的 2N 点输入。使用这战略,我们可以划分 FFT 的大小,它有一半花费在包装输入 O (N 的操作和打开 输出上。 这样的 RFFT 算法和一般的 FFT 算法同样迅速, 计算速度几乎都达到了两次 DFT 的 连续输入。下列一部分将描述更多的在 TMS320C54x 上算法和运行的细节。2. 程序流程图3.程序的自编函数及其功能rfft_task(;功能:在 C

4、语言中进行汇编调用。三.实验步骤1. 启动 Code Composer Studio2. 新建工程 FFT , 建立程序 BIT_REV.ASM、 FFT.ASM 、 INITRFFT.ASM 、 mcbsp54.h 、 POWER.ASM 、 rfft.asm 、 type.h 、 UNPACK.ASM 、 VECTORS.ASM 、 RFFT.CMD ,保存在工程目录为 F: FFT3.编译并下载程序4.加入断点,指定输入数据文件-打开工程中文件 rfft.asm-在第一个“ NOP ”语句上加探针(Probe Point-在第二个“ NOP ”语句上加软件断点(Break Point-在

5、最后一个“ NOP ”语句上加软件断点(Break Point5.打开观察窗口-选择菜单“ View ”、“ Graph ”、“ Time/Frequency ”进行如下设置: -在打开的窗口中单击鼠标右键,选择“ Clear Display”- 选择菜单 “ File ” 、 “ File I/O ” ; 单击 “ Add File ” 按钮, 选择 F: FFT1.DAT 文件,单击“打开”按钮;在“ Adress ”中输入 real_fft_in,在“ Length ”中输入 128; 在“ Warp Around”项前面加上选中符号;单击“ Add Probe Point”按钮。-单击

6、“ Probe Point”列表中的“ rfft.asm line 34”行;在“ Connect ”项选择“ FILE IN: F:.1.DAT”;单击“ Replace ”按钮;单击“确定”按钮。-单击“确定”按钮。-再次选择菜单“ View ”、“ Graph ”、“ Time/Frequency ”进行如下设置: -在打开的窗口中单击鼠标右键,选择“ Clear Display”6.按 F5 或选择 debug 菜单下的 run 来运行程序;当程序停止在软件断点时可在“ Input ” 窗口中观察到输入波形,为一正弦波。7.按 F5 或选择 debug 菜单下的 run 运行程序;当程

7、序停止在软件断点时可在“ Output ”窗 口中观察到输出波形。8.重复第 5 步,将输入波形文件改为 2.DAT ,选择“ Debug ”菜单“ Restart ”项,程序将 重新开始,再做第 6, 7 步。四.实验结果输入波形为一个低频率的正弦波,输出波形为此波形经 fft 运算后的显示。*步骤 7 实验现象图:-输入波形时域图和频域图: -输出波形图: *步骤 8 实验现象图:-输入波形时域图和频域图: 输出波形图: 通过观察频域和时域图,可以验证 fft 运算后的结果是否正确。五.问题与思考试选用不同点数的 fft 运算法则来运算。六.参考程序1. BIT_REV.ASM.mmreg

8、s.include "fft_size.inc".def bit_rev.ref _real_fft_input, fft_data.asg AR2,REORDERED_DATA.asg AR3,ORIGINAL_INPUT.asg AR7,DATA_PROC_BUF.textbit_rev:SSBX FRCT ; fractional mode is onSTM #_real_fft_input,ORIGINAL_INPUT ; AR3 -> 1st original input STM #fft_data,DATA_PROC_BUF ; AR7 -> dat

9、a processing buffer MVMM DATA_PROC_BUF,REORDERED_DATA ; AR2 -> 1st bit-reversed data STM #K_FFT_SIZE-1,BRCRPTBD bit_rev_end-1STM #K_FFT_SIZE,AR0 ; AR0 = 1/2 size of circ bufferMVDD *ORIGINAL_INPUT+,*REORDERED_DATA+MVDD *ORIGINAL_INPUT-,*REORDERED_DATA+MAR *ORIGINAL_INPUT+0Bbit_rev_end:RET ; retur

10、n to Real FFT main module .end2. FFT.ASM.mmregs.include "fft_size.inc".ref fft_data, d_grps_cnt, d_twid_idx, d_data_idx, sine, cosine.asg AR1,GROUP_COUNTER.asg AR2,PX.asg AR3,QX.asg AR4,WR.asg AR5,WI.asg AR6,BUTTERFL Y_COUNTER.asg AR7,DATA_PROC_BUF ; for Stages 1 & 2.asg AR7,STAGE_COUN

11、TER ; for the remaining stagesK_ZERO_BK .set 0K_TWID_TBL_SIZE .set 512 ; Twiddle table sizeK_DATA_IDX_1 .set 2 ; Data index for Stage 1K_DATA_IDX_2 .set 4 ; Data index for Stage 2K_DATA_IDX_3 .set 8 ; Data index for Stage 3K_FLY_COUNT_3 .set 4 ; Butterfly counter for Stage 3K_TWID_IDX_3 .set 128 ; T

12、widdle index for Stage 3.def fft.text;fft:fft:; Stage 1 -STM #K_ZERO_BK,BK ; BK=0 so that *ARn+0% = *ARn+0LD #-1,ASM ; outputs div by 2 at each stageMVMM DATA_PROC_BUF,PX ; PX -> PRLD *PX,16,A ; A := PRSTM #fft_data+K_DATA_IDX_1,QX ; QX -> QRSTM #K_FFT_SIZE/2-1,BRCRPTBD stage1end-1STM #K_DATA_

13、IDX_1+1,AR0SUB *QX,16,A,B ; B := PR-QRADD *QX,16,A ; A := PR+QRSTH A,ASM,*PX+ ; PR':= (PR+QR/2ST B,*QX+ ; QR':= (PR-QR/2|LD *PX,A ; A := PISUB *QX,16,A,B ; B := PI-QIADD *QX,16,A ; A := PI+QISTH A,ASM,*PX+0 ; PI':= (PI+QI/2ST B,*QX+0% ; QI':= (PI-QI/2|LD *PX,A ; A := next PRstage1end

14、:; Stage 2 -MVMM DATA_PROC_BUF,PX ; PX -> PRSTM #fft_data+K_DATA_IDX_2,QX ; QX -> QRSTM #K_FFT_SIZE/4-1,BRCLD *PX,16,A ; A := PRRPTBD stage2end-1STM #K_DATA_IDX_2+1,AR0; 1st butterflySUB *QX,16,A,B ; B := PR-QRADD *QX,16,A ; A := PR+QRSTH A,ASM,*PX+ ; PR':= (PR+QR/2ST B,*QX+ ; QR':= (P

15、R-QR/2|LD *PX,A ; A := PISUB *QX,16,A,B ; B := PI-QIADD *QX,16,A ; A := PI+QISTH A,ASM,*PX+ ; PI':= (PI+QI/2STH B,ASM,*QX+ ; QI':= (PI-QI/2; 2nd butterflyMAR *QX+ADD *PX,*QX,A ; A := PR+QISUB *PX,*QX-,B ; B := PR-QISTH A,ASM,*PX+ ; PR':= (PR+QI/2SUB *PX,*QX,A ; A := PI-QRST B,*QX ; QR

16、9;:= (PR-QI/2|LD *QX+,B ; B := QRST A, *PX ; PI':= (PI-QR/2|ADD *PX+0%,A ; A := PI+QRST A,*QX+0% ; QI':= (PI+QR/2|LD *PX,A ; A := PRstage2end:; Stage 3 thru Stage logN-1 -STM #K_TWID_TBL_SIZE,BK ; BK = twiddle table size always ST #K_TWID_IDX_3,d_twid_idx ; init index of twiddle tableSTM #K_

17、TWID_IDX_3,AR0 ; AR0 = index of twiddle table STM #cosine,WR ; init WR pointerSTM #sine,WI ; init WI pointerSTM #K_LOGN-2-1,STAGE_COUNTER ; init stage counterST #K_FFT_SIZE/8-1,d_grps_cnt ; init group counterSTM #K_FLY_COUNT_3-1,BUTTERFLY_COUNTER ; init butterfly counterST #K_DATA_IDX_3,d_data_idx ;

18、 init index for input datastage:STM #fft_data,PX ; PX -> PRLD d_data_idx, AADD *(PX,ASTLM A,QX ; QX -> QRMVDK d_grps_cnt,GROUP_COUNTER ; AR1 contains group counter group:MVMD BUTTERFL Y_COUNTER,BRC ; # of butterflies in each group RPTBD butterflyend-1LD *WR,T ; T := WRMPY *QX+,A ; A := QR*WR |

19、 QX->QIMACR *WI+0%,*QX-,A ; A := QR*WR+QI*WI; | QX->QRADD *PX,16,A,B ; B := (QR*WR+QI*WI+PRST B,*PX ; PR':=(QR*WR+QI*WI+PR/2 |SUB *PX+,B ; B := PR-(QR*WR+QI*WI; | PX->PIST B,*QX ; QR':= (PR-(QR*WR+QI*WI/2 |MPY *QX+,A ; A := QR*WI T=WI; | QX->QIMASR *QX,*WR+0%,A ; A := QR*WI-QI*WR

20、ADD *PX,16,A,B ; B := (QR*WI-QI*WR+PIST B,*QX+ ; QI':=(QR*WI-QI*WR+PI/2; | QX->QR|SUB *PX,B ; B := PI-(QR*WI-QI*WRLD *WR,T ; T := WRST B,*PX+ ; PI':= (PI-(QR*WI-QI*WR/2; | PX->PR|MPY *QX+,A ; A := QR*WR | QX->QI butterflyend:; Update pointers for next groupPSHM AR0 ; preserve AR0MVD

21、K d_data_idx,AR0MAR *PX+0 ; increment PX for next groupMAR *QX+0 ; increment QX for next groupBANZD group,*GROUP_COUNTER-POPM AR0 ; restore AR0MAR *QX-; Update counters and indices for next stageLD d_data_idx,ASUB #1,A,B ; B = A-1STLM B,BUTTERFL Y_COUNTER ; BUTTERFLY_COUNTER = #flies-1STL A,1,d_data

22、_idx ; double the index of dataLD d_grps_cnt,ASTL A,ASM,d_grps_cnt ; 1/2 the offset to next group LD d_twid_idx,ASTL A,ASM,d_twid_idx ; 1/2 the index of twiddle table BANZD stage,*STAGE_COUNTER- ; AR0 = index of twiddle table MVDK d_twid_idx,AR0Fft_end:RET ; return to Real FFT main module .end3. INI

23、TRFFT.ASM.include "fft_size.inc".def fft_data, _real_fft_input,_real_fft_in, real_fft_output, sine, cosine .def FFT_DP, d_grps_cnt, d_twid_idx, d_data_idx, BOS, TOS; Set start addresses of buffers.datafft_data .space 2*K_FFT_SIZE*16 ; fft data processing buffer_real_fft_input .space 2*K_FF

24、T_SIZE*16 ; real fft input buffer_real_fft_in .space 2*K_FFT_SIZE*16 ; real fft input buffer.sect "power"real_fft_output .space 2*K_FFT_SIZE*16 ; real fft output buffer (power; Copy twiddle tables.sect "sin_tbl"sine .copy twiddle1 ; sine table.sect "cos_tbl"cosine .copy

25、 twiddle2 ; cosine table; Define variables for indexing input data and twiddle tablesFFT_DP .usect "fft_vars",0d_grps_cnt .usect "fft_vars",1 ; (# groups in current stage-1d_twid_idx .usect "fft_vars",1 ; index of twiddle tablesd_data_idx .usect "fft_vars",1 ;

26、 index of input data table; Set up stackBOS .usect "stack",0FhTOS .usect "stack",1.end4. mcbsp54.h#ifndef _MCBSP_H_#define _MCBSP_H_#include "regs54xx.h"/* Bits, Bitfields, . */#define MCBSP_RX 1#define MCBSP_TX 2#define MCBSP_BOTH 3/* CONFIGURATION REGISTER BIT and BIT

27、FIELD values */* Serial Port Control Register SPCR1 */#define DLB_ENABLE 0x01 /* Enable Digital Loopback Mode */ #define DLB_DISABLE 0x00 /* Disable Digital Loopback Mode */ #define RXJUST_RJZF 0x00 /* Receive Right Justify Zero Fill */#define RXJUST_RJSE 0x01 /* Receive Right Justify Sign Extend */

28、 #define RXJUST_LJZF 0x02 /* Receive Left Justify Zero Fill */#define CLK_STOP_DISABLED 0x00 /* Normal clocking for non-SPI mode */#define CLK_START_W/O_DELAY 0x10 /* Clock starts without delay */ #define CLK_START_W_DELAY 0x11 /* Clock starts with delay */ #define DX_ENABLE_OFF 0x00 /* no extra del

29、ay for turn-on time */#define DX_ENABLE_ON 0x01 /* enable extra delay for turn-on time */#define ABIS_DISABLE 0x00 /* A-bis mode is disabled */#define ABIS_ENABLE 0x01 /* A-bis mode is enabled */* Serial Port Control Registers SPCR1 and SPCR2 */#define INTM_RDY 0x00 /* R/X INT driven by R/X RDY */ #

30、define INTM_BLOCK 0x01 /* R/X INT driven by new multichannel blk*/ #define INTM_FRAME 0x02 /* R/X INT driven by new frame sync */ #define INTM_SYNCERR 0x03 /* R/X INT generated by R/X SYNCERR */ #define RX_RESET 0x00 /* R or X in reset */#define RX_ENABLE 0x01 /* R or X enabled */* Serial Port Contr

31、ol Register SPCR2 */#define SP_FREE_OFF 0x00 /* Free running mode is diabled */#define SP_FREE_ON 0x01 /* Free running mode is enabled */#define SOFT_DISABLE 0x00 /* SOFT mode is disabled */ #define SOFT_ENABLE 0x01 /* SOFT mode is enabled */ #define FRAME_GEN_RESET 0x00 /* Frame Synchronization log

32、ic is reset */ #define FRAME_GEN_ENABLE 0x01 /* Frame sync signal FSG is generated */#define SRG_RESET 0x00 /* Sample Rate Generator is reset */ #define SRG_ENABLE 0x01 /* Sample Rate Generator is enabled */* Pin Control Register PCR */#define IO_DISABLE 0x00 /* No General Purpose I/O Mode */#define

33、 IO_ENABLE 0x01 /* General Purpose I/0 Mode enabled */ #define CLKR_POL_RISING 0x01 /* R Data Sampled on Rising Edge of CLKR */ #define CLKR_POL_FALLING 0x00 /* R Data Sampled on Falling Edge of CLKR*/ #define CLKX_POL_RISING 0x00 /* X Data Sent on Rising Edge of CLKX */ #define CLKX_POL_FALLING 0x0

34、1 /* X Data Sent on Falling Edge of CLKX */ #define FSYNC_POL_HIGH 0x00 /* Frame Sync Pulse Active High */ #define FSYNC_POL_LOW 0x01 /* Frame Sync Pulse Active Low */ #define CLK_MODE_EXT 0x00 /* Clock derived from external source */ #define CLK_MODE_INT 0x01 /* Clock derived from internal source *

35、/#define FSYNC_MODE_EXT 0x00 /* Frame Sync derived from external src */ #define FSYNC_MODE_INT 0x01 /* Frame Sync dervived from internal src */ /* Transmit Receive Control Register XCR/RCR */#define SINGLE_PHASE 0x00 /* Selects single phase frames */ #define DUAL_PHASE 0x01 /* Selects dual phase fra

36、mes */ #define MAX_FRAME_LENGTH 0x7f /* maximum number of words per frame */ #define WORD_LENGTH_8 0x00 /* 8 bit word length (requires filling */#define WORD_LENGTH_12 0x01 /* 12 bit word length "" */ #define WORD_LENGTH_16 0x02 /* 16 bit word length "" */ #define WORD_LENGTH_20

37、0x03 /* 20 bit word length "" */ #define WORD_LENGTH_24 0x04 /* 24 bit word length "" */ #define WORD_LENGTH_32 0x05 /* 32 bit word length (matches DRR DXR sz*/ #define MAX_WORD_LENGTH 0x20 /* maximum number of bits per word */#define NO_COMPAND_MSB_1ST 0x00 /* No Companding, Dat

38、a XFER starts w/MSb */ #define NO_COMPAND_LSB_1ST 0x01 /* No Companding, Data XFER starts w/LSb */ #define COMPAND_ULAW 0x02 /* Compand ULAW, 8 bit word length only */ #define COMPAND_ALAW 0x03 /* Compand ALAW, 8 bit word length only */ #define FRAME_IGNORE 0x01 /* Ignore frame sync pulses after 1st

39、 */ #define NO_FRAME_IGNORE 0x00 /* Utilize frame sync pulses */#define DATA_DELAY0 0x00 /* 1st bit in same clk period as fsync */#define DATA_DELAY1 0x01 /* 1st bit 1 clk period after fsync */#define DATA_DELAY2 0x02 /* 1st bit 2 clk periods after fsync */* Sample Rate Generator Register SRGR */* C

40、lock mode (ext. / int. see PCR */#define MAX_SRG_CLK_DIV 0xff /* max value to divide Sample Rate Gen Cl*/#define MAX_FRAME_WIDTH 0xff /* maximum FSG width in CLKG periods */ #define MAX_FRAME_PERIOD 0x0fff /* FSG period in CLKG periods */ #define FSX_DXR_TO_XSR 0x00 /* Transmit FSX due to DXR to XSR

41、 copy */ #define FSX_FSG 0x01 /* Transmit FSX due to FSG */#define CLKS_POL_FALLING 0x00 /* falling edge generates CLKG and FSG */ #define CLKS_POL_RISING 0x01 /* rising edge generates CLKG and FSG */ #define GSYNC_OFF 0x00 /* CLKG always running */ #define GSYNC_ON 0x01 /* CLKG and FSG synch'ed

42、 to FSR */* Multi-channel Control Register 1 and 2 MCR1/2 */#define RMCM_CHANNEL_ENABLE 0x00 /* all 128 channels enabled */#define RMCM_CHANNEL_DISABLE 0x01 /* all channels disabled, selected by */ /* enabling RP(A/BBLK, RCER(A/B */#define XMCM_CHANNEL_DX_DRIVEN 0x00 /* transmit data over DX pin for

43、 as many */ /* number of words as required */#define XMCM_XCER_CHAN_TO_DXR 0x01 /* selected channels written to DXR */ #define XMCM_ALL_WORDS_TO_DXR 0x02 /* all words copied to DXR(1/2, */ /* DX only driven for selected words */#define XMCM_CHANNEL_SYM_R/X 0x03 /* symmetric transmit and receive */ /

44、* operation */#ifdef _INLINE#define _INLINE static inline#else#define _INLINE#endif/* Function Definitions */_INLINE void mcbsp_init(unsigned short port_no,unsigned int spcr1_ctrl, unsigned int spcr2_ctrl,unsigned int rcr1_ctrl, unsigned int rcr2_ctrl,unsigned int xcr1_ctrl, unsigned int xcr2_ctrl,u

45、nsigned int srgr1_ctrl, unsigned int srgr2_ctrl,unsigned int mcr1_ctrl, unsigned int mcr2_ctrl,unsigned int rcera_ctrl, unsigned int rcerb_ctrl,unsigned int xcera_ctrl, unsigned int xcerb_ctrl,unsigned int pcr_ctrl;#ifdef _INLINE/*/ /* mcbsp_init - initialize and start serial port operation */* */ /

46、*/ static inline void mcbsp_init(unsigned short port_no,unsigned int spcr1_ctrl, unsigned int spcr2_ctrl, unsigned int rcr1_ctrl, unsigned int rcr2_ctrl, unsigned int xcr1_ctrl, unsigned int xcr2_ctrl, unsigned int srgr1_ctrl, unsigned int srgr2_ctrl, unsigned int mcr1_ctrl, unsigned int mcr2_ctrl,

47、unsigned int rcera_ctrl, unsigned int rcerb_ctrl, unsigned int xcera_ctrl, unsigned int xcerb_ctrl, unsigned int pcr_ctrl/*/ /* Place port in reset - setting XRST & RRST to 0 */*/ MCBSP_SUBREG_BITWRITE(port_no, SPCR1_SUBADDR, RRST, RRST_SZ, 0; MCBSP_SUBREG_BITWRITE(port_no, SPCR2_SUBADDR, XRST,

48、XRST_SZ, 0; /*/ /* Set values of all control registers */*/ MCBSP_SUBREG_WRITE(port_no, RCR1_SUBADDR, rcr1_ctrl;MCBSP_SUBREG_WRITE(port_no, RCR2_SUBADDR, rcr2_ctrl;MCBSP_SUBREG_WRITE(port_no, XCR1_SUBADDR, xcr1_ctrl;MCBSP_SUBREG_WRITE(port_no, XCR2_SUBADDR, xcr2_ctrl;MCBSP_SUBREG_WRITE(port_no, SRGR

49、1_SUBADDR, srgr1_ctrl;MCBSP_SUBREG_WRITE(port_no, SRGR2_SUBADDR, srgr2_ctrl;MCBSP_SUBREG_WRITE(port_no, MCR1_SUBADDR, mcr1_ctrl;MCBSP_SUBREG_WRITE(port_no, MCR2_SUBADDR, mcr2_ctrl;MCBSP_SUBREG_WRITE(port_no, RCERA_SUBADDR, rcera_ctrl;MCBSP_SUBREG_WRITE(port_no, RCERB_SUBADDR, rcerb_ctrl;MCBSP_SUBREG

50、_WRITE(port_no, XCERA_SUBADDR, xcera_ctrl;MCBSP_SUBREG_WRITE(port_no, XCERB_SUBADDR, xcerb_ctrl;MCBSP_SUBREG_WRITE(port_no, PCR_SUBADDR, pcr_ctrl;MCBSP_SUBREG_BITWRITE(port_no, SPCR1_SUBADDR, RRST, RRST_SZ, 1; MCBSP_SUBREG_BITWRITE(port_no, SPCR2_SUBADDR, XRST, XRST_SZ, 1; #endif/* Macro Definitions

51、 */*/ /* MCBSP_BYTES_PER_WORD - return # of bytes required to hold # */* of bits indicated by wdlen */*/ #define MCBSP_BYTES_PER_WORD(wdlen (int(wdlen + 1 / 2/*/* MCBSP_ENABLE(unsigned short port_no, unsigned short type - */* starts serial port receive and/or transmit */* type= 1 rx, type= 2 tx, type= 3 both */*/#define MCBSP_ENABLE(port_no,mode REG_WRITE(SPCR1_ADDR(port_no, (MCBSP_SUBREG_READ(port_no, SPCR1_SUBADDR | (mode & 1; REG_WRITE(SPCR2_ADDR(port_no, (MCBSP_SUBREG_READ(port_no, S