研一课程考试数字集成assig

1、Assignment 3聪201428007326030计控学院1.Access relevant reference books or technical data books and give accurate definitions for the following timing parameters:(1) propagation time tPD,(2) transition time tTD,(3) setup time tSU,(4) hold time tHD,(5) clock-to-output time tCO.propagation time tPD :传送时间是从输

2、入脉冲到引起输出电平跳变之间的时间间隔。transition timetTD : Transitiontime is the dynamical system need to switchbetween two different stable states, when responding to a stable input signal. setup time tSU :建立时间是在时钟到达之前，输入信号稳定不变的一段时间。hold time tHD:保持时间是在时钟上升沿到来之后，数据在改变之前稳定不变的时间。clock-to-output time tCO:输出时钟时间是在时钟边沿过去

3、之后，为了使信号正常输出，仍然要保持信号稳定不变的一段时间。2.Construct VHDL ms for 74-139 dual 2-to-4-line decoders using threedescription types, i.e., behavioral, dataflow and structural descriptions. Synthesizeand simulate these ms respectively in the environment of Xilinx ISE with theMSim simulator integrated. When simulatin

4、g these ms, test vector(s) arerequired to stimulate the units under test (UUT). Reasonable test vectors are designed and created by your own as sources added to your VHDL project.Logic schematic of 74-139:Function table of one decoder of 74-139:答：行为描述：只描述电路的功能，不提供电路的硬件结构。数据流描述：分析寄存器之间的逻辑，利用逻辑关系描述电路。

5、结构描述：用各种元件描述电路。(1)Behavioral description:library IEEE;use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VComponents.all;entity decode

6、r_behavior is port(A1:in std_logic;B1:in std_logic; G1:in std_logic;INPUTSOUTPUTSENABLEGSELECTBAY0Y1Y2Y3HXXHHHHLLLLHHHLLHHLHHLHLHHLHLHHHHHLA2:in std_logic; B2:in std_logic; G2:in std_logic;Y1:out std_logic_vector(3 downto 0); Y2:out std_logic_vector(3 downto 0);end decoder_behavior;architecture Beha

7、vioral of decoder_behavior is beginprocess(A1,B1,G1) beginif G1='1' then Y1<="1111" elsif(A1='0')and(B1='0') then Y1<="1110"elsif(A1='1')and(B1='0') then Y1<="1101"elsif(A1='0')and(B1='1') then Y1<=&quo

8、t;1011" else Y1<="0111"end if; end process;process(A2,B2,G2) beginif G2='1' then Y2<="1111" elsif(A2='0')and(B2='0') then Y2<="1110"elsif(A2='1')and(B2='0') then Y2<="1101"elsif(A2='0')and(B2=

9、9;1') then Y2<="1011" else Y2<="0111"end if; end process;end Behavioral;Synthesis Result:Simulation Result:(2)Dataflow description:library IEEE;use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following library de

10、claration if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VComponents.all;entity decoder_dataflow is port(A1,B1,G1:in std_logic;A2,B2,G2:in std_logic; Y10,Y11,Y12,Y13:out std_logic; Y20,Y21,Y22,Y23:out std_logic);end decoder_dataflow;architecture dataflow of decoder_

11、dataflow is beginY10<='0' when(A1='0')and(B1='0')and(G1='0') else '1'Y11<='0' when(A1='1')and(B1='0')and(G1='0') else '1'Y12<='0' when(A1='0')and(B1='1')and(G1='0') else '1

12、9;Y13<='0' when(A1='1')and(B1='1')and(G1='0') else '1'Y20<='0' when(A2='0')and(B2='0')and(G2='0') else '1'Y21<='0' when(A2='1')and(B2='0')and(G2='0') else '1'Y22<='

13、0' when(A2='0')and(B2='1')and(G2='0') else '1'Y23<='0' when(A2='1')and(B2='1')and(G2='0') else '1'end dataflow;Synthesis Result:Simulation Result:(3)Structural Description结构描述是通过对电路元件之间端口的描述来定义电路的，所以首先，要知道电路使用了哪些元件，以及各端口之

14、间相连的关系。从74139的结构图可以看出， 使用了10个反相器与8各三输入的与非门。编程实现反相器与三输入与非门，再使用多个反相器与三输入与非门将电路描述出来。程序代码如下：其中NOT_1 表示反相器，AND_NOT3表示三输入与非门。library IEEE;use IEEE.std_logic_1164.ALL;entity NOT_1 is port(i:in bit;o: out bit); end entity;architecture func_1 of NOT_1 is begino<=not i; end func_1;entity AND_NOT3 is port(i

15、1,i2,i3:in bit;o: out bit); end entity;architecture func_2 of AND_NOT3 is begino<=not (i1 and i2 and i3); end func_2;entity structure7 is port(G1,G2: in bit;A1,B1,A2,B2: in bit; Y10,Y11,Y12,Y13: out bit; Y20,Y21,Y22,Y23: out bit);end entity;architecture Behavioral of structure7 is component NOT_1

16、 isport(i: in bit;o: out bit);end component; component AND_NOT3 isport(i1,i2,i3: in bit;o:out bit);end component;signal G1_R,A1_R,B1_R,G2_R,A2_R,B2_R: bit; signal A1_RR,B1_RR,A2_RR,B2_RR: bit;beginn1: NOT_1 port map(G1,G1_R); n2: NOT_1 port map(A1,A1_R); n3: NOT_1 port map(B1,B1_R); n4: NOT_1 port m

17、ap(G2,G2_R); n5: NOT_1 port map(A2,A2_R); n6: NOT_1 port map(B2,B2_R);n7: NOT_1 port map(A1_R,A1_RR); n8: NOT_1 port map(B1_R,B1_RR); n9: NOT_1 port map(A2_R,A2_RR); n10: NOT_1 port map(B2_R,B2_RR);an1: AND_NOT3 port map(A1_R,B1_R,G1_R,Y10); an2: AND_NOT3 port map(G1_R,B1_R,A1_RR,Y11); an3: AND_NOT3

18、 port map(G1_R,A1_R,B1_RR,Y12); an4: AND_NOT3 port map(G1_R,A1_RR,B1_RR,Y13); an5: AND_NOT3 port map(A2_R,B2_R,G2_R,Y20); an6: AND_NOT3 port map(G2_R,B2_R,A2_RR,Y21); an7: AND_NOT3 port map(G2_R,A2_R,B2_RR,Y22); an8: AND_NOT3 port map(G2_R,A2_RR,B2_RR,Y23);end Behavioral;Synthesis Result:Simulation Result:3. (Optional) Macrocells (MCs) are key components of Complex Programmable Logic Device (PLD). Based on the MC logic schemat