C兼容微处理器单片机PWM控制器设计方案

1、作者：Pan Hon glia ng仅供个人学习Design of PWM Controller in a MCS-51 Compatible MCUIn troduct ionPWM tech no logy is a ki nd of voltage regulati on method by con trolli ng the switch freque ncy of DC power with fixed voltage to modify the two-e nd voltage of load. This tech no logy can be used for a variety

2、 of applications including motor control, temperature control and pressure con trol and so on. In the motor con trol system show n as Fig. 1, through adjust ing the duty cycle of power switch, the speed of motor can be con trolled. As show n in Fig. 2, un der the con trol of PWM sig nal, the average

3、 of voltage that con trols the speed of motor cha nges with Duty-cycle ( D =t1/T in this Figure ), thus the motor speed can be in creased whe n motor power tur n on, decreased whe n power turn off.Fig.1: The Relati on ship betwee n V oltage of Armature andFig.2 Architecture of PWMModuleTherefore, th

4、e motor speed can be con trolled with regularly adjusti ng the time of turn-o n and turn-off. There are three methods could achieve the adjustme nt of duty cycle: (1) Adjust freque ncy with fixed pulse-width. (2) Adjust both freque ncy and pulse-width. (3) Adjust pulse-width with fixed freque ncy.Ge

5、n erally, there are four methods to gen erate the PWM sig nals as the followi ng: (1) Gen erated by the device composed of separate logic comp onen ts. This method is the origi nal method which now has bee n discarded. (2) Gen erated by software. This method n eed CPU to continu ously operate in str

6、uct ions to con trol I/O pins for gen erat ing PWM output sig nals, so that CPU can not do anything other. Therefore, the method also has been discarded gradually. (3) Gen erated by ASIC. The ASIC makes a decrease of CPU burde n and steady work gen erally has several functions such as over-curre nt

7、protect ion, dead-time adjustme nt and so on. Then the method has bee n widely used in many kinds of occasi on now. (4) Gen erated by PWM fun cti on module of MCU. Through embedding PWM function module in MCU and initializing the fun ctio n, PWM pins of MCU can also automatically gen erate PWM out s

8、ig nals without CPU controlling only when need to change duty-cycle. It is the method that will be implemented in this paper.In this paper, we propose a PWM module embedded in a 8051 microc on troller. The PWM module can support PWM pulse sig nals by in itializ ing the con trol register and duty-cyc

9、le register with three methods just men ti oned above to adjust the duty cycle and several operati on modes to add flexibility for user.The followi ng sect ion expla ins the architecture of the PWM module and the architectures of basic functional blocks. Section3 describes two operation modes. Exper

10、imental and simulation results verify ing proper system operati on are also show n in that sect ion. Depe nding on mode of operati on, the PWM module creates one or more pulse-width modulated sig nals, whose duty ratios can be in depe nden tly adjusted.Impleme ntatio n of PWM module in MCUOverview o

11、f the PWM moduleA block diagram of PWM module is shown in Fig.3. It is clearly from the diagram that the whole module is composed of two secti ons: PWM sig nal gen erator and dead-time gen erator with cha nnel select logic. The PWM function can be started by the user through impleme nting some in st

12、ruct ions for in itializi ng the PWM module. In particular, the followi ng power and moti on con trol applicati ons are supported:? DC Motor? Unin terruptablel Power Supply (UPS)The PWM module also has the following features:? Two PWM signal o utputs with complementary or independent operation? Hard

13、ware dead-time gen erators for compleme ntary mode? Duty cycle updates are con figurable to be immediated or synchroni zed to the PWMFig.3 Architecture of PWM ModuleDetails of the architecturePMW gen eratorThe architecture of the 2-output PWM generator shown in Fig.4 is based on a 16-bit resoluti on

14、 coun ter which creates a pulse-width modulated sig nal. The system is syn thesized by a system clock signal whose frequency can be divided by 4 times or 12 times through setting the value of T3M for PWM0 or T4M for PWM1 in the special register PWMCON as shown in Fig.4. To PWM0 gen erator, the clock

15、 to 16-bit coun ter will be pre-divided by 4 times by default whe n T3M is set to zero. And the clock will be divided by 12 times when T3M is set to 1. This is also true for PWM1. The other bits in PWMCON are explained in detail in Table 1.Fig .4Bit Mappi ng of PWMCONTable 1: The Bit Definition in P

16、WMCONChann el-select logicThe follow Fig. 5 shows the channel-select logic which is useful in Complementary Mode. From this diagram, it is clear to know that sig nal CP and CPWM control the source of PWMH and PWML. And the details about the two con trol sig nals will be discussed in the sect ion 3,

17、and the architecture of dead-time gen erator will also be discussed in sect ion 5 for the continuity of Compleme ntary Mode.Fig. 5 Diagram of Chann el-select LogicOperati on Mode and Simulati on ResultsThe design has two operation modes: Independent Mode and Complimentary Mode. By sett ing the corre

18、sp onding bit CPWM in register PWMCON show n in Fig.6 user can select one of the two operation modes. When CPWM is set to zero, PWM module will work in Independent Mode, whereas, PWM module will work in Complime ntary Mode. In the followi ng of this sect ion, the two operation mode will be explained

19、 respectively in detail and the simulation results of the PWM module from the Synoposys VCS EDA platform which verify the design will also be show n.In depe ndent PWM Output ModeAn Independent PWM Output mode is useful for driving loads such as the one shown in Figure 6. A particular PWM output is i

20、n the In depe ndent Output mode whe n the corresp onding CP bit i n the PWMCON register is set to zero.ln this case, two-cha nnel PWM outputs are in depe ndent of each other. The sig nal on pin PWM0/PWMH is from PWM0 gen erator, and the sig nal on pin PWM1/PWML is from PWM0 gen erator. The separate

21、case is achieved by the cha nn el-select logic show n in Fig. 6. The PWM I/O pins are set to in depe ndent mode by default upon advice reset. The dead-time gen erator is disabled in the In depe ndent mode. The simulati on result is show n in Figure 6 as the followi ng Fig.6 Tr4 and tr3 are run bits

22、to PWM0 and PWM1, respectively. Actually, from this diagram, Pin P15/ P14 of MCU is used for PWMH/ PWML or normal I/O ,alternatively.Fig6 the Waveform of PWM Outputs in In depe ndent ModeCompleme ntary PWM Output ModeThe Complementary Output mode is used to drive inverter loads similar to the one sh

23、own inFigure 7. This in verter topology is typical for DC applicati ons. In Compleme ntary Output Mode, the pair of PWM outputs cannot be active simulta neously. The PWM cha nnel and output pin pair are in ternally con figured through cha nn el-select logic as show n in Figure7. A dead-time may be o

24、ptio nally in serted duri ng device switch ing where both outputs are in active for a short period.Fig 7 : Typical Load for Compleme ntary PWM OutputsThe Complementary mode is selected for PWM I/O pin pair by setting the appropriate CPWM bit in PWMCON. In this case, PSEL is in effect. PWMH and PWML

25、will come from PWMO generator when PSEL is set to zero, when the signals from PWM1 generator is useless, whereas PWMH and PWML will come from PWM1 gen erator whe n PSEL is set to 1, whe n the signals from PWM0 generator is useless. In the process of producing the PWM outputs in Compleme ntary Mode,

26、the dead-time will be in serted to be discussed in the followi ng sect ion. Dead-time Con trolDead-time generation is automatically enabled when PWM I/O pin pair is operating in the Compleme ntary Output mode. Because the power output devices cannot switch in sta ntan eously, some amount of time mus

27、t be provided between the turn-off event of one PWM output in a compleme ntary pair and the turn-o n event of the other tran sistor. The 2-output PWM module has one programmable dead-time with 8-bit register.The complementary output pair for the PWM module has an 8-bit down counter that is used to p

28、roduce the dead-time insertion. As shown in Figure 8, the dead time unit has a rising and falling edge detector connected to PWM signal from one of PWM gen erator. The dead times is loaded into the timer on the detected PWM edge event. Depe nding on whether the edge is rising or falli ng, one of the

29、 tran siti ons on the compleme ntary outputs is delayed un til the timer counts dow n to zero. A tim ing diagram in dicat ing the dead time in serti on for the pair of PWM outputs is show n in Figure 8a.Fig 8a Dead-time Unit Block DiagramFig. 8b the Waveforms of PWM Outputs in Compleme ntary ModeCon

30、 clusi onsIn this paper, we have desig ned PWM module based on an 8-bit MCU compatible with 8051 family. The desig n can gen erate 2-cha nnel programmable periodic PWM sig nals with two operation mode, Independent Mode and Complementary Mode in which dead-time will be in serted. The simulati on results on the EDA platform have prove n its correct ness and usefu In ess.版权申明本文部分内容，包括文字、图片、以及设计等在网上搜集整理。版权为潘宏亮个人所有This article in eludes someparts, in cludi ng text, pictures, and desig n. Copyright is Pan Hon glia ng's pers onal own ership.用户可将本文的内容或服务用于个人学习、