AD9959数据手册部分内容中文翻译

1、AD9959数据手册(部分)GENERAL DESCRIPTIO概N述The AD9959 consists of four direct digitalsynthesizer (DDS) cores that provideindependent frequency, phase, and amplitude control on each channel. This flexibility can be used to correct imbalances between signals due to analog processing, such as filtering, amplif

2、ication, or PCB layout-related mismatches. Because all channels share a common system clock, they are inherently synchronized. Synchronization of multiple devices is supported. The AD9959 can perform up to a 16-level modulation of frequency, phase, or amplitude (FSK, PSK, ASK). Modulation is perform

3、ed by applying data to the profile pins. In addition, the AD9959 also supports linear sweep of frequency, phase, or amplitude for applications such as radar and instrumentation.AD9959含有四个直接数字频率合成器 ( DDS)，提供各通道独立的频率、 相位和振幅控制。 这种灵活性可以用来纠正信号之间的不平衡，这种不平衡是由于模拟处理，如滤波，放大， 或 PCB布局相关的不匹配导致。因为所有通道共用一个系统时钟，因此固

4、有的同步。也支持 多个设备的同步。 AD9959可以执行 16 级频率、相位、振幅( FSK，PSK，ASK)调制，通过将 数据传到配置引脚执行。此外， AD9959还支持频率、线性扫频、相位或振幅的应用，如雷达 和仪表。The AD9959s erial I/O port offers multiple configurations to provide significant flexibility. The serial I/O port offers an SPI- compatible mode of operation that is virtually identical to

5、the SPI operation found in earlier Analog Devices, Inc., DDSp roducts. Flexibility is provided by four data pins (SDIO_0/SDIO_1/ SDIO_2/SDIO_3) that allow four programmable modes of serial I/O operation.AD9959的串行 I/O 端口提供了多种配置，提供显著的灵活性。串行 I / O 端口提供了一 个 SPI 兼容的操作模式， SPI 操作与较早的模拟设备公司 DDS产品几乎相同。灵活性是通过

6、 四个数据引脚( sdio_0 / sdio_1 /sdio_2 / sdio_3)允许四可编程串行 I/O 操作模式来实现的。The AD9959u ses advanced DDSt echnology that provides low power dissipation with high performance. The device incorporates four integrated, high speed 10-bit DACs with excellent wideband and narrow-band SFDR. Each channel has a dedicate

7、d 32-bit frequency tuning word, 14 bits of phase offset, and a 10-bit output scale multiplier.AD9959采用先进的 DDS技术，提供低高性能低功耗。该器件集成了四个高速10 位 DAC具有优良的宽带和窄带 SFDR。每个通道有一个专门的 32位频率调谐字， 14 位相位偏移，和 一个 10 位幅度调节输出。The DAC outputs are supply referenced and must be terminated into AVDD by a resistor or an AVDD ce

8、nter-tapped transformer. Each DAC has its own programmable reference to enable different full-scale currents for each channel. The DDS acts as a high resolution frequency divider with the REFCLKa s the input and the DACp roviding the output. The REFCLK input source is common to all channels and can

9、be driven directly or used in combination with an integrated REFCLK multiplier (PLL) up to a maximum of 500 MSPS. The PLL multiplication factor is programmable from 4 to 20, in integer steps. The REFCLK input also features an oscillator circuit to support an external crystal as the REFCLKs ource. Th

10、e crystal must be between 20 MHza nd 30 MHz. The crystal can be used in combination with the REFCLK multiplier.DAC的输出供给参考必须通过电阻接到 AVDD或接到 AVDD中心抽头变压器。每个 DAC有 自己的可编程参考，能提供各通道的不同满量程电流。 REFCLK作为输入时， DDS核心作为一 个高分辨率分频器，以 DAC提供输出。 REFCLK输入源对所有通道是一样的，可直接驱动或用 于与一个集成的 REFCLK乘法器组合( PLL)，最高 500 MSPS。PLL倍增因子可编程

11、，从 4 到 20 的整数。 REFCLK输入还可作为一个振荡器电路，支持外部晶振作为参考源。该晶振必须介 于 20 兆赫和 30 兆赫。晶振可用于与 REFCLK倍频组合。The AD9959c omes in a space-saving 56-lead LFCSPp ackage. The DDSc ore (AVDDa nd DVDD pins) is powered by a V supply. The digital I/O interface (SPI) operates atV and requires DVDD_I/O (Pin 49) be connected to V.

12、The AD9959 operates over the industrial temperature range of - 40 C to +85 C.AD9959使用节省空间的 56引脚 LFCSP封装。DDS的核心（AVDD和DVDD引脚）由 V 供电。 数字 I / O 接口（ SPI）的工作在 V，要求 dvdd_I/O （引脚 49）连接到 V。AD9959可运行在 超过工业温度范围的 - 40C到 85C。ABSOLUTE MAXIMUM RATING绝S对 最大额定值Table 2. 表 2Parameter 参数Rating 额定值Maximum Junction Tempe

13、rature 最大结温150CDVDD_I/O (Pin 49)4 VAVDD, DVDD2 VDigital Input Voltage (DVDD_I/O = V) 数字输入电压- V to +4 VDigital Output Current 数字输出电流5 mAStorage Temperature Range 存储温度65C to +150 COperating Temperature Range 操作温度40C to +85 CLead Temperature (10 sec Soldering) 焊接温度300CJA21C/WJC2C/WTable 3. Pin Function

14、 Descriptions引脚说明引脚助记符I/ O14针描述3MASTER_RESETI6高电平有效复位引脚；将使 AD9959内部寄存器复位到缺省状态，如寄存器图和位描述部分的描述。4PWR DWN CTLI4外部电源控制（ PDC）40-43P0-P3I1、3用于调制 （FSK,PSK,ASK）的数据引脚 , 启动/ 停止扫频5、7累加器或用于输出幅度的斜坡上升或下降 . 数据同步 于引脚 SYNC_CLK 同（ 步时钟 54 脚）. 数据必需满足 SYNC_CLK设 置和保持时间的要求 ; 引脚的功能由数 据配置说明位 （PPC）控制 （FR114:12）.46IO_UPDATEI8上

15、升沿使 I/O 口缓冲中的数据传送到活动寄存器。 数 据同步于引脚 SYNC_CLK （同步时钟 54 脚）. IO- _UPDATE必需满足 SYNC_CLK设 置和保持时间的要 求，以保证到 DAC输出的数据有固定的延迟管道， 否 则，不确定有 1 个同路时钟（ SYNC_CL）K周期的数 据管道存在。最小的脉冲宽度是 1 个同步时钟周期。47CSI10低电平片选；允许多器件共用 I/O 总线。48SCLKI12I/O 操作的串行数据时钟；数据位在 SCLK的上升沿 写入，在下降沿读取。50SDIO_0I/ O9串行数据引脚51 51SDIO_1 SDIO_2I/ O11、13用于串行数据

16、引脚或启动输出幅度的斜坡上升或下 降53SDIO_3I/ O14用于串行数据引脚或启动输出幅度的斜坡上升或下 降；在单位或 2 位模式，此引脚用于 SYNC_I/O。如 果 SYNC_I/O 功能未使用，连接到地或逻辑 0。在单 位或者 2 位模式中，不要让此引脚浮地。THEORY OF OPERATIO操N 作原理DDS CORE DDS核心The AD9959h as four DDSc ores, each consisting of a 32-bit phase accumulator andphase-to-amplitude converter. Together, these d

17、igital blocks generate a digital sine wave when the phase accumulator is clocked and the phase increment value (frequency tuning word） is greater than 0. The phase-to-amplitude converter simultaneouslytranslates phase information to amplitude information by a cos（） operation. Theoutput frequency （fO

18、UT） of each DDS channel is a function of the rollover rate of each phase accumulator. The exact relationship is given in the following equation:AD9959有四个 DDS内核，每个含 32 相位累加器和相位 -幅度转换器。这些数字模块在一 起产生数字正弦波，当相位累加器的时钟和相位增量值（频率调谐字）大于0。相位幅度转换器同时通过 COS（）操作，转换相位信息到幅度信息。每个 DDS通道输出频率（ f out）是 每个相位累加器的转换函数。确切的关系在

19、下面的等式中给出：where: f S is the system clock rate.FTW is the frequency tuning word and is 0 FTW 2 232 represents the phase accumulator capacity.其中：f s 是系统时钟速率。FTW是频率调谐字和 0FTW231。 232表示相位累加器容量。Because all four channels share a common system clock, they are inherently synchronized.因为所有四个通道共用一个系统时钟，他们是本质同步的

20、。The DDSc ore architecture also supports the capability to phase offset the output signal, which is performed by the channel phase offset word (CPOW). The CPOW is a 14-bit register that stores a phase offset value. This value is added to the output of the phase accumulator to offset the current phas

21、e of the output signal. Each channel has its own phase offset word register. This feature can be used for placing all channels in a known phase relationship relative to one another. The exact value ofphase offset is given by the following equation:DDS的核心架构还支持输出信号的相位偏移，由信道的相位偏移（cpow）字实现。 cpow是一个 14位的

22、寄存器，存储相位偏移值。 此值添加到相位累加器的输出， 偏移电流信号相位。 每个通道都有自己的相位偏移字寄存器。此功能可用于设置所有通道的相位相关关系。相位 偏移量实际值由以下方程给出：DIGITAL-TO-ANALOG CONVERT数E模R 转换The AD9959 incorporates four 10-bit current output DACs. The DAC converts a digital code (amplitude) into a discrete analog quantity. The DAC current outputs can be modeled as

23、 a current source with high output impedance (typically 100 k).Unlike many DACs, these current outputs require termination into AVDDv ia a resistor or a center-tapped transformer for expected current flow.AD9959采用四个 10 位电流输出 DAC。DAC将数字代码 (幅度)转换成离散的模拟量。 DAC 的电流输出可以被建模为高输出阻抗的电流源(通常为100 K)。不像许多 DAC，这些电

24、流输出要求通过电阻器或中心抽头变压器接到 AVDD以获得预期的电流。Each DAC has complementary outputs that provide a combined full-scale output current (I OUT + I OUT). The outputs always sink current, and their sum equals the full-scale current at any point in time. The full-scale current is controlled by means of an external resi

25、stor (RSET) and the scalable DAC current control bits discussed in the Modes of Operation section. The resistor, RSET, is connected between the DAC_RSETp in and analog ground (AGND). The full-scale current is inversely proportional to the resistor RSET)value as follows:每个 DAC互补输出提供一个组合的满量程输出电流 (输出电流

26、和输入电流) 。输出总是吸 收电流，在任何时间点它们的和等于满量程电流。满量程电流通过一个外部电阻器(控制和操作模式部分中讨论的 DAC的电流位进行尺度控制。电阻 RSET，连接 DAC_RES脚T 和 模拟地（ AGN）D之间。满量程电流与电阻值成反比：The maximum full-scale output current of the combined DAC outputs is 15 mA, but limiting the output to 10 mA provides optimal spurious-free dynamic range (SFDR) performance

27、. The DAC output voltage compliance range is AVDD + V to AVDD- V.Voltages developed beyond this range may cause excessive harmonic distortion. Proper attention should be paid to the load termination to keep the output voltage within its compliance range. Exceedingthis range could potentially dam-age

28、 the DACoutputcircuitry.最大满量程的输出组合 DAC电流为 15 mA，但限制输出到 10 毫安以提供最优的无杂散动 态范围( SFDR)性能。 DAC的输出电压范围为 AVDD + V 电压 AVDD- 。超出了这个范围可能 会导致谐波失真过大。应注意负载，以保持其输出电压在其合规范围。超过这个范围可能损 坏 DAC输出电路。MODES OF OPERATIO操N作模式There are many combinations of modes (for example, single- tone, modulation, linear sweep) that the A

29、D9959c an perform simultaneously. However, some modes require multiple data pins, which can imposelimitations. The following guidelines can helpdetermine if a specific combination of modes can be performed simultaneously by the AD9959.有许多组合模式(例如，单音，调制，线性扫频) ，AD9959 能够同时进行。然而，一些 模式需要多个数据引脚，它可以施加限制。下面

30、的指南可以帮助确定模式的特定组合是否可 以用 AD9959同时进行。CHANNEL CONSTRAINT GUIDELIN通E道S约束准则Single-tone mode, two-level modulation mode, and linear sweep modec an be enabled on any channel and in any combination at the same time单音模式，两电平调制模式，线性扫频繁模式，可以启用在任何通道，并在同一时间任何组 合。Any one or two channels in any combination can perfo

31、rm four-level modulation. The remaining channels can be in single-tone mode. 任何一个或两个通道可在任何组合执行四电平调制。剩余的通道可以在单音模式。Any channel can perform eight-level modulation. The three remaining channels can be in single-tone mode. 任何一个通道都可以执行八电平调制。三个剩余信道可以在单音模式。Any channel can perform 16-level direct modulation.

32、 The three remaining channels can be in single-tone mode.任何一个通道都可以执行 16 电平直接调制。三个剩余信道可以在单音模式。The RU/RD function can be used on all four channels in single-tone mode. See the Output Amplitude Control Mode section for the RU/RD function. 所有四个通道可以在单音模式下使用 RU / RD 功能。见输出幅度控制块。When Profile Pin P2 and Pro

33、file Pin P3 are used for RU/RD, any two channels can perform two-level modulation with RU/RD or any two channels can perform linear frequency or phase sweep with RU/RD. The other two channels can be in single-tone mode.当配置引脚 P2和配置引脚 P3用于 RU/ RD，任何两个通道可以执行二电平调制与 RU/ RD，或 任何两个通道可以执行线性频率或相位扫描与 RU/RD。其他

34、两个通道可以处于单音模式。 When Profile Pin P3 is used for RU/RD, any channel can be used in eight-level modulation with RU/RD. The other three channels can be in single-tone mode. 当配置引脚 P3用于 RU/ RD，任何通道可以用在八电平调制与 RU/RD，另三通道可以在单音模 式。? When the SDIO_1, SDIO_2, and SDIO_3p ins are used for RU/RD, any one or two ch

35、annels, any three channels, or all four channels can perform two-level modulation with RU/RD. Any channels not in the two-level modulation can be in single-tone mode.当 sdio_1 ， sdio_2 ，和 sdio_3 引脚用于 RU/RD，任何一个或两个通道，三通道，四通道或可以进行两级调制。其它任何通道不在两级调制的，可以处于单音模式。? When the SDIO_1, SDIO_2, and SDIO_3p ins ar

36、e used for RU/RD, any one or two channels can perform four-level modulation with RU/RD. Any channels not in four-level modulation can be in single-tone mode.当 sdio_1 ，sdio_2 ，和 sdio_3 引脚用于 RU/RD，任何一个或两个通道可以进行四级调制。其 它任何通道进行单频模式。? When the SDIO_1, SDIO_2, and SDIO_3p ins are used for RU/RD, any channe

37、l can perform 16-level modulation with RU/RD. The other three channels can be in single-tone mode. 当 sdio_1 ， sdio_2 ，和 sdio_3 引脚用于 RU/RD，任何一个通道可以进行 16 级调制，其他三 个渠道可以在单频模式。? Amplitude modulation, linear amplitude sweep modes, and the RU/RDf unction cannot operate simultaneously, but frequency and pha

38、se modulation can operate simultaneously as the RU/RD function.振幅调制，线性振幅扫描模式，和 RU/ RD功能不能同时操作，但是，频率和相位调制可以同 时随着 RU/RD功能操作。POWER SUPPLIE电S 源供应The AVDD and DVDD supply pins provide power to the DDS core and supporting analog circuitry. These pins connect to a V nominal power supply. The DVDD_I/Op in c

39、onnects to a V nominal power supply. All digital inputs are V logic except for the CLK_MODE_SEL input. CLK_MODE_SEL (Pin 24) is an analog input and should be operated by V logic.AVDD和 DVDD引脚提供 DDS核心的电力供应， 和支持模拟电路。 这些引脚连接到 V 额定电源。 dvdd_I/O 引脚连接到 V 额定电源。所有数字输入 V 逻辑，除了 clk_mode_sel 输入。 clk_mode_sel (引脚

40、 24)是一个模拟输入和应由伏逻辑操作。SINGLE-TONE MOD单E 音模式Single-tone mode is the default mode of operation after a master reset signal.In this mode, all four DDSc hannels share a commona ddress location for the frequency tuning word (Register 0 x04) and phase offset word (Register 0 x05). Channel enable bits are pr

41、ovided in combination with these shared addresses. As a result, the frequency tuning word and/or phase offset word can be independently programmed between channels (see the following Step 1 through Step 5). The channel enable bits do not require an I/O update to enable or disable a channel.单音模式是主复位信

42、号后的缺省操作模式。在这种模式下，所有四个DDS通道共享频率调谐字(寄存器 0 x04)和相位偏移字(寄存器 0 x05)。通道使能位与这些共享地址组合使用。 作为结果，频率调谐字和 /或相位偏移字可以在通道之间独立编程(见下面步骤 1到步骤 5)。 通道使能位不要求 I/O 更新使能或禁用信道。See the Register Maps and Bit Descriptions section for a description of the channel enable bits in the channel select register (CSR, Register 0 x00). T

43、he channel enable bits are enabled or disabled immediately after the CSR data byte is written.请参见寄存器映射和位描述部分，信道使能位的描述在通道选择寄存器(CSR，寄存器0 x00)。在 CSR数据字节写入后，通道使能位立即使能或禁用。Address sharing enables channels to be written simultaneously, if desired. The default state enables allchannel enable bits. Therefore

44、, thefrequency tuning wordand/or phase offset word is commont o all channels but written only once through the serial I/O port.如果需要的话，地址共享使信道能够同时写入。默认状态启用所有通道使能位。因此， 频率调谐字和 / 或相位偏移字是所有通道共用的，可以只通过串行输入输出端口写一次。The following steps present a basic protocol to program a different frequency tuning word and

45、/or phase offset word for each channel using the channel enable bits.面的步骤介绍了一个基本的协议，用来使用通道使能位对每个通道编程实现不同频率调谐字和 / 或相位偏移字。1Power up the DUT and issue a master reset. A master reset places the part in single-tone mode and single-bit modef or serial programming operations (refer to the Serial I/O Modes

46、of Operation section). Frequency tuning words and phase offset words default to 0 at this point.DUT上电和执行主复位。主复位将部件置于单音模式和单位模式串行编程操作(参照串 行 I/O 模式操作部分)。频率调谐字和相位偏移字默认为 0 在这一点上。2. Enable only one channel enable bit (Register 0 x00) and disable the other channel enable bits.只让一个通道使能位使能(寄存器 0 x00)和禁用其他通道使

47、能位。3.Using the serial I/O port, program the desired frequency tuning word (Register 0 x04) and/or the phase offset word (Register 0 x05) for the enabled channel.使用串行 I/O 口，为使能通道的频率调谐字(寄存器 0 x04)和/ 或相位偏移字(寄存器 0 x05)编程。4. Repeat Step 2 and Step 3 for each channel.每个通道重复步骤 2 和步骤 3。5Send an I/O update s

48、ignal. After an I/O update, all channels should output their programmed frequency and/or phase offset value.发送 I/O 更新信号。在 I/O 更新后，所有通道应输出其编程频率和 / 或相位偏移值。Single-Tone Mode Matched Pipeline Delay 单音模式匹配管道延迟In single-tone mode, the AD9959 offers matched pipeline delay to the DAC input for all frequency,

49、 phase, and amplitude changes. This avoids having to deal with different pipeline delays between the three input ports for such applications. The feature is enabled by asserting the matched pipe delays active bit found in the channel function register (CFR, Register 0 x03). This feature is available

50、 in single-tone mode only在单频模式， 对于 DAC输入的所有频率， 相位和振幅的变化提供相匹配的 AD9959管道延 迟。这避免了此类应用处理这些三个输入端口之间的不同管道延迟。该功能是通过维持在通 道功能寄存器（ CFR，寄存器 0 x03）中的匹配管道延迟活动位实现。此功能仅适用于单音模 式。REFERENCE CLOCK MOD参E考S 时钟模式The AD9959 supports multiple reference clock configurations to generate the internal system clock.As an altern

51、ative to clocking the part directly with a high frequency clock source, the system clock canbe generated using the internal, PLL-based reference clock multiplier. An on-chip oscillator circuit isalso available for providing a low frequency reference signal by connecting a crystal to the clock inputp

52、ins. Enabling these features allows the part to operate with a low frequency clock source and still provide a high update rate for the DDS and DAC. However, using the clock multiplier changes the output phase noise characteristics. For best phase noise performance, a clean, stable clock with a high

53、slew is required （see Figure 17 and Figure 18）.AD9959支持参考时钟的多个配置，产生内部的系统时钟。作为一种选择，部件时钟直接 使用一个高频率的时钟源，系统时钟可以使用内部，基于PLL 参考时钟乘法器生成。一个片上振荡器电路也可通过连接晶体的时钟输入引脚，提供一个低频参考信号。启用这些功能， 允许部件操作低频时钟操作源，仍然可以提供一个高更新速率的DDS和数模转换器。然而，要使用时钟乘法器改变输出相位噪声特性。 对于最佳相位噪声性能， 高转换速率时一个干净， 稳定的时钟是必需的（见图 17图 18）。SCALABLE DAC REFERENCE

54、 CURRENT CONTROL可 M缩OD放E DAC参考电流控制模式RSET is common to all four DACs. As a result, the full-scale currents are equal by default. The scalable DAC reference can be used to set the full-scale current of each DAC independent from one another. This is accomplished by using the register bits CFR9:8. Table

55、 5 shows how each DACc an be individuallyscaled for independentchannel control. This scaling provides for binary attenuation.表 5 DAC 满量程电流CFR9:811Full scale 全尺度01Half scale 半尺度10Quarter scale 四分之一尺度00Eighth scale 八分之一尺度RSET是所有四个 DAC共用的。其结果是，满量程电流在缺省情况下相等。可缩放DAC参考用于设置每个 DAC独立的满量程电流。这是通过使用寄存器位 CFR 9:8

56、 完成。表 5显示了如何让每个 DAC可以单独缩放独立的信道控制。这个缩放提供二进制衰减。Table 5. DAC Full-Scale CurrentLSB Current State LSB 的当前状态POWER-DOWN FUNCTIO断N电S功能The AD9959 supports an externally controlled power-down feature and the more common software programmable power-down bits found in previous Analog Devices DDS products. The

57、software control power-down allows the input clock circuitry, the DAC, and the digital logic (for each separate channel) to be individually powered down via unique control bits (CFR7:6). These bits are not active when the externally controlled power-down pin (PWR_DWN_CTL) is high. When the input pin

58、, PWR_DWN_CTL, is high, the AD9959 enters a power-down mode based on the FR16 bit. When the PWR_DWN_CinTpLu t pin is low, the external power-down control is inactive. WhenF R16 = 0 and the PWR_DWN_CTL input pin is high, the AD9959 is put into a fast recovery power-down mode. In this mode, the digita

59、l logic and the DACd igital logic are powered down. The DAC bias circuitry, PLL, oscillator, and clock input circuitry are not powered down.AD9959 支持外部控制的断电功能和更常见的软件可编程断电位，同AD公司以前的 DDS产品。软件控制关机通过唯一的控制位（ CFR 7：6 ）允许输入时钟电路， DAC，和数字逻 辑（每个单独的通道）被单独断电。这些位不活跃，当外部控制电源关引脚（pwr_dwn_ctl ） 高时。当输入引脚， pwr_dwn_ctl

60、 ，高时， AD9959基于 FR1 6 位模式进入断电模式。当 pwr_dwn_ctl 输入引脚低， 外部电源关断控制处于非活动状态。 当 FR1 6 = 0，pwr_dwn_ctl 输入引脚为高， AD9959进入掉电快速恢复模式。在这种模式下，数字逻辑和 DAC数字逻辑断电。 DAC偏置电路，锁相环，振荡器和时钟输入电路没有断电。When FR16 = 1 and the PWR_DWN_CTL input pin is high, the AD9959 is put intofull power-down mode. In this mode, all functions are po