SMT高級工程師教案---設計、製程及可靠度設計、製程及可靠度

1、SMT 高级工程师教案4ADVANCED IC PACKAGNING(BGA，CSP，FLIP-CHIP)设计、制程及可靠度ICPackagingMarketSegmentType199719981999200020012002CAGR%DIP11,1089,4658,7057,8847,2026,631-9.80SO32,93734,57239,14942,96847,39652,1149.62CC3,8013,7624,0324,2494,4134,7114.39QFP6,0367,0638,1839,31410,72212,43815.56PGA293284273267273282-0.

2、77BGA9301,6512,7203,9145,2436,75548.67CSP1585541,4942,8694,4306,144107.98DCA3,0743,5234,1604,7475,3085,81413.59Total58,33760,87568,72576,21284,98994,91910.23BGA & CSP800060004000200001997 1998 1999 2000 2001 2002year-BGA-CSPamountSource：Electronic Trend SMT Magazine,July,1998 Millions of unitsForeca

3、stGrowthandBreakdownElectronics marketIC shipments IC package shipmentsBGA-style packagesFew Chip BGA packages5%Forecast growth10%Rates(1997-2002)26%49%150%BillionIC package style breakdown(year 2001 for forecast)3025 20 151050SOIC QFP/PLCC BGA/CSP DIPS COB/DCA PGA/SIP TABSource:Prismark PathersChan

4、gingRelationshipswithinthe ElectronicsIndustrysubstrate suppliersSystems electronics firmsIC/ASICvendorsASICdosignerlayoutpackaging suppliersYesterdayPCBlogic designsubstrate suppliersmfgIC/ASICvendorspackaging suppliersASICpcakage designASICdesignerPCBToday!layout outsourcemfgSystems electronics fi

5、rmsdesigInterconnectTechnology-Wirebondovermoldwirebondslayer3layer2 layer1dieviassubstratelayer1layer2Solder ballsInterconnectTechnology-FlipChip Wirebond yield 100PPM:-98% yield for 200 I/O-90% yield for 1000 I/O High speed-Inductance 0.1nH(vs.0.5 to 2.8nH) High I/O-Die size Defect Density & Costd

6、ie underfillencapsulationbumped die padsMulti-layer substratelaser-drilled viasSolderTypesofPackages-PBGA Cavity up 2 to 6 routing layers Injection molded Heat conducted to PCB directly under die，Dieusing conductive vias Relatively unchanged 1.27MM pitch Mask Defined vs.Metal Defined256-600 I/OSubst

7、rateBallsEncapsulationTypesofPackages-S,T,VBGA Cavity down 1 routing layer Metal top,glob-top encapsulation Heat channeled directly to convectively cooled surface using conductive vias or cavity 1MM pitch Multilayer-electrically enhanced Laser / micro vias Up to 900 I/O Direct attach to heat spreade

8、rSubstrateThermal ViasHeat SpreaderBallsDieEncapsulationTypesofPackages-CSP 20%larger than IC Typically 100 I/O DRAM and flash memory DSPs,ASICs,microcontrollers-Digital camcorders,notebooks,memory cardsMulti-ChipPackages(MCM,FCP) “System in a Package” Cavity up 2 to 4 die 2 to 6 routing layersStand

9、ardDataFormatsBGADESIGNBGANetlist DataAnalysis ToolsOld DesignsTechnology FilesMechanical CADICDesignGDSII ASCII DIEGDSII DXF IDFASCIIDESIGNASCII DXFASCIIExcelLibraryCreation Standard data formats-DIE format,GDSII,DXF,ASCII-JEDEC,standard naming no I,O,Q,S,X,Z naming for BallNetManagementfixed?free?

10、Define Source and Target ?Get the ResultDesignRules Placement rules Wirebond rules Escape rules Interconnect rules Same net rules Area rules Signal integrity rules Plating rulesWireBonding Single/Multiplerowbond fingers-orthogonal-arc-stagger-complexViaFanoutBallViaTraceRouting(I)TraceRouting(II)Are

11、aFill(PolygonalMetal)PlatingBar&TraceSolderMaskMetalEtchAdvisorElectricalAdvisorTheLinkageofICPackage1.I/O buffer2.wirebond3.bond finger5.via to package Pin/ball7.to next Package pin,through package and to IC6.trace on PCB4.trace onBGA substrateICAdvanced IC PackageWhere/WhatisPackagesRole How much

12、time you could bargain? Delay percentage(system view)-Interconnect delay:40%Chip delay45%Interconnectdelay40%-Package delay:15%-Chip delay:45%Package delay 15%ImpedancdControl ThecharacteristicImpedance-usually from 3070-if ，over shoot will be double-if zero，under shoot will minus oneElectricalDesig

13、nChallenges(I) Topology-Daisy chain，branch，staretc topology-Stub & wrong way length control Via Control-Effective length of via-Max.vias per net-Max.vias per connection Length Rules-Net length control-Delay RulesElectricalDesignChallenges(II) BranchMatchedLengths-define min length and max length-def

14、ine tolerance and via Control Couplingnoisecontrol-Same layer parallel coupling-Adjacent layer coupling(Tandem)-Coupling noise is an accumulated ElectricalDesignChallenges(III) Avoidinghighspeedtracesroutedoveracutplane Breakouttheaccumulationwhiletheparallelhappened TraceshieldingCut planeGND shiel

15、dingElectricalDesignTrade-off(System)System ImpedanceCoupling NoiseLoad ReflectionLoaded DelayL di/dt NoiseLargerLargerLargerSmallerSmallerSmallerSmallerLargerNoise (Volts)0.50.252040506080100FinalizetheDesignSystemcharacteristicimpedance(ohms)ManufacturingPreparation-NamingballsandfingersManufactur

16、ingPreparation-SrtipandDocumentationOutputFiles&Reports Gerberfiles Drillfiles-by Layer-by Extents DXFfiles GDSIIfiles ASCIIreport-Netlist-wirebonding-component-Technology data Draftprint-HP-GL/2-PostScript-Window based printerOn-LineandPostAnalysisProcessFlowofDesigntoManufacturingGERBER FILESCADSy

17、stemGERBER FILES底片LASERPhotoUpdated GERBER FILESCAMSystem(工作片)Your BoardFabricationHouse1. 即時檢查 Gerber files，以避免錯之發生及往返奔波修正之苦2. 適切的編修，可補 CAD 作業之瓶頸，以提升 PCB 及 Substrate 品質4.因應製程需要，製作工作底片，發揮經濟規模，藉以降低成本5.運用電腦輔助製造(CAM)工具，以精確產生電腦數值控制(CNC)資料Over/UnderSize-CangenerateSoldermaskOver/UnderSize-Canreducetheare

18、aofPowerPlaneRemoveIsolatedPads-CanremovetheisolatedpadsofInternallayerTearDrop(淚滴)Layer(data)Composite；正負Layer(data)Composite正負正DFMAnalysis-OverEtchingSignal traceDFMAnalysis-CopperSilvercopperpadpadDFMAnalysis-MaskSilvermetal dataMask dataDFMAnalysis-SolderBridgemask dataDFMAnalysis-StarvedThermal

19、Thermal padcoppercopperDFMAnalysis-CopperArea(銅箔面積)Panelization(排版)SortDrillholes(鑽孔排序)A3D-simulatorofPackagingAtypicalBGAdesignBondingdiagramA6-layerdesignAnMCMdesign附錄：半導體製作流程(I) 晶圓晶圓的生產由砂即(二氧化矽)開始，經由電弧爐的提煉還原成治煉級的矽，再經由鹽酸氯化，產生三氯化矽，經蒸餾純化候， 透過慢速分解過程，製成棒狀或粒狀之多晶矽。一般晶圓製造廠，半導體的製作過程是一項科技高度整合的作業，結合了化學、物理、電

20、子、電機、機械、自動化、軟體工程、電腦輔助設計(CAE/CAD)等、幾乎所有頂尖的技術都被用來製造半導體將多晶矽融解後，再利用矽晶種慢慢拉出單晶矽晶棒。一般晶圓製造廠，一支 85 公分，重 76.6 公斤的 8 吋矽晶棒，約需 2 天半時間長成。經研磨、拋光、切片後、即成半導之原料晶圓片。黃光黃光：IC 製程是不斷的重覆光學顯影、蝕刻、及薄膜沉積等步驟。光學顯影是在光阻上經過曝光和顯影的程序，把光罩上的圖形轉換到光阻下面的薄膜層或矽晶上。光學顯影 主要包含了光阻塗佈、烘烤、光罩對準、曝光和顯影等程序。小尺寸之顯像解析度，更在IC 製程的進步上，扮演著最關鍵的角色。由於光學上的需要，此段製程之照

21、明採用偏黃色的可見光。因此俗稱此區為黃光區。蝕刻蝕刻顧名思義，蝕刻便是將晶圓上的某一部份物質移去，乾式蝕刻或一般所謂的乾式電漿蝕刻，是常來製造半導體的技術，在氣態狀況下採用的蝕刻化學通常呈現電漿狀況。乾式蝕刻晶圓經過曝光的部份要移除，利用蝕刻的方法可以非常精密的達成任務!而保留下來的部份即為有作用的線路。電漿蝕刻產生電漿的目的是讓氣體透過電場解離，而產生具反應性及方向性之離子，進入化學反應器加速蝕刻，因此使用者能夠在蝕刻過程中控制其變化，以獲得近乎完美的蝕刻結果化學氣相沉積早期在半導體製作工程上皆應用磊晶技術，經過多年的發展，應用材料公司研究有關氣相沉積技術以在晶圓表面沈澱出絕緣膜、氮化矽、氧

22、化矽及其它非磊晶薄膜。在化學氣相沉積製程中，氣體存在物質微粒中，在可控制的製作環境中，被排擠到表面，介質層、金屬間電介質層，以及護層。近年來鎢的運用也在快速成長電。經由熱及電場能量在晶圓的表面形成薄膜。應用化學氣相沉積技術所產生的薄膜僅有幾毫微米的厚度，而且完全均勻，這項技術愈來愈廣泛地應用在半導體制程中。常見的化學氣相沉積膜有：氧化矽、氮化矽、多晶矽及金屬矽化合物。隨著技術的發展，今日應用最廣泛的化學氣相沉積膜為氧化矽及絕緣氮化矽，這些物質來自晶片中三個主要絕緣層一隔層附錄：半導體製作流程(II)化學氣相沉積離子植入ION-IMPLANTN+離子植入在離子植入製程中一般應用的離子束是由元素混

23、合物和某一元素所產生，利用離子束可以非常精確的控制半導體晶片中的電流。當離子束加速到某一能量位階，此時其速度可以穿透半導 體的晶狀結構，到達某特定位置，使得晶片在所需要的區域內元件，可以精確集中地沈積。離子元件的集中程度是由晶片透過離子光線的次數或者是離子光線的掃描頻率來決定。物理氣相沉積PHYSICAL VAPOR DEPOSITION物理氣相沉積如同化學氣相沉積的過程，利用物理氣相沉積技術在高真空中的純物質(矽晶)表面上，噴出鋁或其它金屬，以沉積成薄膜。這項在高真空室內進行的製程，可以讓微粒相互結合獲得純金屬。化學機械式磨平機CHEMICAL MECHANICAL POLISH化學機械式研

24、磨法是表面平坦化技術的一種，由 IBM 公司研發而成，是把隨晶片表面起伏的介電層外觀加以全面平坦的一項技術。它利用機械式的研磨原理，配合適當的研漿，來把晶片表面高低起伏的輪廓一併加以磨平。研漿通常由二氧化鋁和鹼性的氫氧化鉀或氨水等溶液所混合而成。若各種參數控制得宜，化學機械式磨法可提 94%以上的平坦度。切割PACKING切割：晶圓經過所有的製程處理及測試後，切割程壹顆顆的 IC。舉例來說以 0.4 微米製程技術生每片八吋晶圓上可製作近三百顆的十六百萬位元 DRAM。切割PACKING封裝是製程處理的最後一道手續，通常還包含了植晶及打線的過程，後段的測試亦為不可或缺的環節。ISTGeograp

25、hicLocationCompanyBrief1.Business Scope:Provide total solution in IC assembly and testing service including:-Package and technology development.-Electrical test program development.-IC package and electrical test operation2.Paid in Capital：NTD 1.2B (USD 36.36M，1 USD=33.0 NTD)3.Major Shareholder：Comp

26、al Electronics，Inc.China Development Industrial BankTaiwan Industrial Bank4.Factory Location：KEPZ，Kaohsiung City.Space：27,000m 25.Sales Office：Taipei，KaohsiungISTHistory1998 May-Company Start with full experience management team.1998 Sep.-Buy 3 Smart Card Module production line from STP(previous IBM

27、 company) with technology transfer & customer introduction.1998Des.-Start IST building construction with 5 floor,27,000 mspace.1999Jan.-Complete Self-Qualification of Smart Card Module Production line.-1999Fed.Develop MOA2,MCC1,MCC2 for Contactless Module and mass production in Q2.-1999Sept SMC Work

28、ing Sample with 64M bit Flash chip.-2000Feb Developed MMC for flash & mask ROM.1999Fed.-Launch TCP assembly & Testing Project-1999Jun.Oct.Build up TCP assembly andTester production line & sample making-1999Dec. Pass TCP Oualification Test &Japanese Customer Approval.2-2000 Jan. Start TCP Mass Produc

29、tion with 300K pcs / mon Capacity.1999 June-Develop & Release TSSOP 48/56 Assembly and Test production. 1999 Oct-IST Building ready with 1 floor production space.2000 May-Obtain the certification of ISO 9001 for IC Assembly and Test activities. 2000 Jul.Expand 2nd floor production space for TCP expa

30、nsion.PackagingRoadmap/PortfolioFCIP：Flip Chip InPackage01CSP：USOC/QFN/LGA/MAPBGA/F BGA001998TSOP/ (L)(T)/ QFPCOF TCP&MCP：Multi Chip PackageTE：Thermal EnhancedWaferTag/99TSSOPSmart LabelMMC/SMCSmart Card 50%LeadframeFilm base：Capacity&Qffering-SmartCardPackageProductsAvailableRamp up to Q2 2001IC Ca

31、rd ModuleSmart Media Card Multi Media Card3000 k/month200 k/month200 k/month6000 k/month600 k/month1800 k/monthTeam up solution for Customers：-Provide wide product range for different application and co-development with customer for special product-Apply A1.wire bonding for lowest loop height(4580um

32、)LCDDriverICModuleMilestones TCPCOF COF module Total thickness：600 um Inner Lead Pitch：30 umWith devics holePassive components integrated Application：driver IC STNTotal thickness：900 um Inner Lead Pitch：45 umWith device hole Application：driver IC TFT,STNTotal thickness：600 um Inner Lead Pitch：30 umW

33、ithout device hole Application：driver ICICCardPackageMilestonesCapacityPlan-DriverICPackagel Ramp upl LIBPitch 45 / 50 /60 / 70 m Tape width 35 / 48 /70 mm Wafer size 5” / 6” / 8”l 5500 k /monthl 7500 k /month availableQ1 2001l 7500 k /month Q1 2001l Wafer & final test5” / 6” /8” normal / bumped waf

34、er Pitch 45 / 50 / 60 / 70m Min.pad width 30ml 5500 k /month availablel Chip SorterDie size 0.5 20 mm Tray size 2” / 3” 4”l 750 k /month availablel 3.0M /month Q1 2001ICCardModuleOverviewModukeSpecCF64CF83CF83-1CF84CF84-1CF84-2BF83BF84Pitch9.5mm14.25mm14.25mm14.25mm14.25mm14.25mm14.25mm14.25mmDimens

35、ion7.82x10.42mm11.8x13.0mm11.8x13.0mm11.8x13.0mm11.8x13.0mm11.8x13.0mm11.8x13.0mm11.8x13.0mmThickness0.56mm0.46mm0.46mm0.56mm0.56mm0.56mm0.46mm0.56mmMold dimension6.1x6.1mm7.7x7.8mm7.7x7.8mm7.7x7.8mm7.7x7.8mm7.7x8.6mm7.2x6.8mm7.7x7.8mmModule SpecIOA2ICC1ICC2-1ICC2-2LF03LF03-1TAGSmart LabelPitch9.5mm

36、9.5mm4.75mm4.75mm9.5mm14.25mm19.0mmTBFDimension8.0x5.0mm7.55x11.75mm2.93x10.3mm2.93x10.3mm7.75x11.95mm11.8x3.0mm17.0x27.6mmTBFThicness0.4mm0.4mm0.33mm0.33mm0.46mm0.46mm0.56mm0.5mmMold dimension5.1x4.9mm6.8x4.8mm2.93x5.1mm2.93x5.1mm6.8x4.8mm6.64x6.14mm14.0x20.0mmFlip ChipChip capacitor/ ApplicationAp

37、plicableApplicableNot ApplicableNot ApplicableApplicableNot ApplicableID,LaundryI-Code,MifareMemoryCardProductMulti Media CardApplication MP3 Cellular Phone Digital Video Card Specification3Card sizSmart Media CardApplication Digital Still Camers Voice Recorder MP3 Card Specification337.00x45.00x0.7

38、6mmPlastic MaterialPCPacking on TrayPlastic MaterialPVCCard size Packing on Tray24.00x32.00x1.40mmModule SpecificationModule size3Module sizeModule Specification17.00x27.60x0.56mm 3Chip Dimensions17.20x27.00x0.76mm311.00x17.80x0.3mm (Max)Chip Dimensions37.50x16.80x0.2mm (Max)MemoryCardProductMulti M

39、edia CardApplication MP3 Cellular Phone Digital Video Card SpecificationSmart Media CardApplication Digital Still Camers Voice Recorder MP3 Card SpecificationCard size3Card siz337.00x45.00x0.76mm24.00x32.00x1.40mmPacking on TrayPacking on TrayWorldwideTFTLCDMarketingForecastUnit:100Million1361531161

40、0297185200150100500199719981999200020012002Source：Display Search,1999/8TCPManufacturingTechnology&SpecProcessManu.technologySpecificationWafer testDicingChip sorterorILB bondingSpecific driver IC tester,BeCu/ReW probe pinStep cutting,UV foil 2”/3”4”tray,6”/8” wafer45um pitch,6/8 waferElimination of

41、off-grade electrical characteristics Min.pad width 30 um characteristicsLine width Min.80 um,chipping10 um Tray X/Y+0.3mm,Place accuracy2g,pass peel off testPottingDispensing type,post curingCoating Dim.+0/-4mm,Resin strength1.5&0.5kgMarking Final testAppearance checkLaser markingSpecific driver IC

42、tester,BeCu/ReW probe pin Inspection+reject punchMin./Typ.Char.Size 0.3/0.4mmElimination of off-grade electricalcharacteristicsTape/lead form/marking/potting quality evaluationPackingVacuum sealingA1.Bag with vacuum and N filled 2WaferTestManu.technologySpecificationSpecific driver IC tester,BecuEli

43、mination of off-grade electrical characteristics/ReW probe pinMin.pad width 30 umAvailableequipmentAdvantest tester & TSK proberDicingManu.technologySpecificationStep cutting,UV foilLine width Min.80 um,chipping 10umAvailableequipmentDisco dicing machineChipSortManu.technologySpecification2”/3”/4” t

44、ray,6”/8” waferTray X/Y+0.3mm,Place accuracy 2g,pass peel off testAvailableequipmentShibaura ILB bonderPottingManu.technologySpecificationDispensing type,post curingCoating Dim. +0/-4mm,Resin strength 1.5 & 0.5kgAvailableequipmentMisuzu FA pottingMarkingManu.technologySpecificationLaser markingMin./Typ.Char.Size 0.3/0.4mmAvailableequipmentSAMPLEMisuzu FA laser markerFinaltestingManu.technologySpecificationSpecific driver IC tester,BecuElimination of off-grade electri