DLP3000FQB,DLP3000FQB, 规格书,Datasheet 资料

1、DLP3000FQB,DLP3000FQB, 规格书,Datasheet 资料DLP3000 DLPS022JANUARY2012DLP0.3WVGA Series220DMDCheck for Samples:DLP3000FEATURES0.3-Inch(7.62mm)Diagonal Micromirror ArrayPackage Mates to PANASONIC AXT550224Socket608684Array of Aluminum,Micrometer-Sized MirrorsAPPLICATIONS7.6-m Micromirror PitchMachine Visi

2、on12Micromirror Tilt Angle(Relative to FlatIndustrial InspectionState)3D ScanningSide Illumination for Optimized Efficiency3D Optical Metrology3-s Micromirror Cross Over TimeAutomated Fingerprint IdentificationHighly Efficient in Visible Light(420nm720nm):Face RecognitionWindow Transmission97%(Singl

3、e Pass,Augmented RealityThrough Two Window Surfaces)Embedded DisplayMicromirror Reflectivity88%Interactive DisplayArray Diffraction Efficiency86%Information OverlayArray Fill Factor92%SpectroscopyPolarization IndependentChemical AnalyzersUp to WVGA Resolution(854x480)WideMedical InstrumentsAspect Ra

4、tio DisplayPhoto-StimulationLow Power Consumption,only200mWVirtual Gauges(Typical)15-Bit,Double Data Rate(DDR)Input Data Bus60-MHz to80-MHz Input Data Clock RateIntegrated Micromirror Driver CircuitrySupports10C to70C16.6-mm by7-mm by5-mm Package FootprintDedicated DLPC300Controller for ReliableOper

5、ationDESCRIPTIONThe DLP3000digital micromirror device(DMD)is a digitally controlled MOEMS(micro-opto-electromechanical system)spatial light modulator(SLM).When coupled to an appropriate optical system,the DLP3000can be used to modulate the amplitude,direction,and/or phase of incoming light.The DLP30

6、00creates light patterns with speed,precision,and efficiency.Architecturally,the DLP3000is a latchable,electrical-in/optical-out semiconductor device.This architecture makes the DLP3000well suited for use in applications such as3D scanning or metrology with structured light, augmented reality,micros

7、copy,medical instruments,and spectroscopy.The compact physical size of the DLP3000is well-suited for portable equipment where small form factor and lower cost are important.The compact package compliments the small size of LEDs to enable highly efficient,robust light engines.The DLP3000is one of two

8、 devices in the DLP0.3WVGA chipset(see Figure1).Proper function and reliable operation of the DLP3000requires that it be used in conjunction with the DLPC300controller.See the DLP0.3 WVGA Chip-set data sheet(TI literature number DLPZ005)for further details.Figure2shows a typical system application u

9、sing the DLP0.3-inch WVGA chipset.Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.DLP is a registered trademark of Texas Instru

10、ments.PRODUCTION DATA information is current as of publication date.Copyright2012,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does notnecessarily include testing of all parameters.芯天下-VCC VSSDLP3000DL

11、PS022JANUARY 2012Figure 1.DLP 0.3WVGA Chip Set2Submit Documentation FeedbackCopyright 2012,Texas Instruments IncorporatedProduct Folder Link(s):DLP3000芯天下-I 2DLP3000DLPS022JANUARY 2012Figure 2.Typical ApplicationElectrically,the DLP3000consists of a two-dimensional array of 1-bit CMOS memory cells,o

12、rganized in a grid of 608memory cell columns by 684memory cell rows.The CMOS memory array is addressed on column-by-column basis,over a 15-bit double data rate (DDR)bus.Addressing is handled via a serial control bus.The specific CMOS memory access protocol is handled by the DLPC300digital controller

13、.Optically,the DLP3000consists of 415,872highly reflective,digitally switchable,micrometer-sized mirrors (micromirrors)organized in a two-dimensional array.The micromirror array consists of 608micromirror columns by 684micromirror rows in diamond pixel configuration (Figure 3).Due to the diamond pix

14、el configuration,the columns of each odd row are offset by half a pixel from the columns of the even row.Each aluminum micromirror is approximately 7.6microns in size (see Micromirror Pitch in Figure 3),and is switchable between two discrete angular positions:12and +12.The angular positions are meas

15、ured relative to a 0flat reference when the mirrors are parked in their inactive state ,parallel to the array plane (see Figure 4).The tilt direction is perpendicular to the hinge-axis.The on-state landed position is directed toward the left side of the package (see DLP3000Active Mirror Array ,Micro

16、mirror Pitch ,and Micromirror Hinge-Axis Orientation in Figure 3).Each individual micromirror is positioned over a corresponding CMOS memory cell.The angular position of a specific micromirror is determined by the binary state (logic 0or 1)of the corresponding CMOS memory cell contents,after the mir

17、ror clocking pulse is applied.The angular position (12or +12)of the individual micromirrors changes synchronously with a micromirror clocking pulse,rather than being coincident with the CMOS memory cell data update.Therefore,writing a logic 1into a memory cell followed by a mirror clocking pulse res

18、ults in the corresponding micromirror switching to a +12position.Writing a logic 0into a memory cell followed by a mirror clocking pulse results in the corresponding micromirror switching to a 12position.Copyright 2012,Texas Instruments Incorporated Submit Documentation Feedback3Product Folder Link(

19、s):DLP3000芯天下-DLP3000DLPS022 Updating the angular position of the micromirror array consists of two steps.First,updating the contents of the CMOS memory.Second,application of a mirror reset to all or a portion of the micromirror array(depending upon the configuration of the system).Mirror reset puls

20、es are generated internally by the DLP3000DMD,with application of the pulses being coordinated by the DLPC300controller.See SWITCHING CHARACTERISTICS timing specifications.Around the perimeter of the608684array of micromirrors is a uniform band of border micromirrors.The border micromirrors are not

21、user-addressable.The border micromirrors land in the12position once power has been applied to the device.There are10border micromirrors on each side of the608by684active array.4Submit Documentation Feedback Copyright2012,Texas Instruments IncorporatedProduct Folder Link(s):DLP3000芯天下-I n c i d e n t

22、 I l l u m i n a t i o nDLP3000DLPS022JANUARY 2012Figure 3.Micromirror Array,Pitch,and Hinge-Axis OrientationCopyright 2012,Texas Instruments IncorporatedSubmit Documentation Feedback5Product Folder Link(s):DLP3000芯天下-a b a bDLP3000DLPS022JANUARY Figure 4.Micromirror Landed Positions and Light Paths

23、6Submit Documentation FeedbackCopyright 2012,Texas Instruments IncorporatedProduct Folder Link(s):DLP3000芯天下-DLP3000FQBPackage TypeDevice DescriptorDLP3000 DLPS022JANUARY2012 Related DocumentsThe following documents contain additional information related to the use of the DLP3000device:Table1.Relate

24、d DocumentsTI LITERATUREDOCUMENTNUMBERDLP0.3WVGA Chipset data sheet DLPZ005DLPC300Digital Controller data sheet DLPS023DLPC300Software Programmers Guide DLPU004Device Part Number NomenclatureFigure5provides a legend for reading the complete device name for any DLP device.Figure5.Device NomenclatureD

25、evice MarkingThe device marking consists of the fields shown in Figure6.Figure6.Device MarkingDevice TerminalsThis section describes the input/output characteristics of signals that interface to the DLP3000,organized by functional groups.Table2includes I/O,Type,Internal Termination,Clock Domain,and

26、Data Rate characteristics which are further described in subsequent sections.Copyright2012,Texas Instruments Incorporated Submit Documentation Feedback7Product Folder Link(s):DLP3000芯天下-DLP3000DLPS022Figure7.Package Connector Signal Names(Device Bottom View)8Submit Documentation Feedback Copyright20

27、12,Texas Instruments IncorporatedProduct Folder Link(s):DLP3000芯天下-DLP3000 DLPS022JANUARY2012Table2.Connector PinsTERMINAL CONNECTOR INTERNAL CLOCKED DATAI/O/P TYPE DESCRIPTION NAME PINS TERMINATION BY RATEData InputsDATA(0)D2Input LVCMOS None DCLK DDRDATA(1)D4Input LVCMOS None DCLK DDRDATA(2)D5Inpu

28、t LVCMOS None DCLK DDRDATA(3)D6Input LVCMOS None DCLK DDRDATA(4)D8Input LVCMOS None DCLK DDRDATA(5)D10Input LVCMOS None DCLK DDRDATA(6)D12Input LVCMOS None DCLK DDRDATA(7)D14Input LVCMOS None DCLK DDR Input data busDATA(8)E16Input LVCMOS None DCLK DDRDATA(9)E14Input LVCMOS None DCLK DDRDATA(10)E12In

29、put LVCMOS None DCLK DDRDATA(11)E10Input LVCMOS None DCLK DDRDATA(12)E5Input LVCMOS None DCLK DDRDATA(13)E6Input LVCMOS None DCLK DDRDATA(14)E8Input LVCMOS None DCLK DDRDCLK E18Input LVCMOS NoneInput data bus clockData Control InputsLOADB E20Input LVCMOS None DCLK DDR Parallel data load enableTRC E4

30、Input LVCMOS None DCLK DDR Input data toggle rate controlSCTRL E2Input LVCMOS None DCLK DDR Serial control busStepped address control serial bus SAC_BUS E24Input LVCMOS None SAC_CLK DDRdataStepped address control serial bus SAC_CLK D24Input LVCMOS NoneclockMirror Reset Control InputsDRC_BUS D22Input

31、 LVCMOS None SAC_CLK DMD reset-control serial busActive-low output enable signal for DRC_OE D20Input LVCMOS Noneinternal DMD Reset driver circuitryStrobe signal for DMD ResetDRC_STROBE E22Input LVCMOS None SAC_CLKControl inputsPowerVBIAS D16Power Analog NoneMirror reset bias voltageVOFFSET D21Power

32、Analog NoneMirror reset offset voltageVRESET D18Power Analog NoneMirror reset voltagePower supply for double-data-rate VREF E21Power Analog Nonelow-voltage CMOS logic terminalsD1,D13,D25,Power supply for single-data-rate VCC Power Analog NoneE1,E13,E25LVCMOS logic terminalsD3,D7,D9,D11,D15,D17,D19,C

33、ommon return for all power VSS Power Analog NoneD23,E3,E7,inputsE9,E11,E15,E17,E19,E23Copyright2012,Texas Instruments Incorporated Submit Documentation Feedback9Product Folder Link(s):DLP3000芯天下-DLP3000DLPS022Table2.Connector Pins(continued)TERMINAL CONNECTOR INTERNAL CLOCKED DATAI/O/P TYPE DESCRIPT

34、ION NAME PINS TERMINATION BY RATEA3,A5,A7,A9,A11,A13,A15,A17,A19,A21,A23,A25,A27,A29A31,B2,B4,B6,B8,B10,B12,B14,B16,B18,B20,B22,B24,B26,B28,B30,C1,C3,C31,F1,F3,F31,No connection(Any connection to No connect G2,G4,G6,these terminals may result in G8,G10,G12,undesirable effects)G14,G16,G18,G20,G22,G24

35、,G26,G28,G30,H1,H3,H5,H7,H9,H11,H13,H15,H17,H19,H21,H23,H25,H27,H29,H3110Submit Documentation Feedback Copyright2012,Texas Instruments IncorporatedProduct Folder Link(s):DLP3000芯天下-DLP3000 DLPS022JANUARY2012ABSOLUTE MAXIMUM RATINGSover operating free-air temperature range(unless otherwise noted).Str

36、esses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.The Absolute Maximum Ratings are stress ratings only,and functional performance of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implie

37、d.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.PARAMETER CONDITIONS MIN MAX UNIT ElectricalV CC Voltage applied to V CC(1)(2)0.54VV REF Voltage applied to V REF(1)(2)0.54VV OFFSET Voltage applied to V OFFSET(1)(2)(3)0.58.75VV BIAS Voltage applied t

38、o V BIAS(1)(2)(3)0.517VV RESET Voltage applied to V RESET(1)(2)110.5V Supply voltage delta|V BIASV OFFSET|(3)8.75VVoltage applied to all other input terminals(1)0.5V REF+0.3VCurrent required from a high-level output V OH=2.4V20mACurrent required from a low-level output V OL=0.4V15mA EnvironmentalSto

39、rage temperature range(4)(5)-4080CStorage humidity(4)(5)Non-condensing095%RH700nm10 Electrostatic discharge immunity(8)All pins2000V(1)All voltages referenced to V SS(ground).(2)Voltages V CC,V REF,V OFFSET,V BIAS,and V RESET are required for proper DMD operation.(3)Exceeding the recommended allowab

40、le absolute voltage difference between V BIAS and V OFFSET may result in excessive current draw.(4)Optimal,long-term performance of the Digital Micromirror Device(DMD)can be affected by various application parameters,includingillumination spectrum,illumination power density,micromirror landed duty c

41、ycle,ambient temperature(both storage and operating),case temperature,ambient humidity(both storage and operating),and power on/off duty cycle.TI recommends that application-specific effects be considered as early as possible in the design cycle.Contact your local Texas Instruments representative fo

42、r additional information related to optimizing the DMD performance.(5)Simultaneous exposure to high storage temperature and high storage humidity may affect device reliability.(6)Total integrated illumination power density,above or below the indicated wavelength threshold.(7)Limited only by the resu

43、lting array temperature.Refer to the Thermal Characteristics for information related to calculating the micromirrorarray temperature.(8)Tested in accordance with JESD22-A114-B electrostatic discharge(ESD)sensitivity testing,human-body model(HBM).Copyright2012,Texas Instruments Incorporated Submit Do

44、cumentation Feedback11Product Folder Link(s):DLP3000芯天下-DLP3000DLPS022RECOMMENDED OPERATING CONDITIONSover operating free-air temperature range(unless otherwise noted).The functional performance of the device specified in this data sheet is achieved when operating the device within the limits define

45、d by the Recommended Operating Conditions.No level of performance is implied when operating the device above or below the Recommended Operating Conditions limits.PARAMETER CONDITIONS MIN NOM MAX UNIT ElectricalV REF LVCMOS interface supply voltage(1)(2) 1.65 1.8 1.95VV CC LVCMOS logic supply voltage

46、(1)(2) 2.375 2.5 2.625V Mirror electrode and HVCMOS supply voltageV OFFSET8.258.58.75V(1)(2)(3)V BIAS Mirror electrode voltage(1)(2)(3)15.51616.5VV RESET Mirror electrode voltage(1)(2)9.51010.5V Delta supply voltage|V BIASV OFFSET|(3)8.75VV T+Positive-going threshold voltage0.4V REF0.7V REF VV TNega

47、tive-going threshold voltage0.3V REF0.6V REF VV hys Hysteresis voltage(V T+V T)0.1V REF0.4V REF Vf DCLK DCLK clock frequency6080MHz MechanicalStatic load applied to the package electrical45N connector area(4)(5)Static load applied to the DMD mounting area(6)(5)100N EnvironmentalOperating Case Temper

48、ature(7)(8)25COperating Humidity(7)non-condensing50%RH Operating Device Temperature Gradient(9)10COperating Landed Duty-Cycle(7)(10)25%(1)All voltages referenced to V SS(ground)(2)Voltages V CC,V REF,V OFFSET,V BIAS,V RESET are required for proper DMD operation.(3)Exceeding the recommended voltage d

49、ifference between V BIAS and V OFFSET may result in excessive current draw.See the AbsoluteMaximum Ratings for further details.(4)Load should be uniformly distributed across the entire connector area.(5)See Figure8.(6)Load should be uniformly distributed across the three datum-A surfaces.(7)Optimal,

50、long-term performance of the Digital Micromirror Device(DMD)can be affected by various application parameters,includingillumination spectrum,illumination power density,micromirror landed duty cycle,ambient temperature(both storage and operating),case temperature,ambient humidity(both storage and ope

51、rating),and power on/off duty cycle.TI recommends that application-specific effects be considered as early as possible in the design cycle.Contact your local Texas Instruments representative for additional information related to optimizing the DMD performance.(8)Refer to the Thermal Characteristics

52、for the calculation of the micromirror array temperature from the thermal test point TC3shown inFigure15.(9)As measured between any two points on the exterior of the package,or as predicted between any two points inside the micromirrorarray cavity.Refer to the Thermal Characteristics for information related to calculating the micromirror array temperature. (10)Landed Duty-Cyclerefers to the percentage of time an individual micromirror spends landed in one state(+12or-12degrees)versusthe other state(-12or+12degrees).12Submit Documentation Feedback Copyr