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IEEE Vehicle Power and Propulsion Conference (VPPC), September 3-5, 2008, Harbin, China 978-1-4244-1849-7/08/$25.00C2008 IEEE FUNCTIONAL DESIGN OF FPGA IN A BRUSHLESS DC MOTOR SYSTEM BASED ON FPGA AND DSP Dayu Wang *, Kaiping Yu, Hong Guo School of Automation Science and Electrical Engineering, Beijing University of Aeronautics and Astronautics, Beijing, China Email: AbstractBecause of its high performance, brushless DC motors are widely used in motor vehicles. In this paper, according to analysis of present motor control system, a novel hardware structure of motor control system was presented. It is based on Field Programmable Gate Arrays (FPGA) and Digital Signal Processor (DSP). According to the function needed in motor control and the structure feature of FPGA and DSP, the tasks taken by FPGA and DSP were divided. A functional design of FPGA in a brushless DC motor system based on FPGA and DSP was completed by using modular design method. All the function modules are programmed by Very-High-Speed Integrated Circuit Hardware Description Language (VHDL).The function modules implemented in FPGA were introduced in detail. The advantage of the system is its good operational performance and expansibility. The application of FPGA can greatly simplify the design of peripheral circuits and release DSP from tedious operation. The simulation and experiment results verified its validity, and it can also act as an example for the application of FPGA in motor control field. KeywordsMotor control; Field Programmable Gate Arrays; Digital Signal Processor; Brushless DC Motor I. INTRODUCTION At present, brushless DC motors are widely used in motor vehicles. Therefore, the researches on motor control are afforded for more attention. In existing motor control system DSP are widely used. There are two shortcomings in this structure. One is DSP in the system is fixed-point, and it can not complete some more complex control algorithms quickly and accurately. Two is peripheral module in the system is fixed, which can not be modified and it is lack of flexibility 1, 2. In recent years, programmable logic devices have developed rapidly, especially the Field Programmable Gate Arrays (FPGA).It has low power consumption, flexible programming, shorter development cycle, easier to transplant and other advantages 3 .Now FPGA + DSP control scheme is widely used in motor control field. And many valuable researches on it have been done, such as in paper 1, 2, 3, 4. In conventional scheme based on FPGA and DSP, FPGA only takes some relatively simple functions in the whole system. Performance of the FPGA has not been fully exploited and utilized. In paper 3, 4 FPGA only act as a buffer for PWM generation unit of the DSP. In this paper, according to the function needed in motor control and the structure feature of FPGA and DSP, the tasks taken by FPGA and DSP were divided. A functional design of FPGA in a system of brushless DC motor based on FPGA and DSP has been completed. Compared with the conventional DSP+FPGA scheme, in our system more functions was taken by FPGA. And the performance of FPGA was made full use. So DSP can be used in operating complex control algorithm. In this way, resources of FPGA and DSP are configured reasonably. The application of FPGA in motor control system can not only simplify the systems hardware structure, but also increase system flexibility. Therefore the system is particularly suited for the requirements of high-performance motor control system. In functional design of FPGA, we use modularized design with Very-High-Speed Integrated Circuit Hardware Description Language (VHDL).The function taken by FPGA was divided into six functional modules. And each functional module is independent, and it can be tested individually. And then the whole FPGA system is unitized with this functional modules .In this way, the modularized design of the whole system was completed. The design method of each functional module is presented in the following paper. II. HARDWARE STRUCTURE AND FUNCTION DIVIDING A. Hardware structure In controller design, a hardware structure based on FPGA and DSP was used. In power circuit we use Integrated Power Module (IPM) yielded by International Rectifier Corporation. It is an Integrated Power Module developed and optimized for electronic motor control in appliance applications such as washing machines and refrigerators. Plug N Drive technology offers an extremely compact, high performance AC motor-driver in a single isolated package for a very simple design. Hall position sensor is used as rotor position sensor, which also can be used to generate the phase conversion control signal for BLDC motor. A hall current sensor is used to measure DC bus current. B. Function dividing According to the function needed in motor control and the structure feature of FPGA and DSP, the tasks taken by FPGA and DSP were divided. The functions taken by FPGA include: generating the Pulse Width Modulation (PWM) signal, detecting the current signal, calculation of motor rotational speed ，generating the phase conversion control signal, data exchanging between FPGA and DSP, and calculation of current loop. The functions taken by DSP include: calculation of rotational speed loop, IEEE Vehicle Power and Propulsion Conference (VPPC), September 3-5, 2008, Harbin, China receiving speed instruction 5. Hardware architecture and function dividing are shown in Fig.1. Figure 1. Block diagram of hardware architecture and function dividing III. FUNCTION MODULES IMPLEMENTED IN FPGA All the function modules are programmed by Very-High-Speed Integrated Circuit Hardware Description Language (VHDL). FPGA development process is supported by specialized software tools. Typical design flow includes the following steps 6: 1) Design entry: schematic, HDL (Hardware Description Language), waveform, Boolean, with mixed structure options； 2) Compilation and logic optimization； 3) Mapping, place and route； 4) Interactive simulation and timing analysis； 5) Optional floor-planning； 6) Design verification and in-circuit hardware debugging. Each function module is independent, and it can be tested individually. The function modules which have been tested can be used in top entity. In this way, the modularized design of the whole system was completed. A. Generating the PWM signal The principle of generating PWM waveform is shown in Fig.2.Bidirectional counter is used to generate triangular wave. The value of compare register is compared with triangular wave .If the value of compare register is less than the value of triangular wave ,then PWM is 1, else PWM is 0.And a PWM signal is generated in this way. Figure 2. Principle of generating PWM waveform B. A/D sampling control An external A/D converter is controlled by FPGA to measure DC bus current signal generated by hall current sensor. We use ADC10064 yielded by National Semiconductor as A/D converter. The key features of ADC10064: 1) Built-in sample-and-hold; 2) Single +5V supply; 3) 1, 2, or 4-input multiplexer options; 4) typical Conversion time to 10 bits: 600 ns ; 5) Sampling rate: 800 kHz. All this features can meet the requirements of our system. A/D converter timing diagram of ADC10064 is shown in Fig.3.A conversion is initiated by pulling both pins(S/H and RD) low. The A/D converter samples the input voltage and causes the coarse comparators to become active. An internal timer then terminates the coarse conversion and begins the fine conversion. 850 ns after S/H and RD are pull low; INT goes low, indicating that the conversion is completed. Approximately 20 ns later the data appearing on the TRI-STATE output pins will be valid. That data will appear on these pins throughout the conversion, but until INT goes low the data at the output pins will be the result of the previous conversion. We design the A/D conversion controller by using Finite State Machine (FSM).The FSM is compiled according to the A/D converter Timing Diagram of ADC10064 shown in Fig.3.In this system the current sampling rate is set same with PWM carrier frequency. So the current sampling rate is 10 kHz in our system and it can meet requirements of current loop. Figure 3. A/D conversion timing diagrams of ADC10064 C. Generating the electronic switching and commutation control signal Hall position sensor signal is shown in Fig.4.In each electrical cycle, hall position sensor signal can give six codes, 101、100、110、010、011、001.And the six codes are corresponding to six-step commutation states of three-phase BLDC motor. With hall signal, commutation control for BLDC motor is completed by decoding the six codes with FPGA. aHbHcHFigure 4. Hall position sensor signal IEEE Vehicle Power and Propulsion Conference (VPPC), September 3-5, 2008, Harbin, China D. Speed Calculation The hall position signal not only can be used to generate the commutation control signal, but also can be used to calculate speed of BLDC motor. Therefore, a speed calculation algorithm is needed to implement it. As it is well known, the general formula for speed is distance divided by the time. So a timer is needed to extort the speed form Hall position sensors signals. The speed calculation algorithm is based on Hall sensors signals period interval measured with timer. The counter time interval iscT . Accordingly, the motor speed calculation equation: 60()cSpeed rpmcnt T p=(1) Where: 60 is seconds in a minute, cnt is the counter number between two sequential Hall sensors, p is the number of pair of poles. E. Data exchanging between FPGA and DSP In motor control system, high-speed and reliable communication between the DSP and FPGA is required .And we hope hardware structure as simple as possible. So we communication between the DSP and FPGA is achieved through the dual-port RAM. In system design, we not use expanding dual-port RAM, and we achieve a dual-port RAM by using FPGA. A dual-port RAM achieved by FPGA is shown in Fig.5.In this way, the hardware structure of the system is simplified, and reliability of communication is improved. Hardware resources of the system can be taken full of advantage, flexibility of FPGA in hardware design is fully reflected. The dual-port RAM achieved by FPGA can act as expanding memory, and DSP can access it with no latency time. High-speed and reliable communication between the DSP and FPGA is completed by using a dual-port RAM achieved by FPGA. Figure 5. A dual-port RAM achieved by FPGA F. Current Loop Calculation FPGA can only deal with digital signal. Therefore, in current loop control strategy we use incremental digital PI algorithm. Incremental digital PI algorithm with output limit: () () ()ref backek I k I k= （2） 01() ( 1) () ( 1)uk uk q ek q ek=+ + （3） min minmin maxmax max( )() () () ( )uukuuk uk u uk uuuku=（4） Where: ()refI k: reference current value ,the control output of speed loop achieved by DSP; ()backI k: present current feedback value; e(k):present error of current value; e(k-1):previous error of current value; u(k):present control output; u(k-1):previous control output. IV. SIMULATION AND EXPERIMENT RESULTS A. Simulation Results To test the system, function simulation and timing simulation are preceded by using Quarussoftware. When motor works in six-step commutation, system simulation waveform is shown in Fig.6.The simulation result of PI calculation module is shown in Figure 7.From simulation results, it can be seen that the design of FPGA is successful. Figure 6. Simulation result of BLDC motor working in six-step commutation Figure 7. Simulation result of PI calculation module B. Experimental Results To test the system, a closed loop control experiment for a BLDC motor is completed by using the system based FPGA and DSP. 10 KHz PWM waveform generated by FPGA is shown in Fig.8. Step response of 0.5A current is IEEE Vehicle Power and Propulsion Conference (VPPC), September 3-5, 2008, Harbin, China shown in Fig.9. Step response of 500 rpm speed is shown in Fig.10. Figure 8. 10 KHz PWM signal generated by FPGA Figure 9. Step response of 0.5A current Figure 10. Step response of 500 rpm speed From experimental results, it can be seen that closed loop speed control system based on FPGA and DSP can achieve constant speed. Achieved results verify that functional design of FPGA is successful. And this system can complete the closed loop control for BLDC motor. V. CONCLUSION In this paper, a functional design of FPGA in a system of brushless dc motor based on FPGA and DSP has been completed. The application of FPGA can deeply simplify the design of peripheral circuits and release DSP from tedious control operation. DSP can be used in operating complex control arithmetic. And it can make full use of high-speed data processing ability of the DSP. In this way, resource of FPGA and DSP are both configured in reason, and make this system with great flexibility and good real-time control ability. The