序列检测器的设计 实验报告

1、EDA实验报告书 姓名xxx 学号xxxxxxx 实验时间课题名称序列检测器的设计实验目的1.用状态机实现序列检测器的设计2.了解一般状态机的设计与应用设计要求1.采用VHDL语言设计序列检测器，具体要求如下：（1）检测序列为“10101110”。该序列从左到右依次进入检测器，如果检测到完整序列，检测器输出为1，反之输出为0。（2）利用Quatus II软件生成状态转移图。（3）对该检测器进行仿真，得到仿真波形。2.采用状态图编辑方法设计序列检测器，检测序列为“11010101”。具体要求为（1）对电路进行仿真，得到仿真波形。（2）将该电路图转化成VHDL语言形式。设计思路序列检测器可用于检测

2、一组或多组由二进制码组成的脉冲序列信号，当序列检测器连续收到一组串行二进制码后，如果这组码与检测器中预先设置的码相同,则输出为1，否则输出为0.由于这种检测的关键在于正确码的收到必须是连续的，这就要求检测器必须记住前一次的正确码及正确序列，直到在连续的检测中所收到的每一位码都与预置数的对应码相同。在检测过程中，任何一位不相等都将回到初始状态重新检测。设计原理图及源程序LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;ENTITY AA ISPORT ( CLK ,DIN,RST : IN STD_LOGIC; SOUT : OUT STD_LOGIC;END

3、AA;ARCHITECTURE behav OF AA IS TYPE states IS (s0, s1, s2, s3,s4,s5,s6,s7,s8); SIGNAL ST,NST : states :=s0 ; BEGIN COM : PROCESS(ST,DIN) BEGIN CASE ST IS WHEN s0 = IF DIN = 1 THEN NST = s1;ELSE NST IF DIN = 0 THEN NST = s2;ELSE NST IF DIN = 1 THEN NST = s3;ELSE NST IF DIN = 0 THEN NST = s4;ELSE NST

4、IF DIN = 1 THEN NST = s5;ELSE NST IF DIN = 1 THEN NST = s6;ELSE NST IF DIN = 1 THEN NST = s7;ELSE NST IF DIN = 0 THEN NST = s8;ELSE NST IF DIN = 0 THEN NST = s2;ELSE NST NST = st0; END CASE ; END PROCESS; REG: PROCESS (CLK,RST) BEGIN IF RST=1 THEN ST=s0; ELSIF ( CLKEVENT AND CLK=1) THEN ST=NST; END

5、IF; END PROCESS REG; SOUT=1WHEN ST=s8 ELSE 0 ;END behav;仿真波形图实验结果LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY SM1 IS PORT ( clock : IN STD_LOGIC; reset : IN STD_LOGIC := 0; input1 : IN STD_LOGIC := 0; input2 : IN STD_LOGIC := 0; output1 : OUT STD_LOGIC );END SM1;ARCHITECTURE BEHAVIOR OF SM1 IS TY

6、PE type_fstate IS (st1,st2,st3,st4,st5,st6,st7,st8,st0); SIGNAL fstate : type_fstate; SIGNAL reg_fstate : type_fstate;BEGIN PROCESS (clock,reset,reg_fstate) BEGIN IF (reset=1) THEN fstate = st1; ELSIF (clock=1 AND clockevent) THEN fstate = reg_fstate; END IF; END PROCESS; PROCESS (fstate,input1,inpu

7、t2) BEGIN output1 IF (input1 = 1) AND (input2 = 1) THEN reg_fstate = st2; ELSE reg_fstate = st0; END IF; output1 IF (input1 = 1) AND (input2 = 1) THEN reg_fstate = st3; ELSE reg_fstate = st0; END IF; output1 IF (input1 = 1) AND (input2 = 1) THEN reg_fstate = st4; ELSE reg_fstate = st0; END IF; outpu

8、t1 IF (input1 = 1) AND (input2 = 1) THEN reg_fstate = st5; ELSE reg_fstate = st0; END IF; output1 IF (input1 = 1) AND (input2 = 1) THEN reg_fstate = st6; ELSE reg_fstate = st0; END IF; output1 IF (input1 = 1) AND (input2 = 1) THEN reg_fstate = st7; ELSE reg_fstate = st0; END IF; output1 IF (input1 =

9、 1) AND (input2 = 1) THEN reg_fstate = st8; ELSE reg_fstate = st0; END IF; output1 IF (input1 = 1) AND (input2 = 1) THEN reg_fstate = st3; ELSE reg_fstate = st0; END IF; output1 IF (input1 = 1) AND (input2 = 1) THEN reg_fstate = st1; ELSE reg_fstate = st0; END IF; output1 output1 = X; report Reach undefined state; END CASE; END PROCESS;END BEHAVIOR;问题讨论1. 利用序列检测器设计简易数字密码锁。先输入一个密码，然后在程序中设定一个你