CMOS制造工艺流程简介

2.1

CMOS制造工艺流程简介

We

will

describe

a

modern

CMOS

process

flow.Process

described

here

requires

16

masksand

>

100

process

steps.1第二章CMOS制备基本流程StagesofICFabrication2•

In

the

simplest

CMOS

technologies,

we

need

to

realizesimply

NMOS

and

PMOS

transistors

forcircuits

like

those

illustrated

below.CMOS

Digital

Gates反相电路或非门：同时输入低电平时才能获得高电平输出3PMOS

and

NMOSwafer

crosssection

afterfabrication2-Level

Metal

CMOS两层互连布线的CMOS4有源器件（MOS、BJT等类似器件），必须在外加适当的偏置电压情况下，器件才能正常工作。对于MOS管，有源区分为源区和漏区，在进行互联之前，两者没有差别。••••••••Choosing

a

SubstrateActive

RegionN

and

P

WellGateTip

or

ExtensionSource

and

DrainContact

and

Local

InterconnectMultilevel

MetalizationProcessing

Phases51

µmPhotoresist40

nmSiO2Choose

the

substrate(type,

orientation,resistivity,

wafer

size)•

Initial

processing: -

Wafer

cleaning -

thermal

oxidation,

H2O

(≈

40

nm,

15

min.

@

900ºC) -

nitride

LPCVD(低压化学气相沉积)

(≈

80

nm@

800ºC)•

Substrate

selection:-moderately

high

resistivity(25-50

ohm-cm)-(100)

orientation-P-

type.80

nmSi3N4Choosing

a

SubstrateSi,(100),PType,25~50Ωcm1st

Mask

Photoresist

•

spinning

and

baking@

100ºC(≈

0.5

-

1.0

µm)62.2有源区的形成•

Photolithography-Mask

#1

pattern

alignmentand

UV

exposure-Rinse

away

non-pattern

PR-Dry

etch

the

Nitride

layer--Plasma

etch

with

FluorineCF4

or

NF4

Plasma-Strip

Photoresist(H2SO4或O2plasma)Active

Area

Definition(主动区)SiO2Si3N4Photoresist7•

Wet

Oxide

(thick

SiO2)-

H2O

(≈

500

nm,90min.

@1000ºC)•

Strip

Nitride

layer

-

Phosophoric

acid(磷酸)

orplasma

etch，选择性问题Field

Oxide

Growth

-

LOCOS:

Local

Oxidation

ofSilicon(局部硅氧化工艺)SiO2Si3N4•

薄的SiO2层，厚的Si3N4层，避免鸟喙(bird’sbeak)的影响8•场区:很厚的氧化层，位于芯片上不做晶体管、电极接触的区域，可以起到隔离晶体管的作用。•

Photolithography(套刻)-

Mask

#2

pattern

alignmentand

UV

exposure•

IonImplantation离子注入

-

B+

ion

bombardmentPenetrate

thin

SiO2

and

fieldSiO2

--反型：半导体表面的少数载流子浓度等于体内的多数载流子浓度时，半导体表面开始反型。-

150-200keV

for

1013cm-2

--

Implantation

Energy

andtotal

dose

adjusted

fordepth

and

concentrationP-well

Fabrication•

Strip

Photoresist-

Rinse

away

non-pattern

PR2.3N阱和P阱的形成SiO2Photoresist9•

Ion

Implantation

-

P+

ion

bombardment-

Penetrate

thin

SiO2

and

field

SiO2-

300-400keV

for

1013cm-2

--

Implantation

Energy

andtotal

dose

adjusted

fordepth

and

concentration•

Strip

PhotoresistN-well

Fabrication•

Photolithography

-Mask

#3

pattern

alignmentand

UV

exposure-

Rinse

away

non-pattern

PR10•

ThermalAnneal(热退火)-

Repair

crystal

lattice

structuredamage

due

to

implantation•

Dry

Furnace

(N2

ambient，防止氧化层生成)

-

Anneal30

min

@

800˚C

orRTA(快速热退火)

10

sec

@

1000˚C-

Drive-in4-6

hours

@

1000

˚C

-

1100

˚CThermal

Anneal

and

Diffusion•

NandPDrive-in(扩散推进)-

Thermal

diffusion

of

dopant

toshallower

than

desired

depth--

Drive-in

is

a

cumulativeprocess!11•

Photolithography

-

Mask

#4

pattern

alignmentand

UV

exposure-

Rinse

away

non-pattern

PR-

B+

ion

bombardment-

50-75keV

for

1-5

×

1012cm-2--

Implantation

Energy

and

total

dose

adjusted

for

depth

and

concentration•

Strip

PhotoresistThreshold

Adjustment,

P-type

NMOS•

Ion

Implantation2.4栅电极的制备开启电压调整12调整之前P阱的掺杂浓度调整时的注入剂量Threshold

Adjustment,

N-type

PMOS•

Photolithography

-

Mask

#5

pattern

alignmentand

UV

exposure-

Rinse

away

non-pattern

PR-

As+

ion

bombardment-

75-100keV

for

1-5

×

1012cm-2--

Implantation

Energy

and

total

dose

adjusted

for

depth

and

concentration•

Strip

Photoresist•

Ion

Implantation13•

Remove

existing

gate

regionoxide•

Furnace

Steps -

Thermal

Anneal-

Oxide

growth

3-5

nm--O2

ambient--0.5-1hour@800°CGate

Oxide

Growth栅极氧化层生长-HF

etch，具有良好的选择性--Dry

Furnace

(N2

ambient)--30

min

@

800˚C14•LPCVD

Deposition

of

Si-

Silane硅烷•

Amorphous

or

polycrystalline

silicon

layer

results

Ion

Implantation -

P+

or

As+

(N+)

implant

dopes

the

poly(typically

5

×

1015

cm-2)

Polysilicon

Gate

Deposition•

0.3-0.5

umSiO2多晶硅薄膜15热分解•

Photolithography

-

Mask

#6

pattern

alignmentand

UV

exposure•

Plasma

Etch

-

Anisotropic

etch各向异性蚀刻

--

Vertical

etch

rate

high

--

Lateral

etch

rate

lowGate

Patterning（栅极的图形化）-

Rinse

away

non-pattern

PR•

Clorine(氯)or

Bromine(溴)

based

forSiO2

selectivity16目标：NMOS器件中的N-注入区PMOS器件中的P-注入区多晶硅栅的两侧形成侧壁隔离层的薄氧化层2.5前端或延伸区(LDD)的形成17LDD:•

Lightly

Doped

Drain(轻掺杂漏)•

Reduce

short

channel

effects

due

to

gate

voltagemagnitudes

and

electric

fields•

Source

and

Drain

must

be

layered

asNMOS:N+N-P

or

PMOS:

P+P-NExtension

(LDD)

Formation

NMOS•

Photolithography

-

Mask

#7

pattern

alignmentand

UV

exposure-

Rinse

away

non-pattern

PR-P+

ion

bombardment-

50keV

for

5

×

1013cm-2•

Strip

Photoresist•

Ion

Implantation18•

Photolithography

•

Mask

#8

pattern

alignment

and

UV

exposure

•

Rinse

away

non-pattern

PR•

Ion

Implantation

•

B+

ion

bombardment

•

50keV

for

5

×

1013cm-2•

Strip

PhotoresistExtension

(LDD)

Formation

PMOS19SiO2

隔离介质层CVDorLPCVDDepositionofSiO2•SilaneandOxygenOr0.5um•Providesspacingbetweengateandsource-drain.SiO2SpacerDeposition20•

Photolithography

•

Mask

#6

oversized

pattern

alignment

and

UV

exposure

•

Rinse

away

non-pattern

PR•

Vertical

etch

rate

high•

Lateral

etch

rate

low•

Strip

PhotoresistAnisotropic

Spacer

Etch•

Plasma

Etch

•

Anisotropic

etch•

Flourine

based21•

Screen

Oxide

Growth•

Thin

SiO2

layer

~10

nm

toscatter

the

implanted

ions•

Photolithography•

Mask

#9

pattern

alignment

and

UV

exposure•

Rinse

away

non-pattern

PR•

Ion

Implantation

•

As+

ion

bombardment

•

75

keV

for

2-4

×

1015cm-2•

Strip

PhotoresistNMOS

Source

and

Drain

Implant2.6源漏区的形成Arsenic•

Reduce

channeling22•

Photolithography•

Mask

#10

pattern

alignment

and

UV

exposure•

Rinse

away

non-pattern

PR•

Ion

Implantation

•

B+

ion

bombardment

•

5-10

keV

for

1-3

×1015cm-2

•

Strip

PhotoresistPMOS

Source

and

Drain

Implant23•

N+

and

P+

Drive-in•

Thermal

diffusion

of

dopant

toshallower

than

desired

depth

•Drive-in

is

a

cumulativeprocess!•

Dry

Furnace

(N2

ambient)

•

Anneal30

min

@

900˚C

orRTA

60

sec

@

1000

˚C

-

1050

˚CTransient

Enhanced

Diffusion

(TED瞬态增强扩散)

•

Higher

than

normal

diffusivity

due

tocrystal

damageThermal

Annealing•ThermalAnneal•Repaircrystallatticestructuredamageduetoimplantation242.7接触与局部互联的形成

Contacts

and

Interconnects•Titaniumsputteringlocalcontacts•ConformalCoatwithSiO2•Planarization•TungstenPlugvias•AluminumMetalDeposition•Repeat–Coat–Planarize–Plug–Metaldeposition25•

HF

etch

to

remove

thin

SiO2

•

Remove

screen

oxide

fromdrain,

source

and

ploy

gateregions

•

Dip(浸)

for

a

few

secondswithHFContact

OpeningsLDDandSidewallstructure•NMOS:LateralN+N-PN-N+•PMOS:LateralP+P-NP-P+26

Titanium

Deposition•

Ti

is

deposited

bysputtering(typically

100

nm).

•

Ti

target

hit

withAr+

ions

in

avacuum

chamber•

The

Ti

is

reacted

in

anN2

ambient•

Forms

TiSi2

and

TiN(typically

1

min

@

600

-700

˚C).•

TiSi2

has

excellentcontact

characteristics(良好的导体)•

TiN

does

not,

but

canbe

used

for

local

wiring(导电材料，短程互连布线)TiSi2TiN27•Photolithography•Mask#11patternalignmentand

UV

exposure•

Rinse

away

non-pattern

PR•

TiN

etch

•

NH4OH:H2O2:H2O(1:1:5)•

Strip

PhotoresistLocal

TiN

InterconnectThermalTreatinAr减小电阻

•1min@800°C28用TiN作为局部互连引线•

Conformal

layer

ofSiO2

is

deposited

byCVD

or

LPCVD(typically

1

µm)•PSG(磷硅玻璃)

or

BPSG(硼磷硅玻璃)•磷：Surface

passivation(表面钝化)•硼：Glass

reflow

forpartialplanarization(加热，令表面平整)•

Chemical

MechanicalPolishing

(CMP化学机械抛光)•Planarize

the

wafersurface平坦化

•Polish

with

high

pHsilicaslurry(硅酸盐研磨浆料)Conformal

Coat

and

Planarize2.8多层金属互连的形成SiO229

表面不平坦带来很多问题,两种解决方法：•

Photolithography•

Mask

#12

pattern

alignmentand

UV

exposure•

Rinse

away

non-pattern

PR•

SiO2

plasma

etch

•

Anisotropic

etch•

Strip

PhotoresistVias

to

1st

Metal30•

选择第一层金属布线需要与下层器件结构形成连接的接触孔位置•

接触孔形成

Via

Deposition

–

Tungsten

Plugs(插头)•

TiN

or

Ti/TiN

barrier

layer粘结层/阻挡层，增强金属与SiO2的粘附性•

Sputtering

or

CVD(few

tens

of

nm)•

CVD

Tungsten

(W)•Chemical

MechanicalPolishing

(CMP)•

Planarize

the

wafersurface•

Polish

with

high

pHsilica

slurry31•

Etch

Contact

Holes(接触孔的蚀刻)or

Line

Trenches(沟道)

•

Fill

etched

regions(蚀刻区的填充)

•

Planarize(平坦化)

–

CMP

process

–

Also

removes

material

that

“overflowed

holes

or

trenches”Damascene

Process大马士革镶嵌工艺32大马士革镶嵌工艺包括：

•

Strip

PhotoresistMetal

#1

Deposition第一层金属布线Photolithography•Mask#13patternalignmentandUVexposure•Rinseawaynon-patternPR•Anisotropicplasmaetch33SiO2Al光刻胶•SputteredAluminum•AlwithsmallamountsofSiandCu-Cureduceselectromigration避免电迁移现象带来的断路

-Si降低接触电阻

Multiple

Metal

Layers•DepositsOxideLayer•CMP•PhotolithographyMask#14•EtchVias•Depositviamaterial•CMP•DepositNextMetalLayer•PhotolithographyMask#15•FinalpassivationlayerofSi3N4isdepositedbyPECVDandpatternedwithMask#16.防止Na+、K+污染和封装中的机械损伤•Finalannealandalloyinforminggas(10%H2inN2)

•30min@400-450°C•形成良好的欧姆接触，降低Si/SiO2界面的电荷34SiO2WTiNSi3N4或SiO2Intel

µprocessor

chip52MB

SRAM

chips

on

a

12”

wafer

•

Photos

of

state-of-the-art

CMOS

chips

(from

Intel

website).

•

90

nm

technology.35Summary

of

Key

ideas•ThischapterservesasanintroductiontoCMOStechnology.•Itprovidesaperspectiveonhowind