jetson 系列移植指南 Jetson-Xavier-NX-and-Jetson-TX2-Series-Interface-Comparison-Migration-Application-Note-v1.0

DA-09708-001_v1.0|April2020

NVIDIAJetsonXavierNXandJetsonTX2SeriesInterfaceComparisonandMigration

ApplicationNote

NVIDIAJetsonXavierNXandJetsonTX2SeriesInterfaceComparisonandMigration

DA-09708-001_v1.0|

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DocumentHistory

DA-09708-001_v1.0

Version

Date

DescriptionofChange

0.9

November6,2019

PreliminaryInformation

1.0

April20,2020

Updated

Figure1,

Figure2,

and

Figure3

Updated

Table1

Addednoteregardingimagesfor

Figure3

and

Figure4

Updated

Table3

toreflectthechangeoflanesusedforPCIeinJetsonXavierNXmoduledesign

Updated“

PCIExpress

”section

Updated“

Camera

”section

TableofContents

NVIDIAJetsonXavierNXandJetsonTX2SeriesInterfaceComparisonandMigration

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Introduction 1

JetsonXavierNXvs.JetsonTX2 2

ModuleInterfaceComparisons 4

FunctionandInterfaceDifferenceDetails 6

On-ModuleWireless 6

SupportedVDD_INVoltageRange 6

MechanicalDifferences 6

USB3.x,PCIExpress,andSATAMapping 9

PCIExpress 10

SATA 10

Ethernet 11

Display 11

DSI 11

eDP,DP,andHDMI 12

Camera 12

SDIOandSDCard 13

Audio 14

I2C 15

UART 16

Debug 17

ListofFigures

NVIDIAJetsonXavierNXandJetsonTX2SeriesInterfaceComparisonandMigration

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Figure1. JetsonTX2BlockDiagram 3

Figure2. JetsonXavierNXBlockDiagram 3

Figure3. JetsonXavierNXvs.JetsonTX2ModuleTop 7

Figure4. JetsonXavierNXvs.JetsonTX2ModuleBottom 8

Figure5. JetsonXavierNXandJetsonTX2PCIeBlockDiagram 10

Figure6. JetsonXavierNXandJetsonTX2EthernetBlockDiagram 11

Figure7. JetsonTX2DSIBlockDiagram 12

Figure8. JetsonXavierNXandJetsonTX2CSIBlockDiagrams 13

Figure9. JetsonXavierNXandJetsonTX2SeriesSDIO/SDCardBlockDiagrams 14

Figure10.JetsonXavierNXandJetsonTX2AudioBlockDiagram 15

Figure11.JetsonXavierNXandJetsonTX2I2CBlockDiagrams 16

Figure12.JetsonXavierNXandJetsonTX2UARTBlockDiagrams 17

ListofTables

Table1. JetsonXavierNXandJetsonTX2FeatureComparison 4

Table2. MechanicalDifferences 6

Table3. JetsonXavierNXUSB3.1,PCIeLaneMappingConfigurations 9

Table4. JetsonTX2USB3.1,PCIe,andSATALaneMapping 9

Table5. eDP,DP,andHDMIDisplaySupport 12

NVIDIAJetsonXavierNXandJetsonTX2SeriesInterfaceComparisonandMigration

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Introduction

ThisapplicationnotecomparesthefeaturesandinterfacessupportedontheNVIDIA®JetsonXavier™NXandJetson™TX2modules.ThisapplicationnotealsodescribesthemigrationpathfordesignersfamiliarwithJetsonTX2todesignacarrierboardforJetsonXavierNXthatwillsupportthefeaturesavailableonJetsonXavierNX.

JetsonXavierNXvs.JetsonTX2

TheJetsonXavierNXandJetsonTX2modulesarenotpincompatiblebutsharemanyofthesamefeatures.ThisapplicationnotedescribesthedifferencestoallowusersfamiliarwithJetsonTX2todesignasimilarcarrierboardforJetsonXavierNX.

ThefollowingfiguresshowtheJetsonXavierNXandJetsonTX2blockdiagrams.Theinterfacesorblocksthataresupportedonlybyoneofthemodulesarehighlightedinred.Theinterfacetypesthataresupportedonbothmodulesbutwherethenumberoflanes/instances,voltagelevel,oraccessisdifferentarehighlightedinmagenta.

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JetsonXavierNXvs.JetsonTX2

Figure1. JetsonTX2BlockDiagram

LPDDR4

TX2:8GB

TX24GB:4GBTX2i:8GB

eMMC

TX2:32GB

TX24GB:16GBTX2i:32GB

PowerSubsystem

PMIC

CPU,GPU/SRAM,

&CORERegsOpenVREG(x3)Power&VoltageMonitors

Thermal

Sensor

TegraX2

AntennaConn.#2

AntennaConn.#1

CAN3x

JTAG

UART5x

CAMMCLK4x

SPI3x

CSI:3x4or6x2

DIGITALSPK

GSYNC_H/V

DIGITALMIC

HPD2x,CEC

I2S4x

(1)DP_AUX/DDC2x

AUDIOMCLK

(e)DP/HDMI2x

DSI,4-lane2x

I2C1x–3.3V(1)

I2C5x–1.8V(1)

(1)PCIex4+x1

2x1+x2

TX2:SDCardorSDIO

TX24GB/TX2i:

SDCardandSDIO

SATA

GBE_MDI

(1)USB3.03x

USB2.03x

VDD_IN

JetsonTX2

TX24GB/TX2i:NoWiFi/Bt

TX2:WiFi/Bt

Gigabit

Ethernet

Note:

1USB3.0,PCIe,andSATAsharelanes.Notallinstancesshownin

Figure1

canbebroughtouttogether.SeetheJetsonTX2OEMProductDesignGuidefordetails.

Figure2. JetsonXavierNXBlockDiagram

LPDDR4x8GB

GigabitEthernet

QSPINOR32MB

PowerSubsystem

PMIC

CPU/GPU&CoreRegs

Power&Voltage

Monitors

Xavier

CAN1x

PWM3x

UART3x

GeneralPurpose

Clocks2x

SPI2x

CAMMCLK2x

DIGITALMIC

CSI:3x4or6x2

I2S2x

AUDIOMCLK

HPD2x,CEC

DP_AUX/DDC2x

I2C3x–3.3V

[E]DP/HDMI2x

eMMC16GB

I2C1x–1.8V

PCIex1+x4

SDCARD/SDIO

USB3.11x

GBE_MDI

USB2.03x

VDD_IN

JetsonXavierNX

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ModuleInterfaceComparisons

Table1liststhekeysystemspecifications,devicesandinterfacesthataresupportedoneithertheJetsonXavierNXortheJetsonTX2module.

Table1. JetsonXavierNXandJetsonTX2FeatureComparison

Feature

JetsonXavierNX

JetsonTX2

SystemSpecificationsandDeviceontheModule

GPU

NVIDIAVolta™architecturewith384NVIDIA®CUDA®coresand48Tensorcores

256CoreNVIDIAMaxwell™(1TFLOPsFP16)

CPU

6-coreNVIDIACarmelArmv8.264-bitCPU

Dual-coreDenver1.564-bitCPUandquad-coreArmA57complex

DLAccelerator

2xNVDLAEngines

NotSupported

VisionAccelerator

7-WayVLIWVisionProcessor

NotSupported

Memory

8GB128-bitLPDDR4x

TX2:8GB128-bitLPDDR4

TX24GB:4GB128-bitLPDDR4TX2i:8GB128-bitLPDDR4

Storage

16GBeMMC

TX2:32GBeMMC5.1

TX24GB:16GBeMMC5.1

TX2i:32GBeMMC5.1

Networking

10/100/1000Mbit

VideoEncode

2x464MP/sec

2x4K@30(HEVC)

6x1080p@60(HEVC)

14x1080p@30(HEVC)

500MP/sec

1x4K@60(HEVC)

3x4K@30(HEVC)

4x1080p@60(HEVC)

8x1080p@30(HEVC)

VideoDecode

2x690MP/sec

2x4K@60(HEVC)

4x4K@30(HEVC)

12x1080p@60(HEVC)

32x1080p@30(HEVC)

1000MP/sec

2x4K@60(HEVC)

4x4K@30(HEVC)

7x1080p@60(HEVC)

20x1080p@30(HEVC)

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ModuleInterfaceComparisons

Feature

JetsonXavierNX

JetsonTX2

SystemSpecificationsandDeviceontheModule

16x1080p@30(H.264)

Camera

14lanes(3x4or6x2)MIPICSI-2D-PHY

(2.5Gb/sperpair)

12lanes(3x4or6x2)MIPICSI-2D-PHY1.2

(2.5Gb/sperpair)

WiFi

Requiresexternalsolution

TX2:Onboard

TX24GB/TX2i:Requiresexternalsolution

Mechanical

69.6mmx45mm260-pinedgeconnector

87mmx50mm400-pinconnector

InputVoltage

5V(nominal)

TX25.5V(min)to19.6V(max)

TX24GB/TX2i:9.0V(min),19.6V(max)

Interfaces

USB2.0

3x

USB3.x(SeeNote1)

1x(3.1)

Upto3x(3.1)

PCIe(SeeNote1)

1x1(Gen3)+1x4(GEN4).x1isRootPortonly.x4hasbothRootPortandEndpointsupport

1x1+1x4or1x2+2x1(Gen2),RootPortonly.

SATA(SeeNote1)

Notsupported

x1

Display

Twomulti-mode(e)DP1.4/HDMI™2.0a

Twomulti-modeDP1.2a/eDP1.4/HDMI2.0a/b.Two1x4DSI(1.5Gbps/lane)

Audio(I2S)

2x

4x

SDIO/SDCard

1xSDCard/SDIO

TX2:1xSDCard/SDIO

TX24GB/TX2i:2xSDCard/SDIO

GigabitEthernet

Supported

I2C

4x

8x(seeNote2)

UART

3x

5x

SPI

2x

3x

JTAG

Notsupported

Broughttomodulepins

Fan

PWMandTachInput

Notes:

SeetheUSB3.0,PCIe,andSATAinterfacemappingcomparisontablesfordetailsonlanesharingforJetsonTX2SeriesModules.

IncludingDP_AUXpinsusedasI2C.

Thereare2displaycontrollers.IfbotharedrivingDSIdisplays,theymustbeatthesameresolution.

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FunctionandInterfaceDifferenceDetails

On-ModuleWireless

JetsonXavierNXaswellasJetsonTX24GBandTX2idonotincludeon-modulewirelessfunctionality.JetsonTX2doessupportWi-FiandBluetooth®.

SupportedVDD_INVoltageRange

JetsonXavierNXrequiresanominalinputvoltageonVDD_INof5V.JetsonTX2supportsaVDD_INrangefrom5.5V(min)to19.6V(max).JetsonTX24GBandTX2isupportaVDD_INrangefrom9.0V(min)to19.6V(max).

MechanicalDifferences

Table2

liststhemechanicaldifferences.

Table2. MechanicalDifferences

Feature

JetsonXavierNX

JetsonTX2

Size

69.9mmx45mm

87mmx50mm

Built-inThermalSolution

None

ThermalTransferPlate(TTP)

ThermalSolutionMounting

4holesinPCBforscrewstopassthroughthermalsolutionandJetsonXavierNXboardtoconnecttoametalbracketbelowmodule.ThermalsolutioncontactsSoC(w/thermalmaterialplacedbetween).

JetsonTX2:4smallthreadedholesintheTTPormainmountingholes.

JetsonTX24GB/TX2i:Mainmountingholesonly.ThermalsolutioncontactsTTP.

FunctionandInterfaceDifferenceDetails

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Figure3. JetsonXavierNXvs.JetsonTX2ModuleTop

JetsonXavierNXTop

45mm

69.9mm

50mm

JetsonTX2Top

87mm

87mm

JetsonTX24GB/TX2iTop

50mm

Figure4. JetsonXavierNXvs.JetsonTX2ModuleBottom

JetsonXavierNXBottom

JetsonTX2Bottom

JetsonTX24GB/TX2iBottom

Note:TheJetsonXavierNXimagesin

Figure3

and

Figure4

aretakenfromthe3DCADSTEPmodelswhichshowonlythe“envelop”viewwhichprovidesthemaximumcomponentheightsbyregioninsteadoftheindividualcomponents.Seethethermaldesignguidesformoredetailedimagesofthemodule.

USB3.x,PCIExpress,andSATAMapping

ThefollowingtablesshowthedifferentoptionsformappingUSB3.x,PCIe,andSATA(JetsonTX2only)tothecommonsetofinterfacepins.

Table3. JetsonXavierNXUSB3.1,PCIeLaneMappingConfigurations

JetsonXavierNXPinNames

PCIe#0,

Lane3

PCIe#0,

Lane2

PCIe#0,

Lane1

PCIe#0,

Lane0

PCIe#1,

Lane0

USBSS

XavierLanes

NVHSLane3

NVHSLane2

NVHSLane1

NVHSLane0

PCIeLane11

Lane1

USB3.1

PCIe

1

1x4+1x1

PCIe#0_3

PCIe#0_2

PCIe#0_1

PCIe#0_0

PCIe#1_0

USB_SS#2

RecommendedUsage

PCIex4connectorordevice(i.e.M.2KeyM)

PCIex1conn.ordevice(i.e.M.2KeyE)

USB3.1

connector,deviceorhub

Table4. JetsonTX2USB3.1,PCIe,andSATALaneMapping

JetsonTX2SeriesPinNames

PEX1

PEX_RFU

PEX2

USB_SS1

PEX0

USB_SS0

(seenote1)

SATA

TegraLanes

Lane0

Lane1

Lane3

Lane2

Lane4

Lane5

Avail.Outputsfromthemodule

Configs

USB3.0

PCIe

SATA

1

0

1x1+1x4

1

PCIe#2_0

PCIe#0_3

PCIe#0_2

PCIe#0_1

PCIe#0_0

SATA

2(CB

Default)

1

1x4

1

PCIe#0_3

PCIe#0_2

PCIe#0_1

PCIe#0_0

USB_SS#0

SATA

3

2

3x1

1

PCIe#2_0

USB_SS#1

PCIe#1_0

USB_SS#2

PCIe#0_0

SATA

4

3

2x1

1

USB_SS#1

PCIe#1_0

USB_SS#2

PCIe#0_0

USB_SS#0

SATA

5

1

2x1+1x2

1

PCIe#2_0

USB_SS#1

PCIe#1_0

PCIe#0_1

PCIe#0_0

SATA

6

2

1x1+1x2

1

USB_SS#1

PCIe#1_0

PCIe#0_1

PCIe#0_0

USB_SS#0

SATA

DefaultUsageonCB(carrierboard)

Unused

X4PCIeConnector

USB3TypeA

SATA

Note:

1. PCIeinterface#2canbebroughttothePEX1pins,orUSB3.0port#1totheUSB_SS0pinsonJetsonmodulesdependingonthesettingofamultiplexoronthemodule.

PCIExpress

JetsonXavierNXsupportstwoPCIeinterfaces.Ax1laneinterfaceandax4laneinterface(canbex2orx1instead)atthemodulepins.JetsonTX2cansupportthesame1x1laneand1x4laneconfigurationor2x1laneand1x2laneinterfaces(Configuration#5in

Table4

)atthemodulepins.JetsonXavierNXsupportsbothRootPortandEndpointoperationonthex4interfaceuptoGen4.Thex1interfacesupportsonlyRootPortandonlyuptoGen3.JetsonTX2onlysupportsRootPortoperationuptoGen2.

Figure5. JetsonXavierNXandJetsonTX2PCIeBlockDiagram

JetsonTX2

JetsonXavierNX

0.22uF

PEX1_REFCLK+PEX1_REFCLK–PEX1_TX+PEX1_TX–

B45

H42

H41

E42

E41

B46

0.1uF

0.1uF

PCIe–SingleLane(Ctrlr#2)or

(USB3.0Ctrlr#0).

UsedforM.2

PCIE0_TX3_NPCIE0_TX3_P

PCIE0_RX3_NPCIE0_RX3_P

156

0.22uF

154

155

157

PCIe#0Lane3

PEX1_RX+

PEX1_RX–

Connectoron

PCIE0_TX2_N

148

0.22uF

Mux

USB_SS0_TX+USB_SS0_TX–USB_SS0_RX+

F44

F43

C44

C43

USB3.0(Ctrlr#1)

CarrierBoard

PCIE0_TX2_P

PCIE0_RX2_NPCIE0_RX2_P

0.22uF

150

149

151

PCIe#0Lane2

Mux

USB_SS0_RX–

PEX0_REFCLK+PEX0_REFCLK–

PEX_RFU_TX+PEX_RFU_TX–PEX_RFU_RX+PEX_RFU_RX–

USB_SS1_TX+USB_SS1_TX–USB_SS1_RX+USB_SS1_RX–

PEX2_TX+PEX2_TX–PEX2_RX+PEX2_RX–

PEX0_TX+PEX0_TX–PEX0_RX+PEX0_RX–

PEX0_CLKREQ#PEX0_RST#

PEX2_REFCLK+PEX2_REFCLK–

PEX2_CLKREQ#PEX2_RST#

SATA_DEV_SLPPEX1_CLKREQ#PEX1_RST#PEX_WAKE#

A44A45

H45

H44

E45

E44

F41

F40

C41

C40

G43

G42

D43

D42

G40

G39

D40

D39

C48C49

A41A42

C46D49

D47

C47E50

D48

0.1uF

0.1uF

PCIe#0Lane3

0.1uF

0.1uF

PCIe#0Lane1

0.1uF

0.1uF

PCIe#0Lane2

0.1uF

0.1uF

PCIe#0Lane0

Option#1:PCIex1-x4(Ctrlr#0)

Option#2:PCIex1(Ctrlr#1-onlyPEX2_TX/RXlaneused)

OptionallyusedwithPCIex1onPEX2_TX/RX(PCIeCtrlr#1).

ControlforPCIeCtrlr#1Lane

ControlforPCIeCtrlr#2Lane

Shared

NVHS0_REFCLK

PEX_CLK5

CAN0_EN

PCIE0_TX1_NPCIE0_TX1_P

PCIE0_RX1_NPCIE0_RX1_P

PCIE0_TX0_NPCIE0_TX0_P

Mux

SEL

PCIE0_RX0_NPCIE0_RX0_P

PCIE0_CLK_NPCIE0_CLK_P

PCIE1_TX0_NPCIE1_TX0_P

PCIE1_RX0_NPCIE1_RX0_P

PCIE1_CLK_NPCIE1_CLK_P

PCIE1_CLKREQ*PCIE1_RST*

PCIE_WAKE*

PCIE0_CLKREQ*PCIE0_RST*

0.22uF

140

0.22uF

142

PCIe#0Lane1

137

139

0.22uF

134

0.22uF

136

PCIe#0Lane0

133

137

160

162

0.22uF

134

0.22uF

136

PCIe#1Lane0

133

137

160

162

180

181

179

180

181

PCIe#0–PCIex4conn/device(i.e.M.2KeyM)

PCIe#1–PCIex1conn/device(i.e.M.2KeyE)

PCIe#1–PCIex1conn/device(i.e.M.2KeyE)

Sharedwakepin

PCIe#0–PCIex4conn/device(i.e.M.2KeyM)

SATA

SATAisonlysupportedontheJetsonTX2Seriesmodules.JetsonXavierNXdoesnotsupportthisfeature.

Ethernet

BothJetsonTX2SeriesandJetsonXavierNXmoduleshaveGigabitEthernetPHYsonthemoduleandoutputtheMDxinterface.JetsonTX2hasanadditionalLinkcontrolpin.

Figure6. JetsonXavierNXandJetsonTX2EthernetBlockDiagram

JetsonTX2Series

GBE_MDI0+

SoC

EQOS

GBE_MDI0–

GBE_MDI1+GBE_MDI1–F48GBE_MDI2+GBE_MDI2–

GBE_MDI3+H47

GBE_MDI3–H48

GBE_LINK_ACTGBE_LINK_100

GBE_LINK_1000

F46

F50

E47

G49

G48

F47

E49

E48

GbETranceiver

SoC

JetsonXavierNX

GBE_MDI0_P

GBE_MDI0_N

GBE_MDI1_P

EQOS GBE_MDI1_N

GBE_MDI2_PGBE_MDI2_NGBE_MDI3_P

GBE_MDI3_N

198

GBE_LED_ACT 194

GBE_LED_LINK 188

202

204

196

190

192

184

186

EthernetPHY

ToMagnetics/RJ45Connector

ToMagnetics/RJ45Connector

Display

JetsonTX2supportDSI,Vesa®DisplayPort™(DP),embeddedDisplayPort(eDP),andHDMIasdescribedinthissection.JetsonXavierNXdoesnotsupportDSIbutdoessupportDisplayPort(DP),embeddedDisplayPort(eDP),andHDMI.

DSI

JetsonXavierNXdoesnotsupportDSI.JetsonTX2supportsuptoadual-linkDSIconfigurationwhichincludestwosetsoffourdatalanes,eachwithaclocklane.

D33

D34

C34

C35

E32

E33

JetsonTX2

DSI0_CK+DSI0_CK–DSI0_D0+DSI0_D0–DSI0_D1+DSI0_D1–

DSI1_CK+DSI1_CK–DSI1_D0+DSI1_D0–DSI1_D1+DSI1_D1–

DSI2_CK+DSI2_CK–DSI2_D0+DSI2_D0–DSI2_D1+DSI2_D1–

DSI3_CK+DSI3_CK–DSI3_D0+DSI3_D0–DSI3_D1+DSI3_D1–

DisplayConn.(DSI)

CLK_P

CLK_N

D0_P

1-2

D0_N

Lanes

D1_P

D1_N

CLK_P

CLK_N

D0_P

1-2

D0_N

Lanes

D1_P

D1_N

CLK_P

CLK_N

D0_P

1-2

D0_N

Lanes

D1_P

D1_N

CLK_P

CLK_N

D0_P

1-2

D0_N

Lanes

D1_P

D1_N

G33

G34

F34

F35

H32

H33

Figure7. JetsonTX2DSIBlockDiagram

G30

G31

F31

F32

H29

H30

D30

D31

C31

C32

E29

E30

eDP,DP,andHDMI

BothJetsonXavierNXandJetsonTX2cansupporteDP,DP,andHDMIdisplays.Twointerfacesareprovidedwhichcansupportanyofthedisplaytypeslisted.

Table5. eDP,DP,andHDMIDisplaySupport

Feature

JetsonXavierNXorTX2Series

eDP/DP/HDMI

DP[1:0]_TXD[3:0]_P/N,DP[1:0]_AUX_P/N,DP[1:0]_HPD

Camera

JetsonTX2has12CSIdatalanes.JetsonXavierNXhas14totaldatalanesalthoughonly12canbeusedinadesign.BothJetsonXavierNXandJetsonTX2cansupportthefollowingconfigurationstocamerasorserializers:

⯈3x4

⯈2x4+2x2

⯈1x4+4x2

⯈6x2

Figure8. JetsonXavierNXandJetsonTX2CSIBlockDiagrams

JetsonTX2

CSI0_CK+G28

CSI0_CK–G27

CSI0_D0+ F29

CSI0_D0– F28

CSI0_D1+H27

CSI0_D1–H26

CSI1_CK+D28

CSI1_CK–D27

CSI1_D0+C29

CSI1_D0–C28

CSI1_D1+E27

CSI1_D1–E26

CSI2_CK+G25

CSI2_CK–G24

CSI2_D0+ F26

CSI2_D0– F25

CSI2_D1+H24

CSI2_D1–H23

CSI3_CK+D25

CSI3_CK–D24

CSI3_D0+C26

CSI3_D0–C25

CSI3_D1+E24

CSI3_D1–E23

CSI4_CK+G22

CSI4_CK–G21

CSI4_D0+ F23

CSI4_D0– F22

CSI4_D1+H21

CSI4_D1–H20

CSI5_CK+D22

CSI5_CK–D21

CSI5_D0+C23

CSI5_D0–C22

CSI5_D1+E21

CSI5_D1–E20

2-laneMapping

JetsonXavierNX

CSI_0_CLK_N 10

CSI_0_CLK_P 12

CSI_0_D0_N 4

CSI_0_D0_P 6

CSI_0_D1_N 16

CSI_0_D1_P 18

CSI1_CLK_N 9

CSI1_CLK_P 11

CSI1_D0_N 3

CSI1_D0_P 5

CSI1_D1_N 15

CSI1_D1_P 17

CSI2_CLK_N 28

CSI2_CLK_P 30

CSI2_D0_N 22

CSI2_D0_P 24

CSI2_D1_N 34

CSI2_D1_P 36

CSI3_CLK_N 27

CSI3_CLK_P 29

CSI3_D0_N 21

CSI3_D0_P 23

CSI3_D1_N 33

CSI3_D1_P 35

CSI4_CLK_N 52

CSI4_CLK_P 54

CSI4_D0_N 46

CSI4_D0_P 48

CSI4_D1_N 58

CSI4_D1_P 60

CSI4_D2_N 40

CSI4_D2_P 42

CSI4_D3_N 64

CSI4_D3_P 66

DSI_CLK_N 76

DSI_CLK_P 78

DSI_D0_N 70

DSI_D0_P 72

DSI_D1_N 82

DSI_D1_P 84

4-laneMapping

Camera#0(2-lane)

Camera#1(2-lane)

Camera#2(2-lane)

Camera#3(2-lane)

Camera#4(2-lane)

Camera#5(2-lane)

CameraA(OnlyCSI0ClockUsed)

CameraB(OnlyCSI2ClockUsed)

CameraC(OnlyCSI4ClockUsed)

Camera1(2-Lane)

Camera2(2-Lane)

Camera3(2-Lane)

Camera4(2-Lane)

Camera5(2-Lane)

Camera1(4-Lane)OnlyCSI0ClockUsed

Camera2(4-Lane)OnlyCSI2ClockUsed

Camera3(4-Lane)

Camera6(2-Lane)

SDIOandSDCard

JetsonTX24GBandJetsonTX2ibringtwoSDMMCinterfacestothemodulepins(SDCARDpinssupportingSDCardorSDIOandSDIOpinssupportingSDIO).OtherSDMMCinterfacesareusedon-moduleforeMMCandWi-Fi/BT.JetsonTX2andJetsonXavierNXbringoneSDMMCinterfacetothemodulepins.ThiscanbeusedforSDCardorSDIO.TwooftheotherSDMMCinterfacesareunusedandthelastisusedforeMMConthemodule.

Figure9. JetsonXavierNXandJetsonTX2SeriesSDIO/SDCardBlockDiagrams

JetsonTX2

SDCARD_CLKSDCARD_CMDSDCARD_D0

SDMMC1 SDCARD_D1SDCARD_D2SDCARD_D3

SDMMC2

(EQOS)

SDMMC3 WiFi

GbE

SDIO_CLKSDIO_CMDSDIO_D0SDIO_D1SDIO_D2SDIO_D3

SDMMC4 eMMC

A03

A31

A32

B32

B29

B30

F18

F19

H17

H18

G19

G18

SDCard/SDIO

SDIO_CLK B30

SDIO_CMD B29

SDIO_D0 B32

SDMMC3 SDIO_D1

A32

SDIO_D2 A31

SDIO_D3 A03

SDMMC4 eMMC

GbE

SDMMC2

(EQOS)

G18

G19H18H17F19F18

SDMMC1 SDCARD_D1

SDCARD_D2SDCARD_D3

JetsonTX2

4GB/TX2i

SDCARD_CLKSDCARD_CMD

SDCARD_D0

SDCard/SDIO

SDIO

eMMC

SDMMC4

Unstuffed

SDMMC1 MicroSDCardsocket

SDMMC_CLK 229

SDMMC_CMD 227

SDMMC_DAT0 219

SDMMC3 SDMMC_DAT1

221

SDMMC_DAT2 223

SDMMC_DAT3 225

JetsonXavierNX

SDCardorSDIO

Audio

JetsonTX2SeriesmodulesbringfourI2SinterfacesandamasteraudioMCLKtothemodulepins.Inaddition,adigitalmicrophoneanddigitalspeakerinterfacearealsosupported.JetsonXavierNXbringstwoI2SandanaudioMCLKtothemodulepins.

Figure10. JetsonXavierNXandJetsonTX2AudioBlockDiagram

JetsonTX2

AUDIO_MCK F1

I2S0_CLK G2

I2S0_LRCK H1

I2S0_SDOUT H2

I2S0_SDIN G1

AO_DMIC_IN_CLK E16

AO_DMIC_IN_DAT D16

I2S1_CLK C15

I2S1_LRCK D13I2S1_SDOUTD14I2S1_SDIN C14

DSPK_OUT_CLK G4

DSPK_OUT_DAT H4

I2S2_CLK G5

I2S2_LRCK H5

I2S2_SDOUT H6

I2S2_SDIN G6

I2S3_CLK C15

I2S3_LRCK D13I2S3_SDOUTD14I2S3_SDIN C14

Recommended

Usage

AudioDevice(i.e.Codec)

Microphone

AudioDevice

Speaker

AudioDevice(i.e.M.2KeyE)

AudioDevice

AudioDevice(i.e.Codec)

Jetson

XavierNX

GPIO09

211

I2S0_SCLK

199

I2S0_FS

197

I2S0_DOUT

193

I2S0_DIN

195

I2S1_SCLK

226

I2S1_FS

224

I2S1_DOUT

220

I2S1_DIN

222

RecommendedUsage

AUD_MCLK

AudioDevice(i.e.M.2KeyE)

I2C

JetsonTX2supportseightI2CinterfaceswhenDP[1:0]_AUXinterfacesareincluded.JetsonXavierNXsupportuptofourI2Cinterfacesatthemodulepins.

⯈ForJetsonTX2,twooftheinterfacesaretheDP_AUXinterfacesthatareusedforeDP/DP/HDMIsupport,butcanbeusedasI2Cinterfacesifavailable.Thesepinsdonothaveon-modulepull-upsandcanbepulledtoeither1.8Vor3.3Vonthecarrierboard.

⯈TheJetsonTX2I2C_PM,I2C_CAM,I2C_GP0,I2C_GP2andI2C_GP3pinshavepull-upsto1.8Vonthemodulesosupport1.8Vsignallevels.JetsonXavierNXhaspull-upsto1.8VonI2C2only(1.8Vsignallevels).

⯈TheJetsonTX2I2C_GP1pinshaveon-modulepull-upsto3.3V,sosupport3.3Vsignallevels.

OnJetsonXavierNX,I2C0,I2C1,andCAM_I2Chaveon-modulepull-upsto3.3V(3.3Vsignallevels).

Figure11. JetsonXavierNXandJetsonTX2I2CBlockDiagrams

JetsonTX2

I2C_GP1_CLKA21

I2C_GP1_DATA20

I2C_CAM_CLK C6

I2C_CAM_DAT D6

I2C_GP2_CLKC11

I2C_GP2_DATC10

I2C_GP3_CLKC12

I2C_GP3_DATC13

I2C_GP0_CLKE15

I2C_GP0_DATD15

I2C_PM_CLK A6

I2C_PM_DAT B6

DP0_AUX_CH+B35

DP0_AUX_CH–B34

DP1_AUX_CH+A35

DP1_AUX_CH–A34

3.3VLevels

Typicallyusedforcameracontrol(1.8Vlevels)

1.8VLevels

3.3VLevels

JetsonXavierNX

I2C0_SCL 185

I2C0_SDA 187

I2C1_SCL 189

I2C1_SDA 191

I2C2_SCL 232

I2C2_SDA 234

CAM_I2C_SCL 213

CAM_I2C_SDA 215

3.3VLevels

1.8VLevels

1.8VLevels

1.8VLevels

eDP/DPorI2C(1.8V/3.3Vlevels)HDMI/DPorI2C(1.8V/3.3Vlevels)

1.8VLevels

Typicallyusedforcameracontrol(3.3Vlevels)

UART

BothJetsonTX2andJetsonXavierNXbring3UARTstothemodulepins.OnJetsonTX2,allthreeare4-pinUARTs(includeRTS/CTS).OnJetsonXavierNX,oneoftheUARTssupportsonlyTXandRX(2-pinonly).

Figure12. JetsonXavierNXandJetsonTX2UARTBlockDiagrams

Recommended

Usage

UART1_TXUART1_RXUART1_RTS#

UART1_CTS#

UARTgeneral

RSVD

RSVD

UART7_TX_AP

UART7_RX_AP

Misc.

UART3_TX

UART3_RX

UARTgeneral

JetsonTX2

Mux

UART3_RTS#UART3_CTS#

WiFi/BTon

JetsonTX2

UARTgeneral

UART0_TXUART0_RXUART0_RTS#

UART0_CTS#

DebugUART

UART2_TXUART2_RXUART2_RTS#

UART2_CTS#

UARTgeneral

(i.e.M.2KeyE)

A15

A16

B15

B16

H11

G11

G12

H12

G9

G10

H9

H10

UART3_RXUART3_RTS#

UART3_CTS#

JetsonTX24GB/TX2i

UART3_TX

G9

G10

H9

H10

D5

D8

E10

E9

D10

D9

JetsonTX2

99

JetsonXavierNX

RecommendedUsage

UART0_TXDUART0_RXDUART0_RTS*UART0_CTS*

UART1_TXDUART1_RXDUART1_RTS*UART1_CTS*

UART2_TXDUART2_RXD

UARTgeneral(i.e.M.2KeyE)

203

UARTgeneral

209

207

205

105

103

101

238

236

DebugUART

Debug

JetsonTX2bringstheJTAGinterfacetothemodulepinsandprovidesaUART(UART0)fordebug.JetsonXavierNXprovidesUART2fordebugpurposes.JTAGsupportisnotprovidedforJetsonXavierNX.

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