《信息科学类专业英语》课件第8章

Lesson8Top-downSoCDesignMethodology

(第八课自顶向下的SoC设计方法学)

Vocabulary(词汇)ImportantSentences(重点句)QuestionsandAnswers(问答)Problems(问题)

Deepsub-microneffectscomplicatedesignclosureforverylargedesigns.Top-downhierarchicaldesignmethodologycombinedwithphysicalprototypingincreasesdesignproductivityandrestoresschedulepredictability.Inthispaperatop-downhierarchicalflowwillbediscussedanduseofphysicalprototypingtopredicttheperformanceandphysicalcharacteristicsofthefinalphysicalimplementationwillbeexplained.1Top-DownSoCDesignMethodology

System-on-Chip(SoC)designshavebecomeoneofthemaindriversofthesemiconductortechnologyinrecentyears.Multi-milliongatedesignswithmultiplethirdpartyintellectualproperty(IP)coresarecommonplace.SoCdesignersemployIPreusetoimprovedesignproductivity.Previousdesignsdonein-houseorthirdpartydesignscanbeusedasIPinthecurrentdesign.WhileemployingIPcutsdevelopmentcostsandtime,integrationcomplexityincreases.ThisisoneofthemainreasonswhySoCdesignsareimplementedwithhierarchicaltop-downdesignflows(Fig.1).

Theseflowshelptomanagethedifferentandconflictingrequirementsofincreasingdesignsize,deep-submicroneffects(DSM)andthenecessityforshorterandpredictableimplementationtimes.

Hierarchicalmethodologiesallowmultipleteamstoworkondifferentpartsofthedesignconcurrentlyandindependently.This“divideandconquer”approachreducesthecomplexityofthedesignproblemforeachdesignteamandreducesthetimetomarket.FortheSoCdesigns,whicharebuiltfromindependentfunctionblocks,thesecapabilitiesarekeyadvantagesasthefinalimplementationofcomplexchipscanbealengthyprocessandparallelizationcansavevaluabletime.

HierarchicaldesignstylesalsoallowformuchfasterandeasierlateECO’s.Functionalchangesmaybelocalizedtoasingleblockleavingtheremainderofthedesignunaffected.Thislocalizationresultsinfaster,easierECO’s.Anotherreasonforhierarchyistoovercomethecapacitylimitationsofdesigntools.Hierarchicaldesignflowsarescalabletohandledesignscontainingupwardsof100milliongates.

Inadditiontothecomplexitiesthatarearesultoflargedesignsize,deepsub-microneffectsaddtointegrationcomplexitiesandcauselatestagesurprisesandlargeloopsduringthedesigncycle.Fig.1Atop-downhierarchicaldesignmethodology

Indeepsub-microntechnologies,wires,power,routabilityandmanufacturabilityhavetobeconsideredearlyinthedesigncycle.Physicalprototypingprovidesearlyfeedbackintermsofdesignclosureandhelpsvalidatethecorrectnessofdesigndecisions.Physicalprototypingshouldaccuratelypredictthecharacteristicsofthefinalphysicalimplementation.Thiscanbeaccomplishedbyperformingcellplacementandglobalroutingatanappropriatelevelofgranularityneededtoensurethattheprototypecorrelatestothefinalimplementationwithinaspecifiedtolerance.[1]

Traditional,top-downSoCdesignsrelyontheassumptionthatthebudgetingperformedatthechip-levelneednotberevisedaftertheblocksareimplemented.However,unlessveryconservativebudgetsareused,itisimpossibletopredictupfrontwhetherthefinalblockimplementationswillmeetallconstraints.[2]Also,itisdifficulttoadjustthebudgetingifwecannotcapturethephysicalproperties(e.g.,driverstrength,parasitics,currentdrain,etc)thatareobservedattheblockandchipboundaries.

Atop-downhierarchicaldesignmethodologyshouldthereforebecombinedwithphysicalprototypingtoenhancedesignproductivityandrestoreschedulepredictability.Inthispaper,atop-downhierarchicalblock-basedflowwillbediscussedanduseofphysicalprototypingtopredicttheperformanceandphysicalcharacteristicsofthefinalphysicalimplementationwillbeexplained.2HierarchicalSoCDesignFlow

Thecomponentsofapredictabletop-downhierarchicalflowaredesignplanning,physicalprototyping,andimplementation.Atthedesignplanningstage,chiptopography,area,numberofchiplevelpartitionsandtimingbudgetsaredetermined.Duringphysicalprototyping,thedesignplanningresultsarevalidatedforeachblockandforthetop-level.Ifnecessary,correctiveactionistakenbygoingbacktodesignplanningandprogressivelyrefiningthedesign.

Oncephysicalprototypingresultsaresatisfactory,implementationcancommenceconcurrentlyforeachblockandforthetop-level,withtheassurancethatdesign-planningdecisionsarecorrectandimplementationwillbecompletedwithoutanylatesurprises.Top-downplanningandbottom-upprototypingisthemostpredictablewaytoachieveclosureonlargeSoCdesigns.

Designplanningconstitutesanimportantportionofthetop-downhierarchicaldesignflow(Fig.2).TheSoCdesignerevaluatestradeoffswithrespecttotiming,area,andpowerduringdesignplanning.Atthisstage,variousIPcoresfromdifferentvendorsareintegratedintothedesignalongwithcustomlogic.TheIPmaybeprovidedasRTLcode,gatelevelnetlists,orfullyimplementedhardmacros.DecisionsregardingchoicesofdifferentimplementationsofthesameIP,chipandblockaspectratio,budgetingoftop-levelconstraints,standardcellutilization,andotherdesignaspectsaremadeduringdesignplanning.Fig.2Designplanning

Designplanningfunctionsincludepartitioningofthedesign,blockplacementandshaping,hardmacroplacement,pinassignmentandoptimization,toplevelrouteplanning,toplevelrepeaterinsertion,blockbudgetgeneration,andpowerrouting.AllofthesefunctionsarecloselylinkedtotheunderlyingphysicsofDSMtechnology.Forexample,top-levelrepeaterinsertioncannotbedoneproperlywithoutconsideringsignalintegrityandpinscannotbeassignedwithoutconsideringantennarules.

Designplanningcanstartuponavailabilityoftheinitialtop-levelnetlist,evenifthemoduleshavenointernaldefinitionorstructure.Atthisstagemissingmodulesarerepresentedasblackboxes.Theareasofblackboxesareuserdefinedandquicktimingmodelsaregeneratedforsetup/holdarcsandclock-to-outputdelays.Areaestimatesformodulesthathavealreadybeensynthesizedwillbedeterminedbythegatecountanduserdefinedutilization.

Oncethedesignisreadin,andblocksizesaredetermined,aninitialfloorplaniscreatedbyautomaticallyplacingallblocks,shapingthesoftblocks,andpackingtheblockstogetherbasedonglobalroutinginformation.Usingtheblockplacementresults,adjacentblocksmaybeclusteredtogether,orverylargeblocksmaybedividedintosmallerblocks.Modificationsofthephysicalhierarchyatthisstagemaybemadetotakefulladvantageofthephysicalimplementationtools,andtominimizethenumberoftop-levelblocks.

Theblockplacermustalsobeabletoautomaticallyperformsuchoperationsasdeterminethebestaspectratiosforsoftblocksandchoosethebestamongdifferentequivalentimplementationsofhardblocks.AcombinationoftheblockplacerwithamemoryormacrogeneratorleadstooptimizedSoCblocksasthedesignplannerfindsaglobaloptimumbetweenthedifferentpossibleimplementationsandthechipplan.Afterinitialblockplacement,top-downpinassignmentisperformed;top-levelconnectivityandtimingdrivetheplacementofthepinsontheblocks.ForRTLorblackboxmodules,pinassignmentwillhelptocreateblock-levelconstraints.Oncethephysicallocationsofpinsareknown,top-levelnetlengthscanbeestimated.

Foreachblock,aninternaldesignplaniscreated.Macroplacementisdrivenbybothtop-downpinassignmentsthatweredoneinthepreviousstepandinternalmetricssuchasconnectivity,timingandarea.Oncetheinternalplanningforallblockshasbeencompleted,powerrouteplanningisdone.Mostrecenttechnologiesrequireameshstructure.Thepowerroutinggridandblockplacementgridshouldbecarefullysettopreventconnectivityproblemsthatmayariseduetomisalignmentofablockwithrespecttopowergrid.

Afterpowerrouting,pinassignmentsarerefinedusingglobalroutingresults.Theglobalroutercanidentifynarroworwidechannelsandmoveblocksaroundtoopenupcongestedchannelsandconstrictsparseones.Thisenablesoptimumpinplacementforroutabilityduringtheimplementationstage.

AnothercomplexityfacingSoCdesignersduringdesignplanningistop-levelrouteplanning.Netsbetweencriticalblocksmustbeasshortaspossibleandshouldoftenberoutedoverotherblocks.Theseover-the-blocknetsshouldbepusheddownintotheblocksautomatically.Thisrequiresthatanumberofoperationstakeplace.Pinsmustbeassignedtotheblocktoaccommodatethisnewfeedthroughnet.Boththetop-levelandinternalblock-levelnetlistsmustbealteredtoaddconnectivitytothefeedthroughnet.

Top-leveltimingbudgetsmustbeadjustedandinternalblock-levelbudgetsmustbegeneratedtoaccountforglobaltimingclosureandsignalintegrity.Theuseofroutingoverblocksmayevenincludereservingspecialroutingchannelsandemptyplacementareasforrepeaters.Alteringblocksinthiswayconflictswiththegoalofhavingseparated,orevenre-usableSoCblocks,soitdependsontheoverallprojectgoalstowhatextentsuchtechniquesareused.IfTurn-AroundTime(TAT)orre-usearetheprimarygoals,suchtechniquesshouldusedverycarefully.Ifsmallestdiesizeorbestdesignperformanceareprimarygoals,thentheuseoffeedthroughsmaybeessentialtoachievingthegoals.

Duringtimingbudgeting,delayoftop-levelnetsshouldbecalculatedwiththeassumptionthatbufferswillbeaddedtolongorhighfan-outnetsasneeded.Blockbudgetswillbeusedasconstraintstodrivesynthesis,prototyping,andimplementationoftheblocks.

Inpractice,planningmaybeginbeforealloftheblocksarefullyimplemented,soroughestimatesareinitiallyusedinstead.Astheblocksprogressivelygaindefinition,itisnecessarytorelaythenewblockinformationbackuptothechip-level,whereitisincrementallyupdatedandtheappropriateadjustmentsaremade.Thismaytriggerchangesatthechiplevelthatmustbepushedbackdowntotheblocklevel.Thisleadstoatop-downbudgeting,bottom-upprototypingflow,whichismorepredictableandbettersuitedtohandlevariancesbetweenblock-levelconstraintsandactualimplementation.

Althoughitmayappearthatthereisaconflictbetweenearlydesignplanningusingblack-boxmodelsorRTLandnetlist-baseddesignplanningthisisnotthecase;theseactivitiesactuallycomplementeachother(Fig.3).

Earlytop-downdesignplanningisanimportantsteptodriveRTLsynthesisandtogenerateagate-levelnetlistthatisusedtofurtherrefinethedesignplan.Fig.3Designactivitiescomplementeachother

Acharacteristicofthecontinuousplanningandoptimizationprocessistheuseofdifferenttypesofmodelsthatareoptimizedforthedifferentoperationsintheprocess.Thisisillustratedinthefigureabove.

Simpleblockmodelsareusedfordesignplanningandbudgeting.Thephysicalprototypesoftheblocksarebuiltbaseduponthebudgetsfromthedesignplan.Thephysicalprototypesprovidevaluablephysicalinformationaboutthefinalimplementationoftheblocks.Theywillbedescribedinthenextchapter.ThephysicalprototypesarethenusedtoreplacetheblackboxesandRTLmodulesatthetoplevel,sothatwecanrefinethechip-levelconstraints.Whenthefinalbudgetingisresolved,wereturntotheblocksandresumetheirimplementation,andthenwefinishwiththetop-levelchipassembly.

Also,differenttypesofmodelscanbemixedatthetoplevelsinceitislikelythatallprototypeswillnotbecompletedatexactlythesametime.Thisenablesearlyverificationandadjustmentofthechip-levelconstraintsusingacombinationofblackboxesorRTLforsomeblocks,accurateprototypesforothers,andevencompletedphysicallayoutsforsomeoftheblocks.

PhysicalprototypingisanimportantstageofthehierarchicaldesignflowasitprovidesmoredetailsabouttheblockimplementationtotheSoCdesigner.Itbridgesthegapbetweenlogicalandphysicaldesignbyaddingphysicalrealitytotheabstractviewofthedesignplanningprocess.Duringphysicalprototyping,logicoptimizationandglobalplacementareconcurrentlyapplied.Atthisstage,design-planningresultsarevalidatedforeachblockandforthetop-level,andallconflictsareresolved.Theprototypesuncovertheproblems;thecorrectiveactionistakeninthedesignplanningstage.Incompletetimingconstraintscanbediscoveredandaddressedwiththeavailabilityofaccuratephysicalinformation.

PhysicalprototypingisinseparablyconnectedwiththephysicalsynthesisprocessthataddressesmanyDSMissuesbycombiningelementsoflogicsynthesisandphysicalimplementationtogetherintoasinglestage.Physicalsynthesis,asmostpeopleuseittoday,startswithagate-levelnetlistandperformslogicoptimization,placementandglobalrouting,toproduceaplaceddesignthatmeetstimingrequirements.Physicalsynthesismayemploynumeroustechniquestooptimizethelogicalstructureofthechipincluding:gatesizing,buffering,pinswapping,gatecloning,usefulskew,re-synthesisandtechnologyre-mapping,redundancy-basedoptimization,andareaandpowerrecovery.[3]

Thisisasignificantimprovementoverpurelogicsynthesisbecausethelogicoptimizationisperformedandevaluatedbasedoncellplacementthatisindicativeofthefinalplacement.

ItissignificanttonotethatitnolongermakessenseforRTL-to-gatesynthesistoolstoperformsophisticatedgate-leveloptimization.Withoutaccuratephysicalinformation,logicsynthesistoolscannotmakegooddecisionsaboutcellsizingorbuffering.

Physicalsynthesisismuchbettersuitedforthesetasks.Today,theroleofRTL-to-gatelogicsynthesishasbeenreducedtosimplyproducingastructuralgate-levelnetlistasquicklyaspossible,andthenpassitalongtophysicalsynthesiswithoutattemptingtooptimizethesizingorbufferingaspects.ThishasconsequencesforIPcores,whicharedeliveredassoftmacrosfromtheIPvendortotheuserorimplementer.TheIPproviderdeliverseitherthefinalhardmacrooranRTL/netlistandimplementationconstraintstoallowtheoptimizationoftheIPduringtheimplementationoftheSoCchip.

Alltheinformationgeneratedduringthephysicalprototypingofblocksplaysakeyroleinfeedingbackmoreaccurateinformationtothedesignplanningstageforrefinementoftop-leveldesignparameters.

Thephysicalprototypeconsistsofacoarseplacementandoptimizednetlist.Powerrouting,clocktreebuffers,highfan-outnetbufferingmustbeincludedinthephysicalprototype.Withoutanyoftheseitems,physicalprototypewillnotcorrelatetoimplementationandwillnotgiveusefulresults.

Tocreatethephysicalprototype,ahierarchicaltreeofcell-clustersisbuilt

fromtheoriginalnetlistbeforetheplacementstarts.Whilebuildingthetree,functionalhierarchyandconnectivityareconsidered.Then,theblockareaisdividedintoplacementbins,andthecell-clustersareassignedtobinsamonghardmacros.Thecongestionismodeledusingwirescrossingbinboundaries.Duringtheearlystages,thebinsareverycoarseanditisnotusefultomeasuretimingsincemostofthewirecapacitanceisduetointra-binnetsandcanonlybestatisticallyestimated.

Asplacementprogresses,theblockareaisfurtherdividedintosmallerbins,andplacementisrefined,toimprovebothcongestionandwirelength.Thebinscontinuetogetprogressivelysmallerinsizeuntilatsomepoint,theglobalwirescanbeaccuratelyestimated,andintra-binwireuncertaintyisnegligible.Physicalsynthesiscannowstartandthenetlististransformedtomeettimingconstraints.Theplacementisnotyetfinalized,hence,theimpactofnetlistoptimizationoperationssuchaslongnetbuffering,sizing,fan-outoptimization,technologyre-mapping,etc.,canbeeasilyabsorbed.

Similarly,clocktreesynthesiscanbedoneatthephysicalprototypingstageassumingtheleafinstancesareplacedatthecenterofthebins.Congestionandutilizationestimatesaremoreaccuratewiththeinclusionofclocktreebuffers.

Physicalprototypesareusedtovalidatetimingbudgets,areabudgets,IRdrop,congestion,andpinlocations.Thefeedbackfromphysicalprototypingbacktodesignplanningcontainsaccuratetimingabstractions(forrefiningbudgetingattop-level),powermodels(fortop-levelIR-Dropanalysis),andcongestionhotspots,whichneedtobeaddressedbyrelocatingpinsorhardmacroplacement.

Thetop-levelphysicalprototypewillprovidefeedbackontop-leveltimingclosure,routingcongestion,andrequiredchannelareaforbufferingbothclockandsignalnets.

Asthedesignbecomesmoreandmoredefined,theloopsbetweenthedesignplanningstageandprototypingwillconverge.Onceallblocksandthetop-levelaredefined,theSoCdesignerisreadyforimplementation.

Sign-offisthedelineationbetweenthedesignrefinementprocessdescribedaboveandthefinalimplementation.IthaschangedovertimetoaccommodatethenewrequirementsassociatedwithDSMprocesstechnologies.Inthepast,anetlisthand-offwassufficientandprovidedareliableinterfacebetweenlogicalandphysicaldesign.Aswehaveseeninthepreviouschapter,anetlistgeneratedbyRTLsynthesisisnolongerthefinalnetlist.Insteadaprototypecontaininganoptimizednetlistandacoarseorevenfinalplacementareusedtosign-offthedesignpriortofinalimplementation.

Implementationcompletestheprocessbytransformingtheprototypeintoafinalphysicallayout.Implementationoperationsincludedetailedlogicoptimization,placement,androuting.Throughouttheprocess,thedesignisbeingcontinuouslymonitoredfortiming,power,clockskewanddelay,IRdrop,andsignalintegrity.Oncetheblocksarefinished,top-levelassemblyisdone.Sincetheblock-levelimplementationsweredrivenbytop-downconstraints,top-levelsurprisesareeliminated.[4]

Asmentionedabovethestartingpointforfinalimplementationcanbeaprototypewithacourseplacement,inthiscasethefinalimplementationproceedsusingthesametechnologyaswasusedtogeneratethephysicalprototypewithprogressivelysmallerandsmallerbins.Ateachbinlevel,congestion,wirelength,andtimingoptimizationsareincrementallyrun.Ifthestartingpointforimplementationisafinalplacement,thentheimplementationstageproceedswiththeroutingandadjuststheplacementasneeded.

Accurateabstractionsofcompletedblocksareneededtoperformtop-levelassemblyandsign-offthedesignfortapeout.Timingmodelsshouldincludeinterfaceparasitics,accountforsignalintegrity,andshouldbeabletoconsidertimingexceptionsonnetsthatcrossblockboundaries.Physicalmodelsshouldcorrectlyrepresentembeddedwidewires,viacutsneartheboundariesofblocks,antennamodels,andelectromigrationeffects.

Top-levelclocktreesynthesisplaysanimportantroleinreducingholdviolations.Atthetop-level,clocktreesaresynthesizedsuchthatskewtoeachblockinputisadjustedtoaccountfortheinsertiondelayinsidetheblock.Thetop-levelsetupandholdviolationscanbeidentifiedandfixedwithblocktimingabstractsgeneratedusingpropagatedclocks.Theskewtoeachregisterconnectedtoablock-levelclockpinwillbeincludedinthetimingabstractifapropagatedclockisusedduringabstractgeneration.Atthetop-level,setupandholdviolationsbetweenclockscanbeidentifiedandaddressed.3CONCLUSION

IPreuseinSoCsbridgesthedesigngapbyimprovingproductivitybutatthesametime,DSMeffectscomplicateintegration.Theonlywaytorestorepredictabilitytodesigncycleisthroughtop-downdesignplanning,combinedwithfastandaccuratephysicalprototyping.Block-baseddesignplanningaddressesincreasedcomplexity;whilephysicalprototypingrestorespredictabilityandimprovesturnaroundtimebytakingintoaccountuncertaintiesduetowiresandotherDSMeffects.

1. hierarchicaladj.分层的，分等级的。

2. prototypen.原型,雏形,蓝本。

3. ECO(EngineeringChangeOrder)后期设计修正。

4. upfrontadj.坦率的，诚实的，直爽的；公开的，预付的,预交的,先期的adv.在最前面。

5. parasiticsn.寄生现象，寄生效应。

6. Sign-off签收。

Vocabulary

[1]Physicalprototypingshouldaccuratelypredictthecharacteristicsofthefinalphysicalimplementation.Thiscanbeaccomplishedbyperformingcellplacementandglobalroutingatanappropriatelevelofgranularityneededtoensurethattheprototypecorrelatestothefinalimplementationwithinaspecifiedtolerance.

物理原型设计应当精确地预计最后的物理实现的特性。这可以通过单元布局和全局布线达到，而这种布局布线要在适当的分级层次上进行，以保证相关的设计原型和最终实现之间的误差在规定的容许范围之内。granularity，颗粒度，在这里是电路分级的粒度。ImportantSentences

[2]Traditional,top-downSoCdesignsrelyontheassumptionthatthebudgetingperformedatthechip-levelneednotberevisedaftertheblocksareimplemented.However,unlessveryconservativebudgetsareused,itisimpossibletopredictupfrontwhetherthefinalblockimplementationswillmeetallconstraints.

传统的自顶向下SoC设计假定芯片级的预算在模块实现之后不需要修正。但是，除非使用很保守的预算，否则不可能事先预计最终模块的实现是否会满足所有限制条件。

[3]PhysicalprototypingisinseparablyconnectedwiththephysicalsynthesisprocessthataddressesmanyDSMissuesbycombiningelementsoflogicsynthesisandphysicalimplementationtogetherintoasinglestage.Physicalsynthesis,asmostpeopleuseittoday,startswithagate-levelnetlistandperformslogicoptimization,placementandglobalrouting,toproduceaplaceddesignthatmeetstimingrequirements.Physicalsynthesismayemploynumeroustechniquestooptimizethelogicalstructureofthechipincluding:gatesizing,buffering,pinswapping,gatecloning,usefulskew,re-synthesisandtechnologyre-mapping,redundancy-basedoptimization,andareaandpowerrecovery.把逻辑综合与物理实现结合在一个阶段，物理原型设计与处理很多深亚微米问题的物理综合过程不可分离地联系在一起。物理综合可从门级网表开始，进行逻辑综合，优化、布局和全局布线，产生满足定时要求的定位设计。物理综合可以利用很多技术来优化芯片的逻辑结构，包括：门的大小、缓冲、引脚交换、门的复制、有用的畸变、再综合和工艺再映射、基于冗余的优化，以及面积和电源的恢复。

[4]Implementationcompletestheprocessbytransformingtheprototypeintoafinalphysicallayout.Implementationoperationsincludedetailedlogicoptimization,placement,