简单计算机系统课程设计-计算机组成实验-

《计算机组成实验C》

课程设计

适用专业：电子信息类专业

专业：

班级：

学号：

姓名：

指导教师：

实验学期：2014-2015第1学期

西南交通大学

信息科学与技术学院

简化计算机系统的设计

一.实验目的：通过学习简单的指令系统及其各指令的操作流程，用VHDL语

言实现简单的处理器模块，并通过调用存储器模块，将处理器模块和存储器模块

连接形成简化的计算机系统。

二.实验内容

I.用VHDL语言实现简单的处理器模块。

2.调用存储器模块设计256x16的存储器模块。

3.将简单的处理器模块和存储器模块连接形成简单的计算机系统。

4.将指令序列存入存储器，然后分析指令执行流程。

三.预习要求：1、学习简单指令集。2、学习各指令的操作流程。

四.实验报告

1.BLOCK图

图1原理图

内存文件:

Addr♦0+1♦2+3X+5+6♦7

000000015002400D0001F0094003100E0

8001E004100A10061008400510028002D

16007B00D0001Eooco001900D0001D00B0

24001300F0000000000000000000000000

3200000000000000000000000000000000

4000000000000000000000000000000000

4800000000000000000000000000000000

5600000000000000000000000000000000

6400000000000000000000000000000000

7200000000000000000000000000000000

80____00000000000000000000000000000000

图2内存文件.Mif

2.程序设计

LIBRARYieee;

USEieee.std_logic_1164.ALL;

PACKAGEmypackIS

CONSTANTidle:stdjogic_vector(3DOWNTO0):="0000";

CONSTANTload:stdlogicvector(3DOWNTO0):="0001H;

CONSTANTmove:std_logic_vector(3DOWNTO0):="00l0";

CONSTANTaddx:std_logic_vector(3DOWNTO0):="00ir';

CONSTANTsubp:std_logic_vector(3DOWNTO0):="0100";

CONSTANTandp:std_logic_vector(3DOWNTO0):="0101";

CONSTANTorp:std_logic_vector(3DOWNTO0)

CONSTANTxorp:std_logic_vector(3DOWNTO0):="0111";

CONSTANTshrp:std_logic_vector(3DOWNTO0):="1000";

CONSTANTship:std_logic_vector(3DOWNTO0):="1001";

CONSTANTswap:std_logic_vector(3DOWNTO0):="1010";

CONSTANTjmp:std_logic_vector(3DOWNTO0):="1011";

CONSTANTjz:std_logic_vector(3DOWNTO0):="1100";

CONSTANTread:std_logic_vector(3DOWNTO0)

CONSTANTwrite:std_logic_vector(3DOWNTO0):="1110";

CONSTANTstop:stdjogic_vector(3DOWNTO0):="1111H;

ENDmypack;

LIBRARYieee;

USEieee.std_logic_1164.ALL;

USEieee.std_logic_unsigned.ALL;

USEWORK.mypack.ALL;

-------------------------cpu实体声明-----------------------

ENTITYcpu2IS

PORT(

reset:INstdjogc;-清零信号低有效

clock:INstdjogic;一时钟信号

Write_Read:OUTstdjogic;一读写信号,T为写

M_address:OUTstd_logic_vector(11DOWNTO0);••地址线

M_data_in:INstd_logic_vector(7DOWNTO0);-数据输入线

Mdata_out:OUTstd_logic_vector(7DOWNTO0);--数据输出线

overflow:OUTstdjogic);一溢出标志

ENDcpu2;

..............................cpuRTL级行为描述............

ARCHITECTURERTLofcpu2IS

SIGNALIR:std_logic_vector(15DOWNTO0);-指令寄存器

SIGNALMDR:std_logic_vector(7DOWNTO0);--数据寄存器

SIGNALMAR:std_logic_vector(11DOWNTO0);一地址寄存器

SIGNALstatus:intftgftrRANGE0TO6;--状态寄存器

BEGIN

status_change:PROCESS(reset,clock,status)

BEGIN

IFreset='O'THENstatus<=0;

ELSIFclock'EVENTANDclock='O'THEN

CASEstatusIS

WHEN0=>

status<=1:

WHEN1=>

IFIR(15DOWNTO12)=StopTHEN

status<=1;

ELSE

status<=2;

ENDIF;

WHEN2=>

CASEIR(15DOWNTO12)IS

WHENRead|Write|Jmp|Jz|Swap=>

status<=3;

WHENOTHERS=>

status<=0;

ENDCASE;

WHEN3=>

IFIR(15DOWNTO12)=SwapTHEN

status<=0;

ELSE

status<=4;

ENDIF；

WHEN4=>

status<=5;

WHEN5=>

CASEIR(15DOWNTO12)IS

WHENRead|Write=>

status<=6;

WHENOTHERS=>

status<=0;

ENDCASE;

WHENOTHERS=>

status<=0;

ENDCASE;

ELSE

NULL;

ENDIF;

ENDPROCESSstatuschange;

seq:PROCESS(reset,clock)

VARIABLEPC:std_logic_vector(11DOWNTO0);--程序计数器

VARIABLER0,R1,R2,R3:std_logic_vector(7DOWNTO0);--通用寄存器

VARIABLEA:std_logic_vector(7DOWNTO0);--临时寄存器

VARIABLEtemp:stdlogic_vector(8DOWNTO0);-临时变量

BEGIN

IF(reset='O')THEN—清零

IR<=(OTHERS=>'0');

PC:=(OTHERS=。);

RO:=(OTHERS=>'0,);

R1:=(OTHERS=>'0')；

R2:=(OTHERS=。)；

R3:=(OTHERS=>'0');

A:=(OTHERS='。')；

MAR<=(OTHERS=。)；

MDR<=.：OTHERS=>'0')；

ELSIFfclock'eventANDclock='1')THEN

overflow<='O';

CASEstatusIS

WHEN0=>-状态0

IR<=M_data_in&"00000000";--取指令

PC:=PC+1;-程序计数器加1

WHEN1=>--状态1

IF(IR(15DOWNTO12)/=stop)THEN

MAR<=PC;

ENDIF;

CASEIR(15DOWNTO12)IS

WHENload=>

R0:="0000"&IR(11DOWNTO8；;

WHENshlp|shrp=>

CASEIR(11DOWNTO10)IS-RxtoA

WHEN,,00',=>A:=R0;

WHEN"01"=>A:=R1;

WHEN"10M=>A:=R2;

WHENOTHERS=>A:=R3；

ENDCASE;

WHENMove|addx|subp|andp|orp|xorp|Swap=>

CASEIR(9DOWNTO8)IS-RytoA

WHEN"00"=>A:=R0;

WHEN"01'=>A:=R1;

WHEN"10M=>A:=R2;

WHENOTHERS=>A:=R3;

ENDCASE;

WHENOTHERS=>NULL;

ENDCASE;

WHEN2=>--状态2

CASEIR(15DOWNTO12)IS

WHENaddx=>-Rx:=Rx+A;

CASEIR(11DOWNTO10)IS

WHEN"00"=>

temp:=(R0(7)&R0(7DOWNTO0))+(A(7)&A(7DOWNTO

0))；

R0:=temp(7DOWNTO0);

overflow<=temp(8)XORtemp(7);

WHEN"01"=>

temp:=(R1(7)&R1(7DOWNTO0))+(A(7)&A(7DOWNTO

0))；

R1:=temp(7DOWNTO0);

overflow<=temp(8)XORtemp(7);

WHEN"10"=>

temp:=(R2(7)&R2(7DOWNTO0))+(A(7)&A(7DOWNTO

0))；

R2:=temp(7DOWNTO0);

overflow<=temp(8)XORtemp(7);

WHENOTHERS=>

temp:=(R3(7)&R3(7DOWNTO0))+(A(7)&A(7DOWNTO

0))；

R3:=temp(7DOWNTO0);

overflow<=temp(8)XORtemp(7);

ENDCASE;

WHENsubp=>-Rx:=Rx-A;

CASEIR(11DOWNTO10)IS

WHEN"00"=>

temp:=(R0(7)&R0(7DOWNTO0))+NOT(A(7)&A<7

DOWNTO0))+1；

R0:=temp(7DOWNTO0);

overflow<=temp(8)XORtemp(7);

WHEN"01'=>

temp:=(R1(7)&R1(7DOWNTO0))+NOT(A(7)&A<7

DOWNTO0))+1；

R1:=temp(7DOWNTO0);

overflow<=temp(8)XORtemp(7);

WHEN"10"=>

temp:=(R2(7)&R2(7DOWNTO0))+NOT(A(7)&A<7

DOWNTO0))+1；

R2:=temp(7DOWNTO0);

overflow<=temp(8)xorteTip(7);

WHENOTHERS=>

temp:=(R3(7)&R3(7DOWNTO0))+NOT(A(7)&A<7

DOWNTO0))+1;

R3:=temp(7DOWNTO0);

overflow<=temp(8)XORtemp(7);

ENDCASE;

WHENmove=>

CASEIR(11DOWNTO10)IS

WHEN"00M=>R0:=A;

WHEN"01"=>R1:=A;

WHEN"10M=>R2:=A;

WHENOTHERS=>R3:=A;

ENDCASE;

WHENshrp=>

CASEIR(11DOWNTO10)IS

WHEN"00M=>R0:='O'&A(7DOWNTO1);

WHEN"01"=>R1:='O'&A(7DOWNTO1);

WHEN"10H=>R2:='O'&A(7DOWNTO1);

WHENOTHERS=>R3:=’0,&A(7DOWNTO1);

ENDCASE;

WHENship=>

CASEIR(11DOWNTO10)IS

WHEN"00M=>R0:=A(6DOWNTO0)&'O';

WHEN"01'=>R1:=A(6DOWNTO0)&'O'；

WHEN"10'=>R2:=A(6DOWNTO0)&'O';

WHENOTHERS=>R3:=A(6DOWNTO0)&'O';

ENDCASE;

WHENandp=>-Rx:=RxANDA;

CASEIR(11DOWNTO10)IS

WHEN-00H=>R0:=R0ANDA;

WHEN"01"=>R1:=R1ANDA;

WHEN"10M=>R2:=R2ANDA;

WHENOTHERS=>R3:=R3ANDA;

ENDCASE;

WHENorp=>-Rx:=RxORA;

CASEIR(11DOWNTO10)IS

WHEN"00"=>R0:=R0ORA;

WHEN"01M=>R1:=R1ORA;

WHEN"10M=>R2:=R2ORA;

WHENOTHERS=>R3:=R3ORA;

ENDCASE;

WHENxorp=>-Rx:=RxXORA;

CASEIR(11DOWNTO10)IS

WHEN"00"=>R0:=R0XORA;

WHEN"01M=>R1:=R1XORA;

WHEN"10M=>R2:=R2XORA;

WHENOTHERS=>R3:=R3XORA;

ENDCASE;

WHENSwap=>--Swap:RxtoRy;

CASEIR(11DOWNTO8)IS

WHEN"0100"=>R0:=R1;

WHEN"1000"=>R0:=R2;

WHEN"1100"=>R0:=R3;

WHEN"0001H=>R1:=R0；

WHEN"1001M=>R1:=R2;

WHEN"1101"=>R1:=R3;

WHEN"0010"=>R2:=R0;

WHEN"0110"=>R2:=R1;

WHEN"1110"=>R2:=R3；

WHEN"0111"=>R3:=R1;

WHEN"1011"=>R3:=R2;

WHEN"0011"=>R3:=R0;

WHENOTHERS=>NULL;

ENDCASE;

WHENOTHERS=>NULL;

ENDCASE;

WHEN3=>--状态3

CASEIR(15DOWNTO12)IS

WHENSwap=>-Swap:AtoRx

CASEIR(11DOWNTO10)IS

WHEN"00"=>R0:=A;

WHEN-01M=>R1:=A;

WHEN"10"=>R2：=A；

WHENOTHERS=>R3:=A;

ENDCASE;

WHENjmp|Jz|Read|Write=>

IR(7DOWNTO0)<=M_data_in;-取双字节指令的后半部分

PC:=PC+1;

WHENOTHERS=>NULL;

ENDCASE;

WHEN4=>--状态4

CASEIR(15DOWNTO12)IS

WHENjmp=>-无条件转移指令

PC:=IR(11DOWNTO0);

MAR<=IR(11DOWNTO0)；

WHENJz=>-条件转移指令

IF(R0="00000000")then

PC:=IR(11DOWNTO0)；

MAR<=IR(11DOWNTO0);

else

MAR<=PC;

ENDIF;

WHENRead=>

MAR<=IR(11DOWNTO0);

WHENWrite=>

MARv=IR(11DOWNTO0);

MDR<=RO;

WHENOTHERS=>NULL;

ENDCASE;

WHEN5=>一状态5

MAR<=PC;

WHEN6=>--状态6

CASEIR(15DOWNTO12)IS

WHENRead=>RO:=M_datajn;

WHENOTHERS=>NULL;

ENDCASE;

ENDCASE;

ENDIF;

ENDprocessseq;

comb:PROCESS(reset,status)

BEGIN

IF(reset='1'ANDstatus=5ANDIR(15DOWNTO12)=Write)THEN

Write_Read<=T;

ELSE

Write_Read<='O';

ENDIF;

ENDPROCESScomb;

Maddress<=MAR;

M_data_out<=MDR;

ENDRTL;

3.仿真波形图

clock

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国R3

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图3波形图1

clocknjumnRRnnmuuuuuuinnrLnruuuumnRnnnrLnjuumnnnRnjuuuuuu

reset

回0g：IMS\“qA(99X32xgIX20X64Xqq

回c^n2'inttrcIOOXTCOXroo080)KOX⑸/C8OX划X网X680XEmX】3X划X580XD80

回cpr£：iRst\"QWwX20X03XWXODXR

回cpxi2.iast\5<-qRI99X32X64

(21“G.IANUQK200X20XuX22

回ep«<2:inti\<MKJ8X次

回eyt^'iikttIK8WOX5100X2800X21doX?KK)XDOCO丫101XX1900XDCCOXwinXCOOJXBOOXFOOO

回CJ^12in»t■ABf,OJDXootX81x010XOUX012x013加*OMXOFX016X017加*018X019KCIA

囹cpu2：iftstWDR99

回cp砂.i皿status

回■_44dr・“(13XHX>x1®X17X18X>9»0X20X2.X笠X23/欲24X”X»

(399

回Lq84X51X28X2DX?BXroXIEXco速X19XWXIDX田弟以13XF。X00

“erfl”

Vialw-R«d

图4波形图2

解释如卜.:

操作码OP指令指令的助记符操作的内容

1R(15..12)格式

00003Idle无操作，PC：=PC+I：(为取下一条指令准

备地址)

00012LoadDataR0-I；(立即数I送R0)PC：=PC+1

00101MoveRx.RyRx-(Ry);PCFPC+1

0011