TI-双向 IO用隔离芯片-低速

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SLLSEB6D–JULY2012–REVISEDDECEMBERISO154xLow-PowerBidirectionalI2C IsolatedBidirectional,I2CCompatible,Supportsupto1-MHz3-Vto5.5-VSupplyOpen-DrainOutputsWith3.5-mASide1and35-mASide2SinkCurrentCapability–40°Cto+125°COperating±50-kV/µsTransientImmunityHBMESDProtectionof4kVonAllPins;8kVonBusPinsSafety-Related4242-VPKIsolationperDINVVDEV0884-10(VDEV0884-10):2006-122500-VRMSIsolationfor1MinuteperULCSAComponentAcceptanceNotice5A,IEC60950-1andIEC61010-1EndEquipmentCQCBasicInsulationperGB4943.1-IsolatedI2CSMBusandPMBusOpen-DrainMotorControlBatteryI2CLevel

TheISO1540andISO1541devicesarelow-power,bidirectionalisolatorsthatarecompatiblewithI2Cinterfaces.ThesedeviceshavelogicinputandoutputbuffersthatareseparatedbyTexasInstrumentsCapacitiveIsolationtechnologyusingasilicondioxide(SiO2)barrier.Whenusedwithisolatedpowersupplies,thesedevicesblockhighvoltages,isolategrounds,andpreventnoisecurrentsfromenteringthelocalgroundandinterferingwithordamagingsensitivecircuitry.Thisisolationtechnologyprovidesforfunction,performance,size,andpowerconsumptionadvantageswhencomparedtooptocouplers.TheISO1540andISO1541devicesenableacompleteisolatedI2Cinterfacetobeimplementedwithinasmallformfactor.TheISO1540hastwoisolatedbidirectionalchannelsforclockanddatalineswhiletheISO1541hasabidirectionaldataandaunidirectionalclockchannel.TheISO1541isusefulinapplicationsthathaveasinglemasterwhiletheISO1540issuitableformulti-masterapplications.Forapplicationswhereclockstretchingbytheslaveispossible,theISO1540deviceshouldbeused.Isolatedbidirectionalcommunicationisaccomplishedwithinthesedevicesbyoffsettingthelow-leveloutputvoltageonside1toavaluegreaterthanthehigh-levelinputvoltageonside1,thuspreventinganinternallogiclatchthatotherwisewouldoccurwithstandarddigitalisolators.DevicePARTBODYSIZESOIC4.90mm×3.91Forallavailablepackages,seetheorderableaddendumattheendofthedatasheet.IsolationSimplifiedIsolationororAnIMPORTANTNOTICEattheendofthisdatasheetaddressesavailability,warranty,changes,useinsafety-criticalapplications,intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.SLLSEB6D–JULY2012–REVISEDDECEMBERSLLSEB6D–JULY2012–REVISEDDECEMBERSubmitSubmitDocumentationCopyright©2012–2016,TexasInstrumentsProductFolderLinks:ISO1540SubmitDocumentationSubmitDocumentationCopyright©2012–2016,TexasInstrumentsProductFolderLinks:ISO1540Tableof Revision PinConfigurationand AbsoluteMaximum ESD RecommendedOperating Thermal Power Insulation Safety-Related SafetyLimiting Electrical SupplyCurrent Timing Switching InsulationCharacteristics Typical ParameterMeasurement Detailed

FunctionalBlock Feature IsolatorFunctional DeviceFunctional Applicationand Application Typical PowerSupply Layout Layout DeviceandDocumentation Documentation Related ReceivingNotificationofDocumentationUpdatesCommunity ElectrostaticDischarge Mechanical,Packaging,andOrderable RevisionNOTE:PagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentChangesfromRevisionC(June2015)toRevision DeletedtheDeviceComparisonTable;seetheFeaturesListtablefordevice ChangedthestatusofCQCcertificationfromplannedto ChangedtheRegulatoryInformationtabletoSafety-RelatedCertificationsandupdated Changedformattingofsupplycurrentparameterstocombinedeviceandsides.Movedparameterstoseparate AddedtheReceivingNotificationofDocumentationUpdates ChangesfromRevisionB(May2013)toRevision AddedPinConfigurationandFunctionssection,ESDRatingstable,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementationsection,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,andMechanical,Packaging,andOrderableInformation VDEStandardchangedtoDINVVDEV0884-10(VDEV0884-10):2006- Changedminimumairgap(Clearance)parameter,L(I01),toexternalclearance,CLR,andminimumtracking(creepage)parameter,L(I02),toexternal ChangedvaluesandtestconditionsintheInsulationSpecifications ChangedthedescriptionsofVDEandCSA ChangesfromRevisionA(October2012)toRevision ChangeSafetyFeatureFrom:(VDE0884Part2)(Pending)To:(VDE0884Part2) Changed,VDEcolumnFrom:Filenumber:40016131(pending)To:Filenumber: ChangesfromOriginal(July2012)toRevision ChangedFrom:CSAComponentAcceptanceNotice5A(Pending)To:CSAComponentAcceptanceNotice5A ChangedFrom:IEC60950-1andIEC61010-1EndEquipmentStandards(Pending)To:IEC60950-1and61010-1EndEquipmentStandards ChangedSafety-RelatedCertifications,CSAcolumnFrom:Filenumber:220991(pending)To:Filenumber: PinConfigurationandISO1540DPackage8-PinSOICTop Side1Nottoscale

SidePinFunctions—Ground,sideGround,sideSerialclockinput/output,sideSerialclockinput/output,sideSerialdatainput/output,sideSerialdatainput/output,sideSupplyvoltage,sideSupplyvoltage,sideISO1541DPackage8-PinSOICTop Side1Nottoscale

SidePinFunctions—Ground,sideGround,sideSerialclockinput,sideSerialclockoutput,sideSerialdatainput/output,sideSerialdatainput/output,sideSupplyvoltage,sideSupplyvoltage,sideAbsoluteMaximumoveroperatingfree-airtemperaturerange(unlessotherwiseVCC1,SDA1,VCC1+SDA2,VCC2+OutputSDA1,SDA2,MaximumjunctionStorageStressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratingsonly,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.Allvoltagevaluesherewithinarewithrespecttothelocalgroundpin(GND1orGND2)andarepeakvoltageMaximumvoltagemustnotexceed6ESD ElectrostaticHumanbodymodel(HBM),perANSI/ESDA/JEDECBusAllCharged-devicemodel(CDM),perJEDECspecificationJESD22-MachineModelJEDECJESD22-A115-A,allJEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolJEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolRecommendedOperatingVCC1,SupplyVSDA1,Inputandoutputsignalvoltages,sideVSDA2,Inputandoutputsignalvoltages,sideLow-levelinputvoltage,sideHigh-levelinputvoltage,side0.7×Low-levelinputvoltage,side0.3×High-levelinputvoltage,side0.7×Outputcurrent,sideOutputcurrent,sideCapacitiveload,sideCapacitiveload,sideOperatingAmbientJunctionThermal(1)Thisrepresentsthemaximumfrequencywiththemaximumbusload(C)andthemaximumcurrentsink(IO).Ifthesystemhaslessbuscapacitance,thenhigherfrequenciescanbeachieved.ThermalTHERMALD8Junction-to-ambientthermalJunction-to-case(top)thermalJunction-to-boardthermalJunction-to-case(bottom)thermal(1)Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplicationreport(SPRA953).PowerTEST Maximumpowerdissipation(bothVCC1=VCC2=5.5V,TJ=150°C,C1=40pF,C2=400pF;Inputa1-MHz50%dutycycleclock Maximumpowerdissipation(side- Maximumpowerdissipation(side-InsulationTESTExternalShortestterminal-to-terminaldistancethroughExternalShortestterminal-to-terminaldistanceacrossthepackagesurfaceDistancethroughtheMinimuminternalgap(internalDINEN60112(VDE0303-11);IECMaterialOvervoltageRatedmainsvoltage≤150Ratedmainsvoltage≤300DINVVDEV0884-10(VDEV0884-10):2006-MaximumrepetitivepeakisolationACvoltageMaximumtransientisolationVTEST=t=60st=1s(100%ApparentMethoda:AfterI/Osafetytestsubgroup2/3,Vini=VIOTM,tini=60s;Vpd(m)=1.2×VIORM=680VPK,tm=10Methoda:Afterenvironmentaltestssubgroup1,Vini=VIOTM,tini=60s;Vpd(m)=1.6×VIORM=906VPK,tm=10sMethodb1:Atroutinetest(100%production)andpreconditioning(typetest)Vini=VIOTM,tini=1s;Vpd(m)=1.875×VIORM=1062VPK,tm=1sBarriercapacitance,inputtooutputVIO=0.4sin(2πft),f=1Isolationresistance,inputtooutputVIO=500V,TA=VIO=500V,100°C≤TA≤VIO=500VatTS=PollutionClimaticULWithstandisolationVTEST=VISO=2500VRMS,t=60s(qualification);VTEST=1.2×VISO=3000VRMS,t=1s(100%Creepageandclearancerequirementsshouldbeappliedaccordingtothespecificequipmentisolationstandardsofanapplication.Careshouldbetakentomaintainthecreepageandclearancedistanceofaboarddesigntoensurethatthemountingpadsoftheisolatorontheprinted-circuitboarddonotreducethisdistance.Creepageandclearanceonaprinted-circuitboardbecomeequalincertaincases.Techniquessuchasinsertinggroovesand/orribsonaprintedcircuitboardareusedtohelpincreasethesespecifications.Thiscouplerissuitableforbasicelectricalinsulationonlywithinthemaximumoperatingratings.Compliancewiththesafetyratingsshallbeensuredbymeansofsuitableprotectivecircuits.ApparentchargeiselectricaldischargecausedbyapartialdischargeAllpinsoneachsideofthebarriertiedtogethercreatingatwo-terminalSafety-RelatedCertifiedaccordingtoDINVVDEV0884-10(VDEV0884-10):2006-12andDINEN61010-1ApprovedunderCSAComponentAcceptanceNotice5A,CSA/IEC60950-1,andCSA/IEC61010-1RecognizedunderUL1577ComponentRecognitionCertifiedaccordingtoGB4943.1-BasicMaximumTransientOvervoltage,4242VPK;MaximumRepetitivePeakVoltage,566VPK2.8-kVRMSInsulationRating;400VRMSBasicInsulationworkingvoltageperCSA60950-1-07+A1+A2andIEC60950-12nd300VRMSBasic,150ReinforcedInsulationworkingvoltageperCSA61010-1-12andIEC61010-13rdEd.,Singleprotection,2500BasicInsulation,Altitude≤5000m,TropicalClimate,250VRMSmaximumworkingvoltageMastercontractnumber:Filenumber:Certificatenumber:SafetyLimitingSafetylimitingintendstominimizepotentialdamagetotheisolationbarrieruponfailureofinputoroutputcircuitry.AfailureoftheI/Ocanallowlowresistancetogroundorthesupplyand,withoutcurrentlimiting,dissipatesufficientpowertooverheatthedieanddamagetheisolationbarrier,potentiallyleadingtosecondarysystemfailures.TEST Safetyinput,output,orsupplyRθJA=114.6°C/W,VI=5.5V,TJ=150°C,TA=seeFigureRθJA=114.6°C/W,VI=3.6V,TJ=150°C,TA=seeFigure SafetyThesafety-limitingconstraintisthemaximumjunctiontemperaturespecifiedinthedatasheet.Thepowerdissipationandjunction-to-airthermalimpedanceofthedeviceinstalledintheapplicationhardwaredeterminesthejunctiontemperature.Theassumedjunction-to-airthermalresistanceintheThermalInformationtableisthatofadeviceinstalledonahigh-Ktestboardforleadedsurface-mountpackages.Thepoweristherecommendedmaximuminputvoltagetimesthecurrent.Thejunctiontemperatureisthentheambienttemperatureplusthepowertimesthejunction-to-airthermalresistance.Electricaloverrecommendedoperatingconditions,unlessotherwiseTESTSIDE1Voltageinputthresholdlow,SDA1andSCL1Voltageinputthresholdhigh,SDA1andSCL1VoltageinputVIHT1Low-leveloutputvoltage,SDA1andSCL1(1)0.5mA≤(ISDA1andISCL1)≤3.5Low-leveloutputvoltagetohigh-levelinputvoltagethresholddifference,SDA1andSCL1(1)(2)0.5mA≤(ISDA1andISCL1)≤3.5SIDE2 Voltageinputthresholdlow,SDA2andSCL20.3×0.4×Voltageinputthresholdhigh,SDA2andSCL20.4×0.5×VoltageinputVIHT2–0.05×Low-leveloutputvoltage,SDA2andSCL20.5mA≤(ISDA2andISCL2)≤35BOTH Inputleakagecurrents,SDA1,SCL1,SDA2,andSCL2VSDA1,VSCL1=VCC1;VSDA2,VSCL2= Inputcapacitancetolocalground,SDA1,SCL1,SDA2,andSCL2VI=0.4×sin(2E6πt)+2.5SeeFigureVCCundervoltagelockoutThisparameterdoesnotapplytotheISO1541SCL1lineasitis∆VOIT1=VOL1–VIHT1.ThisrepresentstheminimumdifferencebetweenaLow-LevelOutputVoltageandaHigh-LevelInputVoltageThresholdtopreventapermanentlatchconditionthatwouldotherwiseexistwithbidirectionalcommunication.AnyVCCvoltages,oneitherside,lessthantheminimumwillensuredevicelockout.BothVCCvoltagesgreaterthanthemaximumwillpreventdevicelockout.SupplyCurrentoverrecommendedoperatingconditions,unlessotherwisenoted.Formoreinformation,seeFigureTEST3V≤VCC1,VCC2≤3.6Supplycurrent,sideVSDA1,VSCL1=GND1;VSDA2,VSCL2=GND2;R1,R2=Open;C1,C2=OpenVSDA1,VSCL1=VCC1;VSDA2,VSCL2=VCC2;R1,R2=Open;C1,C2=OpenVSDA1,VSCL1=GND1;VSDA2,VSCL2=GND2;R1,R2=Open;C1,C2=OpenVSDA1,VSCL1=VCC1;VSDA2,VSCL2=VCC2;R1,R2=Open;C1,C2=OpenSupplycurrent,sideISO1540andVSDA1,VSCL1=GND1;VSDA2,VSCL2=GND2;R1,R2=Open;C1,C2=OpenVSDA1,VSCL1=VCC1;VSDA2,VSCL2=VCC2;R1,R2=Open;C1,C2=Open4.5V≤VCC1,VCC2≤5.5Supplycurrent,sideVSDA1,VSCL1=GND1;VSDA2,VSCL2=GND2;R1,R2=Open;C1,C2=OpenVSDA1,VSCL1=VCC1;VSDA2,VSCL2=VCC2;R1,R2=Open;C1,C2=OpenVSDA1,VSCL1=GND1;VSDA2,VSCL2=GND2;R1,R2=Open;C1,C2=OpenVSDA1,VSCL1=VCC1;VSDA2,VSCL2=VCC2;R1,R2=Open;C1,C2=OpenSupplycurrent,sideISO1540andVSDA1,VSCL1=GND1;VSDA2,VSCL2=GND2;R1,R2=Open;C1,C2=OpenVSDA1,VSCL1=VCC1;VSDA2,VSCL2=VCC2;R1,R2=Open;C1,C2=Open TimingInputnoiseTimetorecoverfrom2.7Vto0.9V;SeeFigureSwitchingoverrecommendedoperatingconditions,unlessotherwiseTEST3V≤VCC1,VCC2≤3.6OutputSignalFallTime(SDA1,SCL1)SeeFigure19R1=953Ω,C1=40pF0.7×VCC1to0.3×0.9×VCC1to900OutputSignalFallTime(SDA2,SCL2)SeeFigure19R2=95.3Ω,C2=400pF0.7×VCC2to0.3×0.9×VCC2to400SeeFigure19R1=953Ω,R2=95.3Ω,C1,C2=10pF0.55Vto0.7×Delay,Side1toSide0.7Vto0.4Delay,Side1toSidePulseWidth|tpHL1-2–tpLH1- 0.4×VCC2to0.7×Delay,Side2toSide 0.4×VCC2to0.9Delay,Side2toSidePWDPulseWidth|tpHL2-1–tpLH2-Round-trippropagationdelayonSide1SeeFigureR1=953Ω,C1=40pFR2=95.3Ω,C2=400pF0.4Vto0.3×4.5V≤VCC1,VCC2≤5.5 OutputSignalFallTime(SDA1,SCL1)SeeFigure19R1=1430Ω,C1=40pF0.7×VCC1to0.3×0.9×VCC1to900OutputSignalFallTime(SDA2,SCL2)SeeFigure19R2=143Ω,C2=400pF0.7×VCC2to0.3×0.9×VCC2to400SeeFigure19R1=1430Ω,R2=143Ω,C1,2=10pF0.55Vto0.7×Delay,Side1toSide0.7Vto0.4Delay,Side1toSidePulseWidth|tpHL1-2–tpLH1- 0.4×VCC2to0.7×delay,side2toside 0.4×VCC2to0.9delay,Side2tosidePWDPulseWidth|tpHL2-1–tpLH2-Round-trippropagationdelayonside1SeeFigureR1=1430Ω,C1=40pFR2=143Ω,C2=4000.4Vto0.3×(1)ThisparameterdoesnotapplytotheISO1541SCL1lineasitisInsulationCharacteristicsVCC1VCC1=VCC2=3.6VVCC1=VCC2=5.5SafetySafetyLimitingCurrent AmbientTemperatureFigure1.ThermalDeratingCurveforLimitingCurrentperTypicalOutputOutputVoltage,VOL1

I=3.5mAI=0.5

OutputOutputCurrent,IOL1-

0.1

−40−25−10 203550658095110Free−AirTemperature

TA=

AppliedVoltage,VSDA1,VSCL1Figure2.Side1:OutputLowVoltagevsFree-Air

Figure3.Side1:OutputLowCurrentvsSDA1orSCL1AppliedVoltage FallTime,tFallTime,tf1FallTime,tf1 R1=953 R1=2.2

R1=1430R1=2.2-40-25- 203550658095110 -40-25- 203550658095110

VCC1=3.3 C1=40Falltimemeasuredfrom70%to30%Figure4.Side1:OutputFallTimevsFree-Air

VCC1=5 C1=40Falltimemeasuredfrom70%to30%Figure5.Side1:OutputFallTimevsFree-air FallTimetFallTimetf2FallTimetf2 R2=95.3R2=2.2

R2=143R2=2.2-40-25- 203550658095110 -40-25- 203550658095110

VCC2=3.3 C2=400Falltimemeasuredfrom70%to30%Figure6.Side2:OutputFallTimevsFree-Air

VCC2=5 C2=400Falltimemeasuredfrom70%to30%Figure7.Side2:OutputFallTimevsFree-AirTypicalCharacteristicsPropagationPropagationDelay,tPLH1-2

PropagationPropagationDelay,tPHL1-2 VCC1andVCC2=3.3V,R2=95.3VCC1andVCC2=5V,R2=143

VCC1andVCC2=3.3V,R2=95.3VCC1andVCC2=5V,R2=143-40-25- 203550658095110 -40-25- 203550658095110C2=10

C2=10

Figure8.tPLH1-2PropagationDelayvsFree-AirVCC1andVCC2=3.3

Figure9.tPHL1-2PropagationDelayvsFree-Air

VCC1andVCC2=5 PropagationPropagationDelay,tPHL1-2

VCC1andVCC2=3.3VVCC1andVCC2=5V-40-25- 203550658095110 -40-25- 203550658095110R2=2.2 C2=400

R2=2.2 C2=400

Figure10.tPLH1-2PropagationDelayvsFree-AirPropagationPropagationDelay,tPHL2-1 VCC1andVCC2=3.3V,R1=953VCC1andVCC2=5V,R1=1430

Figure11.tPHL1-2PropagationDelayvsFree-AirPropagationPropagationDelay,tPHL2-1 VCC1andVCC2=3.3V,R1=953VCC1andVCC2=5V,R1=1430-40-25- 203550658095110 -40-25- 203550658095110C1=10

C1=10

Figure12.tPLH2-1PropagationDelayvsFree-Air

Figure13.tPHL2-1PropagationDelayvsFree-AirTypicalCharacteristics PropagationPropagationDelay,tPLH2-1

PropagationPropagationDelay,tPHL2-1VCC1andVCC2=3.3VCC1andVCC2=5

VCC1andVCC2=3.3VVCC1andVCC2=5V-40-25- 203550658095110 R1=2.2 C1=40Figure14.tPLH2-1PropagationDelayvsFree-Air

−40−25 95110Free-AirTemperatureR1=2.2 C1=40Figure15.tPHL2-1PropagationDelayvsFree-AirtLOOP1tLOOP1

tLOOP1tLOOP1 VCC1andVCC2=3.3V,R1=953Q,R2=95.3VCC1andVCC2=5V,R1=1430Q,R2=143

VCC1andVCC2=3.3VVCC1andVCC2=5V-40-25- 203550658095110 -40-25- 203550658095110Free-AirTemperatureC1=40 C2=400Figure16.tLOOP1vsFree-Air

C1=40 C2=400R1=2.2 R2=2.2Figure17.tLOOP1vsFree-Air

VCC1andVCC2=3.3VCC1andVCC2=5-40-25- 203550658095110

Figure18.CMTIvsFree-AirParameterMeasurement

Copyright©2016,TexasInstrumentsFigure19.TestSDA1or

SCL1SCL1(ISO15400.30.4Copyright©2016,TexasInstrumentsFigure20.tLoop1SetupandTiming 22Figure21.Common-ModeTransientImmunityTestParameterMeasurementInformationSDAxorSDAxorSidex,Side1,3.3V,3.395.32,3.3V,3.3953I0ISDAxSDAx0Figure22.tUVLOTestCircuitandTimingDetailedTheI2Cbusisusedinawiderangeofapplicationsbecauseitissimpletouse.Thebusconsistsofatwo-wirecommunicationbusthatsupportsbidirectionaldatatransferbetweenamasterdeviceandseveralslavedevices.Themaster,orprocessor,controlsthebus,specificallytheserialclock(SCL)line.Dataistransferredbetweenthemasterandslavethroughaserialdata(SDA)line.Thisdatacanbetransferredinfourspeeds:standardmode(0to100kbps),fastmode(0to400kbps),fast-modeplus(0to1Mbps),andhigh-speedmode(0to3.4Mbps).Themostcommonspeedsarethestandardandfastmodes.TheI2Cbusoperatesinbidirectional,half-duplexmode,whilestandarddigitalisolatorsareunidirectionaldevices.Tomakeefficientuseofonetechnologysupportingtheother,externalcircuitryisrequiredthatseparatesthebidirectionalbusintotwounidirectionalsignalpathswithoutintroducingsignificantpropagationdelay.ThesedeviceshavetheirlogicinputandoutputbuffersseparatedbyTI'scapacitiveisolationtechnologyusingasilicondioxide(SiO2)barrier.Whenusedinconjunctionwithisolatedpowersupplies,thesedevicesblockhighvoltages,isolategrounds,andpreventnoisecurrentsfromenteringthelocalgroundandinterferingwithordamagingsensitivecircuitry.IsolationFigure23.ISO1540BlockFunctionalBlockDiagramsIsolationFeatureThedeviceenablesacompleteisolatedI2CinterfacetobeimplementedwithinasmallformfactorhavingthefeatureslistedinTable1.Table1.FeaturesPARTCHANNELRATEDMAXIMUMBidirectional(SCL)Bidirectional250042421Unidirectional(SCL)(1)SeeSafety-RelatedCertificationsfordetailedIsolationIsolatorFunctionalToisolateabidirectionalsignalpath(SDAorSCL),theISO1540internallysplitsabidirectionallineintotwounidirectionalsignallines,eachofwhichisisolatedthroughasingle-channeldigitalisolator.Eachchanneloutputismadeopen-draintocomplywiththeopen-draintechnologyofI2C.Side1oftheISO1540connectstoalow-capacitanceI2Cnode,whileside2isdesignedforconnectingtoafullyloadedI2Cbuswithupto400pFof40504050

Copyright©2016,TexasInstrumentsFigure25.SDAChannelDesignandVoltageLevelsatIsolatorFunctionalPrincipleAtfirstsight,thearrangementoftheinternalbufferssuggestsaclosedsignalloopthatispronetolatch-up.However,thisloopisbrokenbyimplementinganoutputbuffer(B)whoseoutputlow-levelisraisedbyadiodedroptoapproximately0.75V,andtheinputbuffer(C)thatconsistsofacomparatorwithdefinedhysteresis.Thecomparator’supperandlowerinputthresholdsthendistinguishbetweentheproperlow-potentialof0.4V(maximum)drivendirectlybySDA1andthebufferedoutputlow-levelofB.Figure26demonstratetheswitchingbehavioroftheI2Cisolator,ISO1540,betweenamasternodeatSDA1andaheavyloadedbusatSDA2.

Figure26.SDAChannelTiminginReceiveandTransmitReceiveDirection(LeftDiagramofFigureWhentheI2CbusdrivesSDA2low,SDA1followsafteracertaindelayinthereceivepath.TheoutputlowisthebufferedoutputofVOL1=0.75V,whichissufficientlylowtobedetectedbySchmitt-triggerinputswithaminimuminput-lowvoltageofVIL=0.9Vat3Vsupplylevels.WhenSDA2isreleased,itsvoltagepotentialincreasestowardsVCC2followingthetime-constantformedbyRPU2andCbus.Afterthereceivedelay,SDA1isreleasedandalsorisestowardsVCC1,followingthetime-constantRPU1×Cnode.Becauseofthesignificantlowertime-constant,SDA1mayreachVCC1beforeSDA2reachesVCC2potential.TransmitDirection(RightDiagramofFigureWhenamasterdrivesSDA1low,SDA2followsafteracertaindelayinthetransmitdirection.WhenSDA2turnslowitalsocausestheoutputofbufferBtoturnlowbutatahigher0.75Vlevel.Thislevelcannotbeobservedimmediatelyasitisoverwrittenbythelowerlow-levelofthemaster.However,whenthemasterreleasesSDA1,thevoltagepotentialincreasesandfirstmustpasstheupperinputthresholdofthecomparator,VIHT1,toreleaseSDA2.SDA1thenincreasesfurtheruntilitreachesthebufferedoutputlevelofVOL1=0.75V,maintainedbythereceivepath.WhencomparatorCturnshigh,SDA2isreleasedafterthedelayintransmitdirection.IttakesanotherreceivedelayuntilB’soutputturnshighandfullyreleasesSDA1tomovetowardVCC1potential.DeviceFunctionalTable2liststheISO154xfunctionalTable2.FunctionPOWERVCC1orVCC2<2.1VCC1andVCC2>2.8VCC1andVCC2>2.8VCC1andVCC2>2.8H=HighLevel;L=LowLevel;Z=HighImpedanceorFloat;X=Irrelevant;?=InvalidinputconditionasanI2CsystemrequiresthatapullupresistortoVCCisApplicationandInformationinthefollowingapplicationssectionsisnotpartoftheTIcomponentspecification,andTIdoesnotwarrantitsaccuracyorcompleteness.TI’scustomersareresponsiblefordeterminingsuitabilityofcomponentsfortheirpurposes.Customersshouldvalidateandtesttheirdesignimplementationtoconfirmsystemfunctionality.ApplicationI2CBusTheinter-integratedcircuit(I2C)busisasingle-ended,multi-master,2-wirebusforefficientinter-ICcommunicationinhalf-duplexmode.I2Cusesopen-draintechnology,requiringtwolines,serialdata(SDA)andserialclock(SCL),tobeconnectedtoVDDbyresistors(seeFigure27).Pullingthelinetogroundisconsideredalogiczerowhilelettingthelinefloatisalogicone.Thislogicisusedasachannelaccessmethod.TransitionsoflogicstatesmustoccurwhiletheSCLpinislow.TransitionswhiletheSCLpinishighindicateSTARTandSTOPconditions.Typicalsupplyvoltagesare3.3Vand5V,althoughsystemswithhigherorlowervoltagesareallowed. C

Figure27.I2C

CI2Ccommunicationusesa7-bitaddressspacewith16reservedaddresses,soatheoreticalmaximumof112nodescancommunicateonthesamebus.Inpraxis,however,thenumberofnodesislimitedbythespecified,totalbuscapacitanceof400pF,whichrestrictscommunicationdistancestoafewmeters.ThespecifiedsignalingratesfortheISO1540andISO1541devicesare100kbps(standardmode),400kbps(fastmode),1Mbps(fastmodeplus).Thebushastworolesfornodes:masterandslave.Amasternodeissuestheclockandslaveaddresses,andalsoinitiatesandendsdatatransactions.Aslavenodereceivestheclockandaddressesandrespondstorequestsfromthemaster.Figure28showsatypicaldatatransferbetweenmasterandslave.ACK/1-1-1-

Figure28.TimingDiagramofaCompleteData

ThemasterinitiatesatransactionbycreatingaSTARTcondition,followingbythe7-bitaddressoftheslaveitwishestocommunicatewith.Thisisfollowedbyasinglereadandwrite(R/W)bit,representingwhetherthemasterwishestowriteto0,ortoreadfrom1theslave.ThemasterthenreleasestheSDAlinetoallowtheslavetoacknowledgethereceiptofdata.Theslaverespondswithanacknowledgebit(ACK)bypullingtheSDApinlowduringtheentirehightimeofthe9thclockpulseontheSCLsignal,afterwhichthemastercontinuesineithertransmitorreceivemode(accordingtotheR/Wbitsent),whiletheslavecontinuesinthecomplementarymode(receiveortransmit,respectively).Theaddressandthe8-bitdatabytesaresentmostsignificantbit(MSB)first.TheSTARTbitisindicatedbyahigh-to-lowtransitionofSDAwhileSCLishigh.TheSTOPconditioniscreatedbyalow-to-hightransitionofSDAwhileSCLishigh.Ifthemasterwritestoaslave,itrepeatedlysendsabytewiththeslavesendinganACKbit.Inthiscase,themasterisinmaster-transmitmodeandtheslaveisinslave-receivemode.Ifthemasterreadsfromaslave,itrepeatedlyreceivesabytefromtheslave,whileacknowledging(ACK)thereceiptofeverybytebutthelastone(seeFigure29).Inthissituation,themasterisinmaster-receivemodeandtheslaveisinslave-transmitmode.ThemasterendsthetransmissionwithaSTOPbit,ormaysendanotherSTARTbittomaintainbuscontrolforfurthertransfers.FromMastertoSlaveFromSlaveto

MasterTransmitterwritingtoSlaveMasterReceiverreadingfromSlave

A=A=notacknowledgeS=StartSlaveSlaveSlaveFigure29.TransmitorReceiveModeChangesDuringaDataWhenwritingtoaslave,amastermainly