时序电路-06C(时序电路VHDL设计典型实例)

数字电路与逻辑设计二、常用时序逻辑电路设计（1）触发器设计（D、JK）（2）计数器设计（分频器）（3）移位寄存器设计（4）状态机设计：序列检测器

Process的物理意义Process进程

由敏感信号触发，并以Process结束为时间分界点，实现信号的初态到次态的转换。分界点以前引用信号的当前值（初态值），并通过赋值语句指定信号的次态值；分界点以后，次态值生效。时序电路VHDL描述方法状态方程法

确定敏感信号，用信号初态值和其他输入表示出次态值，然后代入赋值语句。状态表法确定敏感信号，按一定规则列出状态转换表，逐行描述或多行概括描述。（1）触发器设计DQCLKCLKDQn+1无变化XQn0->1000->111D触发器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYdffISPORT(clk,d:INSTD_LOGIC;q:OUTSTD_LOGIC);ENDdff;ARCHITECTUREaOFdffISBEGINprocess(clk)beginif(clk'eventandclk='1')thenq<=d;endif;endprocess;ENDa;状态方程：

J-K触发器特性表JKQn+1功能说明00011011Qn01Qn不变置0置1翻转JK触发器cpCLKI.依据状态方程实现JK触发器Libraryieee;USEieee.std_logic_unsigned.ALL;USEieee.std_logic_arith.ALL;entityjkjkisport(j,k,clk:instd_logic;Q,nQ:bufferstd_logic);endjkjk;buffer端口模式：端口既作为实体的输出，又回到实体内部做驱动信号。architecturebhofjkjkisbegin

process(clk)

begin

if(clk'eventandclk='0')thenQ<=(jand(notQ))OR((notk)andQ);nQ<=not((jand(notq))OR((notk)andq));

endif;

end

process;endbh;II.依据状态转换表实现JK触发器Libraryieee;USEieee.std_logic_unsigned.ALL;USEieee.std_logic_arith.ALL;entityjkjkisport(j,k,clk:instd_logic;Q,nQ:bufferstd_logic);endjkjk;architecturebh2ofjkjk1isbegin

process(clk)

begin

if(clk'eventandclk='0')then

ifj='0'andk='1'thenq<='0';nq<='1';

elsifj='1'andk='0'thenq<='1';nq<='0';

elsifj='0'andk='0'thenq<=q;nq<=nq;

elsifj='1'andk='1'thenq<=notq;nq<=notnq;

endif;

endif;

endprocess;endbh2;(2)-A简单计数器设计计数器CLKQ3Q2Q1Q0四位加计数器LIBRARYieee;USEieee.std_logic_1164.ALL;USEieee.std_logic_unsigned.ALL;USEieee.std_logic_arith.ALL;ENTITYcounterISPORT(clk:inSTD_LOGIC;q:buffer

STD_LOGIC_vector(3downto0));ENDcounter;ARCHITECTUREaOFcounterISBEGIN

process(clk)

begin

if(clk'eventandclk='1')thenq<=q+1;

endif;

endprocess;ENDa;四位加计数器计数器CLKCLR(2)-B带同步清零、同步置数功能的计数器LDQ3Q2Q1Q0D3D2D1D0控制信号CLR、LD：具有更高优先级LIBRARYieee;USEieee.std_logic_1164.ALL;USEieee.std_logic_unsigned.ALL;USEieee.std_logic_arith.ALL;ENTITYcounterISPORT(clk,clr,ld:inSTD_LOGIC;d:inSTD_LOGIC_vector(3downto0);q:bufferSTD_LOGIC_vector(3downto0));ENDcounter;ARCHITECTUREaOFcounterISBEGIN

process(clk)

begin

if(clk'eventandclk='1')thenif(clr='1')then

q<="0000";elsif(ld='1')thenq<=d;

elseq<=q+1;

endif;endif;endprocess;ENDa;计数器CLKCLR(2)-C带异步清零、同步置数功能的计数器LDQ3Q2Q1Q0D3D2D1D0LIBRARYieee;USEieee.std_logic_1164.ALL;USEieee.std_logic_unsigned.ALL;USEieee.std_logic_arith.ALL;ENTITYcounterISPORT(clk,clr,ld:inSTD_LOGIC;d:inSTD_LOGIC_vector(3downto0);q:bufferSTD_LOGIC_vector(3downto0));ENDcounter;ARCHITECTUREaOFcounterISBEGIN

process(clk,clr)begin

if(clr=‘1’)thenq<=“0000”;

elsif(clk'eventandclk='1'andld=‘1’)

then

q<=d;elsif(clk'eventandclk='1'andld=‘0’)

then

q<=q+1;endif;

endprocess;ENDa;process(clk,clr)begin

if(clr=‘1’)thenq<=“0000”;

else--即clr=‘0’

if(clk'eventandclk='1')

thenif(ld='1')then

q<=d;

elseq<=q+1;

endif;

endif;endif;

endprocess;ENDa;(2)-D带进位计数器设计计数器CLKQ3Q2Q1Q0四位加计数器COUTLIBRARYieee;USEieee.std_logic_1164.ALL;USEieee.std_logic_unsigned.ALL;USEieee.std_logic_arith.ALL;ENTITYcounterISPORT(clk:inSTD_LOGIC;q:buffer

STD_LOGIC_vector(3downto0);cout:outstd_logic);ENDcounter;ARCHITECTUREaOFcounterISBEGINARCHITECTUREbOFcounterISBEGINprocess(clk)begin

if(clk'eventandclk='1')thenq<=q+1;

endif;endprocess;cout<=‘1’whenq=15else‘0’;ENDb;进程设计状态转换并列语句实现输出计数器CLKQ3Q2Q1Q0带进位的十进制加计数器COUTARCHITECTUREbOFcounterISBEGINprocess(clk)begin

if(clk'eventandclk='1')then

if(q<9)thenq<=q+1;

elsif

q>=9q<=“0000”;

endif;

endif;endprocess;cout<=‘1’whenq=9else‘0’;ENDb;进程设计状态转换并列语句实现输出(2)-E分频器Tclk=1usTcout=10us计数器就是对时钟脉冲计数，同时计数器还是一个分频器。fclk=1x106Hzfcout=1x105Hz（3）移位寄存器设计4位右移移位寄存器Reset:异步清零右移移位寄存器dinresetclkQAQBQCQDlibraryieee;useieee.std_logic_1164.all;ENTITYshifterISPORT(

din:instd_logic;reset,clk:instd_logic;QA,QB,QC,QD:bufferstd_logic);

ENDshifter;ARCHITECTUREbehaveOFshifterISBEGINProcess(reset,clk)Begin

if(reset='1')

then

QA<='0';QB<='0';QC<='0';QD<='0';

else

if

(clk'Eventandclk='1')then

QA<=din;QB<=QA;QC<=QB;QD<=QC;

endif;

endif;endprocess;Endbehave;（4）“状态机”概念及设计

我们可以用输入信号X和电路状态Q来描述时序电路的逻辑功能，这时时序电路称为

状态机（StateMachine）。根据输出信号和输入信号以及电路状态的关系，状态机可以分为两种：穆尔（Moore）型和米利（Mealy）型。Y=F[X,Q]

Y=F[Q]

米利（Mealy）型：穆尔（Moore）型：典型状态机示例—序列信号检测器目标序列信号：“110”序列检测器CLKZdin序列信号检测器工作波形图S0S20/01/0S11/00/10/01/0Mealy型序列信号检测器—状态图序列信号：110Sdin/Z‘1’‘11’S0/0S2/001S1/0101Moore型序列信号检测器—状态图序列信号：110S/Zdin‘1’‘11’S3/1‘110’001LIBRARYieee;USEieee.std_logic_1164.ALL;ENTITYsqsISPORT(din,clk:inStd_logic;z:outStd_logic);ENDsqs;Mealy型-VHDL代码转换ARCHITECTUREaOF

sqsISTYPESTATE_TYPEIS(s0,s1,s2);SIGNALstate:STATE_TYPE;BEGIN

Mealy型-VHDL代码转换PROCESS(clk) BEGIN

If

（clk’EVENTANDclk=‘1’）thenCASEstateIS

WHENs0=>IFdin=‘1’

THENstate<=s1;

elsestate<=s0; ENDIF;

WHENs1=>IFdin=‘1'THENstate<=s2;

elsestate<=s0; ENDIF;

WHENs2=>IFdin='0'THENstate<=s0;

elsestate<=s2; ENDIF;

WHENothers=> state<=s0; ENDCASE;Endif;

ENDPROCESS;z<='1'when(state=s2anddin=’0’)else'0';

--输出不仅与状态有关，而且和输入有关。ENDa;

Mealy型-VHDL代码转换序列信号：110序列检测器CLKZdinRst状态机自启动：RST复位控制LIBRARYieee;USEieee.std_logic_1164.ALL;ENTITYsqsISPORT(Rst,din,clk:inStd_logic;z:outStd_logic);ENDsqs;ARCHITECTUREaOFsqsISTYPESTATE_TYPEIS(s0,s1,s2);SIGNALstate:STATE_TYPE;BEGIN

PROCESS(rst,clk) BEGINIf(Rst=‘1’)thenstate<=s0;elsif

（clk‘EVENTANDclk=’1‘）thenCASEstateIS

WHENs0=>IFdin=‘1’

THENstate<=s1;