数字电路系统设计中英文课件教程 05 组合逻辑设计实践- Combinational Logic Design Practices (2)

DIGITALSYSTEMDESIGNESHINEeshine.li@5.6Three-StateDevices

(三态器件)Three-StateBuffer(Three-StateDriver)

[三态缓冲器（三态驱动器）]ThreeStates:ActiveHigh(1)，ActiveLow(0),Hi-Z

(三种状态：高电平，低电平，高阻态）Variousthree-statebuffers:(a)noninverting,active-highenable;(b)non-inverting,active-lowenable;(c)inverting,active-highenable;(d)inverting,active-lowenable.5.6Three-StateDevices

(三态器件)Three-StateDeviceallowMultipleSourcestoShareaSingle“PartyLine“aslongasOnlyOnedevice“talk”ontheLineatatime三态器件允许多个信号源共享单个"同线",条件是每次只有一个器件工作Eightsourcessharingathree-statepartyline.5.6Three-StateDevices

(三态器件)TypicalThree-StateDevicesareDesignedSothattheygointotheHi-ZstateFasterthantheycomeoutoftheHi-Zstate.对典型的三态器件，进入高阻态比离开高阻态的时间快

5.6Three-StateDevices

(三态器件)74x125：activelow,noninverting

低电平使能，输出不反相74x126：activehigh,noninverting

高电平使能，输出不反相Independentenableinputs独立使能

StandardSSIandMSIThree-StateBuffer

(标准SSI和MSI三态缓冲器)Pinoutsofthe74x125and74x126threestatebuffers.5.6Three-StateDevices

(三态器件)

StandardSSIandMSIThree-StateBuffer

(标准SSI和MSI三态缓冲器)74x541：commonenableinputs,activelow两个公共使能端，低电平使能，Schmitttrigger,noninverting施密特触发输入，输出不反相The74x541octalthree-statebuffer:(a)logicdiagram,includingpinnumbersforastandard20-pindualin-linepackage;(b)traditionallogicsymbolABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138EN1EN2_LEN3_LSSRC0SSRC1SSRC2冲突（fighting）Designcontrollogicthatguaranteesadeadtimeduringwhichnooneisdrivingit.利用使能端进行时序控制Three-StateDeviceallowMultipleSourcestoShareaSingle“PartyLine“三态器件允许信号共享单个“同线”P0P1P7SDATATypicalThree-StateDevicesareDesignedsothattheygointotheHi-ZstateFasterthantheycomeoutoftheHi-Zstate.对典型的三态器件，进入高阻态比离开高阻态的时间快EN1EN2_L,EN3_Lmax(tpLZmax,tpHZmax)min(tpZLmin,tpZHmin)SSRC[2:0]01237SDATAP0P1P2P3P7DeadTime(截止时间)A1A8G1G2Y1Y874x541DB[0:7]A1A8G1G2Y1Y874x541NotationofDataBus（数据总线的表示法）A1B1DIRTransferDatainEitherDirectionsByUsingThree-StateTransceiver(利用三态缓冲器实现数据双向传送)BusTransceiver(总线收发)DIRG_L5.7Multiplexer（多路复用器）DigitalSwitch,Multi-Switch,DataSelector(又称数据开关、多路开关、数据选择器)（缩写：MUX）

UnderSelectControllingSignals,SelectOneoftheMulti-InputstotheOutput

(在选择控制信号的作用下，从多个输入数据中选择其中一个作为输出。)5.7Multiplexer（多路复用器）ENSELD0Dn-1YEnable使能Select选择N1bitDatasourcen个1位数据源Dataoutput(1bit)数据输出（1位）ENSELD0Dn-1YEnable(使能)Select(选择)NbbitsDataSourcesn个b位数据源DataOutput(bbits)(数据输出)（b位）EN_LCBAYY_L1XXX0000000100100011010001010110011101D0D0’D1D1’D2D2’D3D3’D4D4’D5D5’D6D6’D7D7’(8输入1位多路复用器)TruthTablefora74x151ABC8-Input,1-bitMultiplexerinput输入G_LS1X000100001A2A3A4A1B2B3B4B(2输入4位多路复用器)TruthTablefora74x157output输出1Y2Y3Y4Y1A2A3A4A2-Input,4-bitMultiplexer1G_L2G_LBA1Y2Y11XX000000010010001101000101011001111000100110101011

001C02C01C12C11C22C21C32C31C001C101C201C30

02C002C102C202C3(4输入2位多路复用器74x153真值表)AB1G2GTruthTablefora74x1534-Input,2-bitMultiplexerDual4-to-1双4选1ExpandingMultiplexers

(扩展多路复用器)ExpandingBit(扩展位)HowtoRealize8-Input,16-bitMultiplexer?

(如何实现8输入，16位多路复用器？)From8-Input,1-bitto8-Input,16-bit

(由8输入1位8输入16位)Need1674x151,EachChipProcess1-bit

(需要16片74x151，每片处理输入输出中的1位)ExpandingMultiplexers

(扩展多路复用器)ExpandingBit(扩展位)Select-InputsConnecttoC,B,AofEachChip(选择端连接到每片的C,B,A)Note:TheFanoutAbilityofSelectfield

(注意：选择端的扇出能力)（驱动16个负载）ENYYABCD0D7ExpandingMultiplexers

(扩展多路复用器)ExpandingInputs(扩展数据输入端的数目)Howtorealize32-Input,1-bitMultiplexer

(如何实现32输入，1位多路复用器？)Inputsfrom8to32,Need4chips

(数据输入由832，需4片)HowtocontrolSelectInputsByHighbitplusLowbit.

(如何控制选择输入端？

——分为：高位＋低位)ENYYABCD0D7ExpandingMultiplexers

(扩展多路复用器)ExpandingInputs(扩展数据输入端的数目)如何实现32输入，1位多路复用器？HighBitsplusDecoderasSelect

(高位＋译码器进行片选)LowBitsConnecttoC,B,AofeachChip

(低位接到每片的C,B,A)OutputUsingORGate(4片输出用或门得最终输出)ENYYABCD0D7ExpandingMultiplexers

扩展多路复用器Combining74x151stomakea32-to-1multiplexer.D0D1D2D3D4D5D6D7A0A1A2YDual4-to-1Multiplexerto8-to-1Multiplexer(用双4选1数据选择器构成8选1数据选择器)UseMultiplexertodesignlogiccircuit用数据选择器设计组合逻辑电路Whenenasserted当使能端有效时，ENABCD0D1D2D3D4D5D6D7YY74x151F=

(A,B,C)(0,1,3,7)CBAVCCF设计七段显示译码器逻辑抽象，得到真值表输入信号：BCD码（A3A2A1A0）输出：七段码（的驱动信号）a~g1表示亮，0表示灭选择器件类型采用基本门电路实现，利用卡诺图化简采用二进制译码器实现，变换为标准和形式采用数据选择器实现,变换为标准和形式电路处理，得到电路图abcdefg七段显示译码器的真值表00000001001000110100010101100111100010011010101111001101111011111111110011000011011011111001011001110110110011111111000011111111110011000110100110010100011100101100011110000000A3

A2

A1

A0abcdefg0123456789101112131415A1A0A3A200

01

11

10000111101011110010000101a用数据选择器74x151

实现逻辑函数F=

(X,Y,Z)(1,3,5,6)AClassProblem(每课一题)ENABCD0D1D2D3D4D5D6D7YY74x151YZWX00

01

11

10000111101111111YWX000111100110ZZZZZ’0Q:use74x151toimplementlogicfunction思考：利用74x151实现逻辑函数F=

(W,X,Y,Z)(0,1,3,7,9,13,14)reducingdimensions:4D-3D降维：由4维3维ENABCD0D1D2D3D4D5D6D7YY74x151VCCYXWFZUse利用74x151F=

(W,X,Y,Z)(0,1,3,7,9,13,14)0

2

6

41

3

7

5YWX000111100110ZZZZZ’0Note:nbitmultiplexercanimplementlogicfunctionofn+1bits说明：用具有n位地址输入端的多路复用器，可以产生任何形式的输入变量数不大于n+1的组合逻辑函数。Demultiplexer（多路分配器）Routethebusdatatooneofmdestinations

(把输入数据送到m个目的地之一)Multiplexer多路复用器SRCASRCBSRCZDemultiplexer多路分配器BUSDSTADSTBDSTZSRCSELDSTSELDST:destinationSRC:sourceSEL:selectDemultiplexer（多路分配器）MultiplexerSRCASRCBSRCZDemultiplexerBUSDSTADSTBDSTZSRCSELDSTSELAbinarydecoderwithanenableinputcanbeusedasademultiplexer(利用带使能端的二进制译码器作为多路分配器)ABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138DST0_LDST7_Lsource数据输入SRCEN_LDSTSEL0DSTSEL1DSTSEL2Destinationselection地址选择——

Enableinputisconnectedtothedataline

(利用使能端作为数据输入端)5.8ParityCircuit(奇偶校验电路)Odd-ParityCircuit（奇校验电路）Outputis1ifanoddnumberofitsinputsare1.

(如果输入有奇数个1，则输出为1。)Even-ParityCircuit（偶校验电路）Outputis1ifanevennumberofitsinputsare1.(如果输入有偶数个1，则输出为1。)Howtoknowthenumberof1s???回顾：用什么可以判断1的个数？？？5.8ParityCircuit(奇偶校验电路)A0

A1…An=

1oddnumberof1s变量为1的个数是奇数0evennumberof1s变量为1的个数是偶数Outputofodd-paritycircuitisinverted,weGetaneven-paritycircuit.(奇校验电路的输出反相就得到偶校验电路)NXORgatesmaybecascadedtoformacircuitwithn+1inputsandasingleoutput.(n个异或门级联，形成具有n+1个输入和单一输出的电路)ReviewofXORANDXNOR

(回顾异或、同或运算)A

B=(A⊙B)’A

B’=A⊙BA

B=A⊙B’Anytwosignals(inputsoroutput)ofanXORorXNORgatemaybecomplementedwithoutchangingtheresultinglogicfunction.(Figure5-72)(对于异或门、同或门的任何2个信号（输入或输出）都可以取反，而不改变结果的逻辑功能（

图5-72)F=A

BABFABFABABFFF=A’

B’F=(A’

B)’F=(A

B’)’I1I2I3I4INODDDaisy-ChainConnection

(菊花链式连接)I1I2I3I4IMINODDTreeStructure

(树状连接)CascadingXORGates(级联异或门）9-bitOdd/EvenParityGenerator74x280(9位奇偶校验发生器74x280）The74x2809-bitodd/evenparitygenerator:(a)logicdiagram,includingpinnumbersforastandard16-pindualin-linepackage;(b)traditionallogicsymbol.Parity-CheckingApplications

(奇偶校验的应用)Todetecterrorsinthetransmissionandstorageofdata用于检测代码在传输和存储过程中是否出现差错AEVENODD74x280HIAEVENODD74x280HItransmitter发端receiver收端DB[0:7]DB[0:7]ERROREnsureevennumber1s发端保证有偶数个1Ifodd,errorasserted收端ODD有效表示出错odd奇数even偶数5.9Comparator（比较器）ComparetwoBinarywordsandindicatewhethertheyareequal(比较2个二进制数值并指示其是否相等的电路)Comparator:CheckiftwoBinarywordsareequal

(等值比较器：检验数值是否相等)MagnitudeComparator:Comparetheirmagnitude(Greaterthan,Equal,Lessthan)(数值比较器：比较数值的大小（>,=,<）)5.9Comparator（比较器）Howtobuilda1-bitComparator?

(如何构造1位等值比较器？？)

——

UseXOR(XNOR)

(利用异或门（同或门）)ABDIFFABEQDIFF:differentEQ:equalHowtoBuildaN-bitComparator?

(如何构造多位等值比较器？？)DIFFA0B0A1B1A2B2A3B3Allindividualbitsarepairwiseequal必须每位都相等——parallelcomparator并行比较——serialcomparator串行比较4bitcomparator4位等值比较器AnIterativeComparator

(迭代比较电路)XYCMPEQIEQOX0Y0X1Y1XN-1YN-1EQ1EQ2EQNEQN-11XYCMPEQIEQOXYCMPEQIEQOserialcomparator——每位串行比较ABEQEQOEQISavelittlecost,butveryslow迭代的方法可能节省费用，但速度慢Cascadinginput用于级联的输入1-BitMagnitudeComparator

(一位数值比较器)①A>B（A=1,B=0）then

A·B’=1②A<B（A=0,B=1）then

A’·B=1③A=B，thenA⊙B=1EQ_LABLT_LGT_LActivelow输出低电平有效EQ_L=A·B’+A’·B=A

B=(A⊙B)’LT:LessThanEQ:EqualGT:GreaterThan(A’·B)’(A·B’)’n-BitMagnitudeComparator

(多位数值比较器)A(A3A2A1A0)

comparewith

B(B3B2B1B0)fromuptodownA与B自高而低逐位比较EQ=(A3⊙B3)·(A2⊙B2)·(A1⊙B1)·(A0⊙B0)GT=(A3>B3)LT=EQ’·GT’=(EQ+GT)’或(A3=

B3)·(A2=

B2)·

(A1>B1)或(A3=

B3)·(A2=

B2)·(A1=

B1)·

(A0>B0)或(A3=

B3)·

(A2>B2)A3·

B3’A2·

B2’A1·

B1’A0·

B0’⊙⊙⊙⊙⊙⊙+++4-BitComparator74x85

(4位比较器74x85)74x85A0A1A2A3ALTBINAEQBINAGTBINCascadinginputforexpanding级联输入，用于扩展ALTBOUT=(A<B)+(A=B)·ALTBINOutputsofLSBconnecttoinputsofMSB通常低位的输出接高位的输入BothhigherandlowerorderbitsareequalA=B：低位和高位都相等AH高位>BH高位AH高位=BH高位&AL低位>BL低位A>BAEQBOUT=(A=B)·AEQBINAGTBOUT=(A>B)+(A=B)·AGTBINSerialExpandingComparators

(比较器的串行扩展)XD[11:0]YD[11:0][3:0][7:4][11:8]X<YX=YX>Y+5VA<BIA=BIA>BIA<BOA=BOA>BOA0~A3B0~B374x85A<BIA=BIA>BIA<BOA=BOA>BOA0~A3B0~B374x85A<BIA=BIA>BIA<BOA=BOA>BOA0~A3B0~B374x85A12-bitcomparatorusing74x85s3片74x85构成12位比较器Lowerorder低位Higherorder高位8bitcomparator74x682

8位比较器P0P1P2P3P4P5P6P7Q1:logicdiagram?Q2：howtorepresentoutputsbelow？PNEQPEQQPGEQPLTQGELTQ3：Canexpand?能否扩展？Note:nocascadinginputs注意：没有级联输入端8bitcomparator74x682Logicdiagramforthe74x6828-bitcomparator,includingpinnumbersforastandard20-pindualin-linepackage.8bitcomparator74x682Q2：howtorepresentoutputsbelow？PNEQPEQQPGEQPLTQParalelExpandingComparators

(比较器的并行扩展)24bitcomparatorusing374x6823片74x682构成24位比较器P0~P7P=QQ0~Q7P>QP0~P7P=QQ0~Q7P>QP0~P7P=QQ0~Q7P>Q[7:0][15:8][23:16]P[23:0]Q[23:0]PEQQPGTQ用数据选择器74x151

实现逻辑函数F=

(X,Y,Z)(1,3,5,6)AClassProblem(每课一题)ENABCD0D1D2D3D4D5D6D7YY74x1515.10Adder(加法器)HalfAdderand

FullAdder（半加器和全加器）0000010110011110ABSCO(半加器真值表)Sum(相加的和):

S=A’·B+A·B’=A

BCarry(向高位的进位)：CO=A·B0000000101010010111010001101101101011111CIXYSCO(全加器真值表)TruthTableofHalfAdderTruthTableofFullAdder5.10Adder(加法器)SCOXYCIS=X

YCIX·Y00100111CIXY0001111001COX·CICO=

+

+Y·CI=X·Y+(X+Y)·CI0000000101010010111010001101101101011111CIXYSCO全加器真值表HalfAdderand

FullAdder（半加器和全加器）TruthTableofFullAdderRippleAdder(串行进位加法器)(缺点：运算速度慢，有较大的传输延迟)tADD=tXYCout+(n-2)*tCinCout+tCinSXYCICOSXYCICOSXYCICOSXYCICOSC1C2C3C4C0S0S1S2S3X0Y0X1Y1X2Y2X3Y3=0——ImproveSpeed:ParallelAdder

(提高速度：并行加法器)Disadvantage:Slow,MorePropagationDelayXYCICOSXYCICOSXYCICOSXYCICOSC1C2C3C4C0S0S1S2S3X0Y0X1Y1X2Y2X3Y3XYCMPEQIEQOX0Y0X1Y1XN-1YN-1EQ1EQ2EQNEQN-11XYCMPEQIEQOXYCMPEQIEQOAnIterativeComparator(串行比较器)RippleAdder(串行加法器)PrimaryInputs(主输入)PrimaryOutputs(主输出)BoundaryInputs(边界输入)BoundaryOutputs(边界输出)Cascadingoutput级联输出AnIterativeCircuit（迭代电路）Iterative：重复的,反复的,[数]迭代的PICICOPOPICICOPOPICICOPOC0C1C2CnPO0PO1POn-1PI0PI1PIn-1Figure5-79Cascadingoutput级联输出BoundaryInputs(边界输入)BoundaryOutputs(边界输出)PrimaryInputs(主输入)Primar