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AdvancedPackagingTech1aOutlinePackageDevelopmentTrend3DPackageWLCSP&FlipChipPackage2aPackageDevelopmentTrend3aSOFamilyQFPFamilyBGAFamilyPackageDevelopmentTrend4aCSPFamilyMemoryCardSiPModulePackageDevelopmentTrend5a3DPackage3DPackage6a3DPackageIntroductionetCSPStackFunctionalIntegrationHighLowTape-SCSP(orLGA)S-CSP(orLGA)S-PBGAS-M2CSPStacked-SiP2ChipStackWirebond2ChipStackFlipChip&WirebondMultiChipStackPackageonPackage(PoP)StackingSS-SCSP(film)FS-BGA3S-PBGAS-SBGAS-TSOP/S-QFP
3S-CSPS-etCSPetCSP+S-CSP
PS-fcCSP+SCSP
PoPwithinterposerFS-CSP2FS-CSP1PaperThinPS-vfBGA+SCSPPiP
5SCSPSS-SCSP(paste)UltrathinStackD2D3D4D2D2D3D4D2
PoPQFN4SS-SCSP7aStackedDieTopdieBottomdieFOWmaterilWire8aTSVTSV(ThroughSiliconVia)
Athrough-siliconvia(TSV)isaverticalelectricalconnection(via)passingcompletelythroughasiliconwaferordie.TSVtechnologyisimportantincreating3Dpackagesand3Dintegratedcircuits.
A3Dpackage(SysteminPackage,ChipStackMCM,etc.)containstwoormorechips(integratedcircuits)stackedverticallysothattheyoccupylessspace. Inmost3Dpackages,thestackedchipsarewiredtogetheralongtheiredges.Thisedgewiringslightlyincreasesthelengthandwidthofthepackageandusuallyrequiresanextra“interposer”layerbetweenthechips. Insomenew3Dpackages,through-siliconviareplaceedgewiringbycreatingverticalconnectionsthroughthebodyofthechips.Theresultingpackagehasnoaddedlengthorthickness.WireBondingStackedDieTSV9aWhat’sPoP?PoPisPackageonPackageTopandbottompackagesaretestedseparatelybydevicemanufacturerorsubcon.
PoP10aPoPPS-vfBGAPS-etCSPLowLoopWirePinGateMoldPackageStackingWaferThinningPoPCoreTechnology11aPoPAllowsforwarpagereductionbyutilizingfully-moldedstructureMorecompatiblewithsubstratethicknessreductionProvidesfinepitchtoppackageinterfacewiththrumoldviaImprovedboardlevelreliabilityLargerdiesize/packagesizeratioCompatiblewithflipchip,wirebond,orstackeddieconfigurationsCosteffectivecomparedtoalternativenextgenerationsolutionsAmkor’sTMV™PoPTopviewBottomviewThroughMoldVia12aPoPBallPlacementontopsurfaceBallPlacementonbottomDieBondMold(UnderFulloptional)LaserdrillingSingulationFinalVisualInspectionBaseM’tlThermaleffectProcessFlowofTMVPoP13aDigital(Btmdie)+Analog(Middledie)+Memory(Toppkg)PotableDigitalGadgetCellularPhone,DigitalStillCamera,PotableGameUnitMemorydieAnalogdieDigitaldiespacerEpoxyPiP14aEasysystemintegrationFlexiblememoryconfiguration100%memoryKGDThinnerpackagethanPOPHighIOinterconnectionthanPOPSmallfootprintinCSPformatIthasstandardballsizeandpitchConstructedwith:FilmAdhesivedieattachEpoxypasteforTopPKGAuwirebondingforinterconnectionMoldencapsulationWhyPiP?
PiP15aMaterialforHighReliabilityBasedonLowWarpageWaferThinningFineProcessControlTopPackageAttachDieAttachetcOptimizedPackageDesignFlipChipUnder-fillTopepoxyISMPiPCoreTechnology
PiP16aMemoryPKGSubstrateFlipchipMemoryPKGFlipchipInnerPKGAnalogAnalogSpacerDigitalInnerPKGWBPIPFCPIPPiPPiP–W/BPiPandFCPiP
17aWLCSP&FlipChipPackage18aWLCSPWhatisWLCSP? WLCSP(WaferLevelChipScalePackaging),isnotsameastraditionalpackagingmethod(dicingpackagingtesting,packagesizeisatleast20%increasedcomparedtodiesize). WLCSPispackagingandtestingonwaferbase,anddicinglater.Sothepackagesizeisexactlysameasbarediesize.
WLCSPcanmakeultrasmallpackagesize,andhighelectricalperformancebecauseoftheshortinterconnection.19aWLCSPWhyWLCSP?Smallestpackagesize:WLCSPhavethesmallestpackagesizeagainstdiesize.Soithaswidelyuseinmobiledevices.Highelectricalperformance:becauseoftheshortandthicktraceroutinginRDL,itgiveshighSIandreducedIRdrop.Highthermalperformance:sincethereisnoplasticorceramicmoldingcap,heatfromdiecaneasilyspreadout.Lowcost:noneedsubstrate,onlyonetimetesting.WLCSP’sdisadvantageBecauseofthediesizeandpinpitchlimitation,IOquantityislimited(usuallylessthan50pins).BecauseoftheRDL,staggerIOisnotallowedforWLCSP.20aRDLRDL:RedistributionLayerAredistributionlayer(RDL)isasetoftracesbuiltuponawafer’sactivesurfacetore-routethebondpads.
Thisisdonetoincreasethespacingbetweeneachinterconnection(bump).21aWLCSPProcessFlowofWLCSP22aWLCSPProcessFlowofWLCSP23aFlipChipPackageFCBGA(PassiveIntegratedFlipChipBGA)(PI)-EHS-FCBGA(PassiveIntegratedExposedHeatSinkFlipChipBGA)(PI)-EHS2-FCBGA(PassiveIntegratedExposed2piecesofHeatSinkFlipChipBGA)MCM-FCBGA(Multi-Chip-ModuleFCBGA)PI-EHS-MP-FCBGA(PassiveIntegratedExposedHeatSinkMultiPackageFlipChip)24aBump25aBumpDevelopment26aBumpDevelopment27aBumpDevelopment28aC4FlipChipWhat’sC4FlipChip?C4is:ControlledCollapsedChipConnectionChipisconnectedtosubstratebyRDLandBumpBumpmaterialtype:solder,gold29aC4FlipChipBGAMainFeaturesBallPitch:0.4mm-
1.27mmPackagesize:upto55mmx55mmSubstratelayer:4-16LayersBallCount:upto2912
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