北科大853电路理论与自动控制原理电子数电课件digitale chap

8-3Up/DownSynchronousCounters

（加/减同步计数器）8-3-13-bitup/downsynchronouscounter8-3-2Up/downdecadesynchronouscounter8-3-13-BitUp/DownSynchronousCounter0123454323456765…Figure8–24

a4-bitsynchronousbinaryup/downcounter.ThomasL.Floyd

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Allrightsreserved.8-3-2Up/DownDecadeSynchronousCounterAnIntegratedCircuit:The74HC190

Anup/downsynchronousdecadecounter.Timingexamplefora74HC190.特点:异步置数

利用已有的计数器产品经过外电路的不同连接方式得到。已有计数器： N进制需要得到的计数器： M进制 分两种情况进行讨论M<NM>N8-4Cascadedcounter---designofcounters任意进制计数器的构成方法1.M<N思考:在N进制计数器的顺序计数过程中,设法使之跳过不需要的状态(多余的状态)方法:有几种?结合芯片的功能表进行考虑.获得任意制进计数器的两种方法

（a）置零法(复位法)

（b）置数法(置位法)

（1）置零法(复位法):利用置零端适用于:异步置零的器件瞬时出现当第M个脉冲出现时，迅速置零例:用置零法将十进制计数器74LS160接成六进制计数器

分析：74160具有异步置零、同步置数功能功能表

CPRDLDETEP工作状态01111011101110置0预置数保持保持但C=0计数例:用置零法将74LS160接成六进制计数器例:用置零法将74LS160接成六进制计数器011060110译码产生低电平电路的状态转换图*电路的改进：考虑到置零信号可能太短，有的来不及动作，可以增加一个RS触发器

增加电路可靠性获得任意制进计数器的两种方法（a）置零法(复位法)

（b）置数法(置位法)利用置位端去掉多余的N-M个状态可以保留原芯片的进位输出（2）置数法(置位法)例用置数法将74160接成六进制计数器注意：74160为同步置数（a）置入00001010用置数法将74160接成六进制计数器50101（b）置入10011001用置数法将74160接成六进制计数器00102.M>N此时,一个芯片就不够用了,考虑用N片。分两种情况考虑：M可以进行分解：M=N1×N2M为素数,无法分解第一种情况:M=N1×N2串行进位并行进位两种方法Figure8–38Twocascadedcounters(allJandKinputsareHIGH).

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Allrightsreserved.例如:100=10×10,60=6×10Figure8–39TimingdiagramforthecascadedcounterconfigurationofFigure8–38.

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Allrightsreserved.4×8=32例:试用两片同步十进制计数器74LS160

接成百进制计数器方法一:电路的并行进位方式：CP同步0000000010011001时自动置零、进位百进制计数器方法二、电路的串行进位方式：CP异步0000000010011001时自动置零、进位百进制计数器思考:如果用十六进制的计数器组成百进制,如何做?Figure8–40Amodulus-100counterusingtwocascadeddecadecounters.

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Allrightsreserved.Figure8–41Threecascadeddecadecountersformingadivide-by-1000frequencydividerwithintermediatedivide-by-10anddivide-by-100outputs.

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Allrightsreserved.Figure8–42

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Allrightsreserved.Figure8–43Adivide-by-100counterusingtwo74F162decadecounters.

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Allrightsreserved.第二种情况:M为素数,无法分解整体置零方式整体置数方式两种方法例:试用两片同步十进制计数器74LS160

接成二十九进制计数器分析:二十九是一个素数,要用…电路的整体置零方式先接成百进制,再整体置零29001010010100100100000000译码产生低电平电路的整体置数方式先接成百进制,再整体(同步)置数28001010000100000100000000下一个CPFigure8–44Adivide-by-40,000counterusing74HC1614-bitbinarycounters.Notethateachoftheparalleldatainputsisshowninbinaryorder(the

right-mostbitD0istheLSBineachcounter).

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Allrightsreserved.说明:四个十六进制共有:16×16×16×16=65,536种状态,要组成40,000进制,多余的状态:65536-40000=25536,对应的十六进制数:(63c0)16任意进制计数器的构成方法小结:

已有计数器：N进制,需要得到的计数器：M进制分两种情况进行讨论M<NM>N置零法(复位法)置数法(置位法)M=N1×N2M为素数串行进位并行进位整体置零整体置数8-5DesignofSynchronousCounters

（同步计数器的设计）REVIEW：Generalclockedsequentialcircuit.MooreType&MealyType;StateMachine同步时序逻辑电路的设计过程STEP1:StateDiagramThomasL.Floyd

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Allrightsreserved.Designa3-bitGraycodecounterThomasL.Floyd

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Allrightsreserved.STEP2:Next-StateTableThomasL.Floyd

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Allrightsreserved.STEP3:Flip-FlopTransitionTableThomasL.Floyd

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Allrightsreserved.STEP4:KarnaughMapsThomasL.Floyd

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Allrightsreserved.STEP5:LogicExpressionsforFlip-FlopInputsSTEP6:CounterImplementationThomasL.Floyd

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Allrightsreserved.STEP6:CounterImplementationSummarySpecifythecountersequenceanddrawastatediagram.Deriveanext-statetablefromthestatediagram.Developatransitiontableshowingtheflip-flopinputsrequiredforeachtransition.TransfertheJandKstatesfromthetransitiontabletoKarnaughmaps.GrouptheKarnaughmapcellstogenerateandderivethelogicexpressionforeachflip-flop.Implementtheexpressionswithcombinationallogic,andcombinewiththeflip-flopstocreatethecounter.P308:Example8-5ThomasL.Floyd

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Allrightsreserved.Designacounterwiththeirregular(无规律的)binarycountsequenceshowninthestatediagram.UseJ-Kflip-flops.Step1:StateDiagramStep2:Next-StateTableStep3:Flip-FlopTransitionTableStep4:ThomasL.Floyd

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Allrightsreserved.Step6:CounterImplementation

Step5:LogicExpressionsforFlip-FlopInputsP308:Example8-6ThomasL.Floyd

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Allrightsreserved.Developasynchronous3-bitup/downcounterwithaGraycodesequence.ThecountershouldcountupwhenanUP/DOWNcontrolinputsis1andcountdownwhenthecontrolinputis0.MooreTypeorMealyType?ThomasL.Floyd

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Allrightsreserved.TheThree-bitup/downGraycodecounter补例1：设计一个串行数据检测器。对它的要求是：连续输入3个或3个以上的1时输出为1，其他输入情况下输出为0。步骤一：逻辑抽象并画出状态转换图确定输入变量：输入数据，用X表示。确定输出变量：检测结果，用Y表示。对状态编号：没有输入1以前的状态为S0，输入一个1以后的状态为S1，连续输入两个1以后的状态为S2，连续输入3个或3个以上1以后的状态为S3。根据题意画出原始的状态转换表X01S0S1S2S3S0/0S0/0S0/0S0/0S1/0S2/0S3/1S3/1步骤二：状态化简合并等价状态——相同的输入下有相同的输出，并转换到同样的次态。等价状态X01S0S1S2S0/0S0/0S0/0S1/0S2/0S3/1简化步骤三：状态分配（状态编码）根据化简后的状态数M确定触发器的个数N。按一定的规律对化简后的每一个状态都选定一个N位二进制代码来表示。此电路M=3，则N=2。取触发器状态Q1Q0的00、01和10分别代表S0、S1、S2。步骤四：选定触发器的类型，并求出电路的状态 方程、输出方程和驱动方程。根据状态转换表画出电路次态和输出的卡诺图。000001110100011110

X00/000/0xx/x00/001/010/0xx/x10/1将此卡诺图分解为Q1、Q0和Y的3个卡诺图。000001110100011110

X00x001x1000001110100011110

X00x010x0000001110100011110

X00x000x1000001110100011110

X00x001x1000001110100011110

X00x010x0000001110100011110

X00x000x1化简3个卡诺图，得到状态方程和输出方程。比照选定触发器的特性方程，变换状态方程的形式，以得出驱动方程。本检测电路选用JK触发器构成则驱动方程为：变换：步骤五：根据驱动方程、输出方程画出逻辑图。步骤六：检查设计的电路能否自启动。画出完整的状态转换图来检验。能自启动，设计完毕；不能自启动，重新修改逻辑设计。补8-2时序逻辑电路的自启动设计000001110100011110

X00/000/0xx/x00/001/010/0xx/x10/1由前面的例题可知，次态为任意项的状态是无效状态。如左图中的11状态为无效状态。若使全部无效状态的次态为有效状态，则此电路必能自启动。000001110100011110

X0