第四章vhdl(6)组合逻辑电路

第4章组合逻辑电路设计

组合电路在任一时刻的输出仅取决于该时刻电路的输入，与电路原来的状态无关，即无存储部件。4.5组合逻辑电路基本逻辑：与、或、非、与非、或非、异或编／译码器与选择器加（减）法器、求补器三态门及总线缓冲器奇偶校验电路、多人表决器、比较器4.5.1基本逻辑4.5.2译码器/编码器/选择器4.5.3加法器/求补器4.5.4三态门及总线缓冲器4.5.5奇偶校验电路/多人表决器/比较器4.5.1基本逻辑直接用逻辑运算符实现用if、case等语句描述例：libraryieee;useieee.std_logic_1164.all;entityn_andisport(a,b:instd_logic;c:outstd_logic);endn_and;architecturertlofn_andisbeginc<=anandb;endrtl;例：architecturertlofexmisbeginProcess(a,b)begintmp<=a&b;casetmpiswhen“00”=>y<=‘1’;when“01”=>y<=‘0’;when“10”=>y<=‘0’;when“11”=>y<=‘0’;whenothers=>y<=‘Z’;endcase;endprocess;endrtl;分析实现的逻辑4.5.2译码器/编码器/选择器

1.译码器

3-8译码器2-4译码器七段显示译码器地址译码器特殊译码器：一般译码器：七段显示译码器：七段显示译码器是对一个4位二进制数进行译码，并在七段数码管上显示出相应的十进制数或十六进制数。地址译码器：在计算机和微处理器系统是很重要的，是数字系统中最典型的CPLD应用。……ARCHITECTUREART3OFDECODERISBEGIND_OUT(0)<=‘1’WHEND_IN="000"ELSE‘0’；D_OUT(1)<=‘1’WHEND_IN="001"ELSE‘0’；D_OUT(2)<=‘1’WHEND_IN="010"ELSE‘0’；D_OUT(3)<=‘1’WHEND_IN="011"ELSE‘0’；D_OUT(4)<=‘1’WHEND_IN="100"ELSE‘0’；D_OUT(5)<=‘1’WHEND_IN="101"ELSE‘0’；D_OUT(6)<=‘1’WHEND_IN="110"ELSE‘0’；D_OUT(7)<=‘1’WHEND_IN="111"ELSE‘0’；ENDART3；

练习2-4译码器1)3-8译码器2)七段显示译码电路process(d)begincasediswhen"0000"=>y<="0111111";when"0001"=>y<="0000110";when"0010"=>y<="1011011";when"0011"=>y<="1001111";when"0100"=>y<="1100110";when"0101"=>y<="1101101";when"0110"=>y<="1111101";when"0111"=>y<="0000111";when"1000"=>y<="1111111";when"1001"=>y<="1101111";whenothers=>y<="0000000";endcase;endprocess;七段译码如果译码功能由共阴转为共阳只需对输出做一个取反，不用重新译码3）地址译码器例如：一个微处理器存储空间0000H---FFFFH,分为5部分，它们的地址分配如下：DRAM：0000H—DFFFH；I/O：E000H—E7FFH；备用：E800H---EFFFH；ROM1：F000H—F7FFH；ROM2：F800H—FFFFH；输入为16位地址，输出4个片选信号低电平有效PROCESS(address)BeginIfaddress<=x”dfff”thenDRAM<=‘0’;IO<=‘1’;ROM1<=‘1’;ROM2<=‘1’;Elsifaddress>=x”e000”andaddress<=x”e7ff”thenDRAM<=‘1’;IO<=‘0’;ROM1<=‘1’;ROM2<=‘1’;Elsifaddress>=x”f000”andaddress<=x”f7ff”thenDRAM<=‘1’;IO<=‘1’;ROM1<=‘0’;ROM2<=‘1’;Elsifaddress>=x”f800”thenDRAM<=‘1’;IO<=‘1’;ROM1<=‘1’;ROM2<=‘0’;Endif;Endprocess;A15A14A13A12A11A10~A0000000…0DRAM：0000H—DFFFH；110111…1111000…0I/O：E000H—E7FFH；111001…1111010…0备用：E800H—EFFFH；111011…1111100…0ROM1：F000H—F7FFH；111101…1111110…0ROM2：F800H—FFFFH；111111…1

A15~A11可区别地址，用最少地址线译码描述，输入仅为A15~A11PROCESS(A15,A14,A13,A12,A11)BeginIf(A15andA14andA13)=‘0’

thenDRAM<=‘0’;IO<=‘1’;ROM1<=‘1’;ROM2<=‘1’;ElsifA13=‘1’andA12=‘0’andA11=‘0’thenDRAM<=‘1’;IO<=‘0’;ROM1<=‘1’;ROM2<=‘1’;ElsifA13=‘1’andA12=‘1’andA11=‘0’thenDRAM<=‘1’;IO<=‘1’;ROM1<=‘0’;ROM2<=‘1’;ElsifA13=‘1’andA12=‘1’andA11=‘1’thenDRAM<=‘1’;IO<=‘1’;ROM1<=‘1’;ROM2<=‘0’;Endif;Endprocess;2.编码器生活中常用十进制数及文字、符号等表示事物数字电路只能以二进制信号工作用二进制代码表示文字符号等特定对象的过程，称为编码普通编码器：任何时刻只允许输入一个有效编码请求信号，否则输出将发生混乱优先编码器：允许同时输入两个以上的有效编码请求信号，只对其中优先权最高的一个进行编码优先级别的高低由设计者根据输入信号的轻重缓急情况而定。使用case语句没有优先级使用if、when_else语句带有优先级1)8线-3线普通编码器（教材p83)2)用if_then_elsif_else实现优先权编码器libraryieee;useieee.std_logic_1164.all;entitypriorityisport(d:instd_logic_vector(7downto0);q:outstd_logic_vector(2downto0));endpriority;architectureoneofpriorityisbeginprocess(d)beginifd(0)='0'thenq<="111";elsifd(1)='0'thenq<="110";elsifd(2)='0'thenq<="101";elsifd(3)='0'thenq<="100";elsifd(4)='0'thenq<="011";elsifd(5)='0'thenq<="010";elsifd(6)='0'thenq<="001";elseq<="000";endif;endprocess;endone;2)when_else实现优先权编码器…….ARCHITECTUREART1OFENCODERISBEGINy<="111"WHENH=‘1’ELSE"110"WHENG=‘1’ELSE"101"WHENF=‘1’ELSE"100"WHENE=‘1’ELSE "011"WHEND=‘1’ELSE"010"WHENC=‘1’ELSE"001"WHENB=‘1’ELSE"000"WHENA=‘1’ELSE"XXX"；ENDART1;3.选择器

选择器常用于信号的切换四选一选择器：4个信号输入端2个信号选择端1个信号输出端

当输入不同的选择信号时，就可以使4个输入中某个相应的输入信号与输出端接通。2选1ENTITYmux21ISPORT(d0,d1,sel:INBIT;q:OUTBIT);ENDmux21;ARCHITECTUREconnectOFmux21ISSIGNALtmp1,tmp2,tmp3:BIT;BEGIN;tmp1<=d0ANDsel;tmp2<=d1AND(NOTsel);tmp3<=tmp1ORtmp2;q<=tmp3;ENDconnect;

4.5.3加法器/求补器半加器全加器多位加法器求补器：对二进制数进行求补码运算libraryieee;useieee.std_logic_1164.all;entityfadderisport(a,b,cin:instd_logic;sum,cout:outstd_logic);endfadder;architecturertloffadderisbeginsum<=axorbxorcin;cout<=(aandb)or(aandcin)or(bandcin);endrtl;半加器（略）一位全加器CoutSum

baCin

CoutSum

baCinCoutSum

baCinCoutSum

baCincoutsum(3)sum(2)sum(1)sum(0)

b(3)a(3)b(2)a(2)b(1)a(1)b(0)a(0)cin四位加法器：libraryieee;useieee.std_logic_1164.all;entityadder4isport(a,b:instd_logic_vector(0to3);cin:instd_logic;cout:outstd_logic;sum:outstd_logic_vector(0to3));endadder4;architectureexmofadder4iscomponentfadderport(a,b,cin:instd_logic;sum,cout:outstd_logic);endcomponent;signalc:std_logic_vector(0to4);beginc(0)<=cin;gen:foriin0to3generateadderx:fadderportmap(a(i),b(i),c(i),sum(i),c(i+1));endgenerate;cout<=c(4);endexm;求补器libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitybuisport(a:instd_logic_vector(7downto0);b:outstd_logic_vector(7downto0));endbu;architecturertlofbuisbeginprocess(a)beginifa(7)=‘1’thenb<=nota+’1’;elseb<=a;endif;endprocess;endrtl;4.5.4三态门及总线缓冲器三态门数据输入控制输入 数据输出din endoutX 0 Z0 1 01 1 1总线缓冲器由多个三态门组成，数据总线是几位就有几个三态门

缓冲器一般分为两种：单向总线缓冲器双向总线缓冲器三态门libraryieee;useieee.std_logic_1164.all;entitythreeisport(a,en:instd_logic;y:outstd_logic);endthree;architecturebhvofthreeisbeginprocess(a,en)beginifen='1'theny<=a;elsey<='Z';endif;endprocess;endbhv;8位双向总线缓冲器LIBRARYieee;USEieee.std_logic_1164.all;ENTITYtri_bigateISPORT(a,b:INOUTstd_logic_vector(7downto0); en，dr:INstd_logic）;ENDtri_bigate;ARCHITECTURErtlOFtri_bigateISSignalaout,bout:std_logic_vector(7downto0);BEGINprocess(a,en,dr)beginif(en=‘1')and(dr=‘1’)thenbout<=a;elsebout<="ZZZZZZZZ";endif; b<=bout;endprocess；process(b,en,dr)beginif(en=‘1')and(dr=‘0’)thenaout<=b;elseaout<="ZZZZZZZZ";endif; a<=aout;endprocess;endrtl;

RTL不用aout和bout中间信号的RTL4.5.5奇偶校验电路/多人表决器/比较器1.奇偶校验电路具体程序见前面章节

另一种实现方式：将输入的8位二进制数用四位二进制数进行计数，判断最低位，若为‘1‘，则为奇数；若为‘0‘，则为偶数。2.七人表决器libraryieee;useieee.std_logic_1164.all;entityvote7isport(a:instd_logic_vector(0to6);lg,lr:outstd_logic);end;architecturebhvofvote7issignalpass:integerrange0to10;begin

process(a)variabletmp1:integerrange0to10;begintmp1:=0;foriin0to6loopifa(i)='1'thentmp1:=tmp1+1;elsetmp1:=tmp1+0;endif;endloop;pass<=tmp1;endprocess;lg<='1'whenpass>=4else'0';lr<='1'whenpass<4else'0';endbhv;

LIBRARYieee;USEieee.std_logic_1164.all;entitybj7isport(a0,a1,a2,a3,a4,a5,a6:instd_logic;y:outstd_logic);endbj7;architectureaofbj7isfunctionsum(a,b,c:std_logic)returnstd_logicisbeginreturn(axorbxorc);endsum;functioncout(a,b,c:std_logic)returnstd_logicisbeginreturn((aandb)or(aandc)or(bandc));endcout;signalc:std_logic_vector(0to2);signals:std_logic_vector(0to2);begin--s(0)<=sum(a0,a1,a2);--s(1)<=sum(a3,a4,a5);--s(2)<=sum(s(0),s(1),a6);--c(0)<=cout(a0,a1,a2);--c(1)<=cout(a3,a4,a5);--c(2)<=cout(s(0),s(1),a6);--c(3)<=cout(c(0),c(1),c(2));--y<=c(3);s(0)<=sum(a0,a1,a2);s(1)<=sum(a3,a4,'0');s(2)<=sum(a5,a6,'0');c(0)<=cout(a0,a1,a2);c(1)<=cout(a3,a4,'0');c(2)<=cout(a5,a6,'0');y<=cout(c(0),c(1),c(2))or(sum(c(0),c(1),c(2))andcout(s(0),s(1),s(2)));enda;3.三人表决器（方法一行为描述方式)ENTITYmajISPORT(a,b,c:INBIT;m:OUTBIT);ENDmaj;ARCHITECTUREbhvOFmajISBEGINPROCESS(a,b,c)CONSTANTlookuptable:BIT_VECTOR