专题七动态扫描电路设计

专题七：七段显示器动态扫描电路设计

一、教学内容：七段显示器动态扫描电路设计二、教学目的及要求：1、驾驭VHDL语言的基本结构及编程思想。2、驾驭七段显示器动态扫描电路设计方法。三、授课课时：6课时

设计要求：1、设计一个七段数码管动态扫描电路。数码管个数为8个，共阴极接法。2、设计一电路，限制上述电路实现“12345678”八个数字的显示，要求显示方式为：（1）自左至右逐个点亮数码管，最终全亮；再重复以上动作，每次变更时间间隔为1秒。（2）自左至右点亮数码管，每次只点亮一个，最终全息灭，再重复以上动作，每次变更时间间隔为1秒。（3）先中间两个点亮，再依次向外点亮；全亮后，再依次向中间熄灭；重复上述步骤，每次变更时间间隔为1秒。相当于实现8279的显示部分的功能一、七段显示器动态扫描电路设计框图abcdefgc6c5c1c4c2c3c7c8扫描控制器显示字符码存储器循环取数电路同步时钟发生器CLKA0A1A2地址线WR数据写入控制数据线RD读A00A01A02数据线clk1clk2双口RAM二、存储器设计（8位8字节静态随机存储器SRAM）LIBRARYieee;USEieee.std_logic_1164.all;ENTITYMEMO_RD_WRISPORT(WR,RD:INSTD_LOGIC;A:INSTD_LOGIC_VECTOR(2DOWNTO0);B:INSTD_LOGIC_VECTOR(2DOWNTO0);D:INSTD_LOGIC_VECTOR(7DOWNTO0);Q:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDMEMO_RD_WR;显示字符码存储器（8字节）A0A1A2地址线WR数据写入控制数据线D[7..0]Q[7..0]RD读数据控制A00A01A02双口RAMABARCHITECTUREaOFMEMO_RD_WRISSIGNALQ0,Q1,Q2,Q3:STD_LOGIC_VECTOR(7DOWNTO0);SIGNALQ4,Q5,Q6,Q7:STD_LOGIC_VECTOR(7DOWNTO0);BEGINPROCESS(WR,A)BEGINIFWR='1'THENCASEAISWHEN"000"=>Q0<=D;WHEN"001"=>Q1<=D;WHEN"010"=>Q2<=D;WHEN"011"=>Q3<=D;WHEN"100"=>Q4<=D;WHEN"101"=>Q5<=D;WHEN"110"=>Q6<=D;WHEN"111"=>Q7<=D;WHENOTHERS=>NULL;

ENDCASE;ENDIF;ENDPROCESS;PROCESS(RD,B)BEGIN

IFRD='1'THENCASEBISWHEN"000"=>Q<=Q0;WHEN"001"=>Q<=Q1;WHEN"010"=>Q<=Q2;WHEN"011"=>Q<=Q3;WHEN"100"=>Q<=Q4;WHEN"101"=>Q<=Q5;WHEN"110"=>Q<=Q6;WHEN"111"=>Q<=Q7;WHENOTHERS=>NULL;ENDCASE;

ENDIF;ENDPROCESS;ENDa;仿真结果：三、同步时钟CLK频率计算同步时钟发生器CLKclk1CLK频率计算：依据人的视觉暂留现象，一个数码管所要显示的字符只要在一秒内点亮24次以上，则感觉上该数码管没有熄灭一样。若8只数码管要出现这种效果，要求在一秒内每只数码管要闪亮24次以上。则CLK频率应为24X8＝192Hz以上，为了削减闪烁现象，达到较好的显示效果，取CLK频率为1024Hz，每秒内每个数码管显示次数为128次。CLK1=CLK;CLK2=CLK;四、循环取数电路设计LIBRARYieee;USEieee.std_logic_1164.all;ENTITYGET_CODEISPORT(CLK1:INSTD_LOGIC;D:INSTD_LOGIC_VECTOR(7DOWNTO0);

RD:OUTSTD_LOGIC;A:OUTSTD_LOGIC_VECTOR(2DOWNTO0);DOUT:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDGET_CODE;该电路利用地址线A00、A01、A02对存储器循环取数，并通过DOUT[7..0]送数码管显示。每个CLK1时钟取出一个显示码并立刻送数码管显示。abcdefgRD读A00A01A02数据线clk1循环取数电路D0—D7DOUT[6..0]DOUT1DOUT0DOUT2DOUT3DOUT4DOUT5DOUT6RDA地址信号发生电路锁存信号产生电路读信号产生电路A00A01A02RDCLK1锁存器DOUT[6..0]D[7..0]锁存信号LOAD循环取数电路内部功能图CLK1的上升沿锁存ARCHITECTUREaOFGET_CODEISSIGNAL LOAD:STD_LOGIC;SIGNALQQ:STD_LOGIC_VECTOR(7DOWNTO0);SIGNALNUM:INTEGERRANGE7DOWNTO0;BEGINRD<=‘1’;LOAD<=CLK1;PROCESS(CLK1)BEGINIFCLK1'EVENTANDCLK1='1'THENNUM<=NUM+1;ENDIF;ENDPROCESS;

PROCESS(NUM)BEGINCASENUMISWHEN0=>A<="000";WHEN1=>A<="001";WHEN2=>A<="010";WHEN3=>A<="011";WHEN4=>A<="100";WHEN5=>A<="101";WHEN6=>A<="110";WHEN7=>A<="111";WHENOTHERS=>NULL;ENDCASE;ENDPROCESS;PROCESS(LOAD)BEGINIFLOAD‘EVENTANDLOAD=‘1’THEN-------上升沿锁存

QQ<=D;ENDIF;ENDPROCESS;DOUT(7DOWNTO0)<=QQ(7DOWNTO0);ENDa;五、扫描限制器设计abcdefgc6c5c1c4c2c3c7c8扫描控制器clk2LIBRARYieee;USEieee.std_logic_1164.all;ENTITYSCAN_8ISPORT(CLK2:INSTD_LOGIC;C:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDSCAN_8;扫描限制器时序图ARCHITECTUREaOFSCAN_8ISSIGNALNUM:INTEGERRANGE7DOWNTO0;BEGINPROCESS(CLK2)BEGINIFCLK2'EVENTANDCLK2=‘1'THENIFNUM<=7THENNUM<=NUM+1;ELSENUM<=0;ENDIF;ENDIF;ENDPROCESS;Process(num)beginCASENUMIS

WHEN1=>C<="11111110";WHEN2=>C<="11111101";WHEN3=>C<="11111011";WHEN4=>C<="11110111";WHEN5=>C<="11101111";WHEN6=>C<="11011111";WHEN7=>C<="10111111";WHEN0=>C<="01111111";WHENOTHERS=>NULL;ENDCASE;ENDPROCESS;ENDA;地址数据线扫描限制器电路图存储器电路读显示码电路列扫描电路应用实例一：显示“01234567”八个数字LIBRARYieee;USEieee.std_logic_1164.all;ENTITYdisp_dataISPORT(CLK:INSTD_LOGIC;WR:OUTSTD_LOGIC;A:OUTSTD_LOGIC_VECTOR(2DOWNTO0);Q:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDdisp_data;ARCHITECTUREaOFdisp_dataIS--SIGNALQQ:STD_LOGIC_VECTOR(7DOWNTO0);SIGNALNUM:INTEGERRANGE7DOWNTO0;BEGINWR<=‘1’;PROCESS(CLK)BEGINIFCLK'EVENTANDCLK='1'THENIFNUM<=7THENNUM<=NUM+1;ELSENUM<=0;ENDIF;ENDIF;ENDPROCESS;PROCESS(NUM)BEGINCASENUMISWHEN0=>Q<="00111111";A<="000";WHEN1=>Q<="00000110";A<="001";WHEN2=>Q<="01011011";A<="010";WHEN3=>Q<="01001111";A<="011";WHEN4=>Q<="01100110";A<="100";WHEN5=>Q<="01101101";A<="101";WHEN6=>Q<="01111101";A<="110";WHEN7=>Q<="01111111";A<="111";WHENOTHERS=>NULL;ENDCASE;ENDPROCESS;ENDa;应用实例二：数字增加依次重复显示“12345678”八个数字应用实例三：单数字依次重复显示“12345678”八个数字七段显示器动态扫描电路设计框图abcdefgc6c5c1c4c2c3c7c8扫描控制器显示字符码存储器循环取数电路同步时钟发生器CLKA0A1A2地址线WR数据写入控制数据线RD读A00A01A02数据线clk1clk2LIBRARYieee;USEieee.std_logic_1164.all;ENTITYdisp_data2ISPORT(clk,clk1s:INSTD_LOGIC;WR:OUTSTD_LOGIC;A:OUTSTD_LOGIC_VECTOR(2DOWNTO0);Qout:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDdisp_data2;ARCHITECTUREaOFdisp_data2ISSIGNALNUM1:INTEGERRANGE7DOWNTO0;SIGNALnum2:INTEGERRANGE8DOWNTO0;SIGNALq0,q1,q2,q3,q4,q5,q6,q7:STD_LOGIC_VECTOR(7DOWNTO0);BEGINWR<='1';process(clk)beginifclk'eventandclk='1'thenifnum1<=7thennum1<=num1+1;elsenum1<=0;endif;endif;endprocess;

process(num1)beginCASENUM1ISWHEN0=>A<="000";qout<=q0;WHEN1=>A<="001";qout<=q1;WHEN2=>A<="010";qout<=q2;WHEN3=>A<="011";qout<=q3;WHEN4=>A<="100";qout<=q4;WHEN5=>A<="101";qout<=q5;WHEN6=>A<="110";qout<=q6;WHEN7=>A<="111";qout<=q7;WHENOTHERS=>NULL;endcase;endprocess;

process(clk1s)beginifclk1s'eventandclk1s='1'thenifnum2<8thennum2<=num2+1;elsenum2<=0;endif;endif;endprocess;process(num2)begincasenum2iswhen0=>q0<="00000000";q1<="00000000";q2<="00000000";q3<="00000000";q4<="00000000";q5<="00000000";q6<="00000000";q7<="00000000";when1=>q0<="00000110";q1<="00000000";q2<="00000000";q3<="00000000";q4<="00000000";q5<="00000000";q6<="00000000";q7<="00000000";when2=>q0<="00000110";q1<="01011011";q2<="00000000";q3<="00000000";q4<="00000000";q5<="00000000";q6<="00000000";q7<="00000000";

when3=>q0<="00000110";q1<="01011011";q2<="01001111";q3<="00000000";q4<="00000000";q5<="00000000";q6<="00000000";q7<="00000000";when4=>q0<="00000110";q1<="01011011";q2<="01001111";q