单周期实验报告1.理解计算机5大组成部分协调工作原理存储程序自动执行

实验目 理解计算机5大组成部分的协调工作原理，理解程序自动执行的原掌握I/O端口的设计方法，理解I/OI/O VerilogHDLquartus20MIPS指令的单周期CPU设计。采用I/O统一编址方式，即将输入输出的I/O地址空间，作为数据存取CPU与外部设备的输入输出端口设计。实验中可采利用设计的I/O端口，通过lw指令，输入DE2实验板上的按键等输入设备信息。即将外部设备状态，读到CPU内部寄存器。利用设计的I/O端口，通过sw指令，输出对DE2实验板上的LED灯CPU内部的寄存器，写入到外部设备的相应控制寄存器（或可直接连接利用自己编写的程序代码，在自己设计的CPU上，实现对板载输入开关或按键的状态输入，并将判别或处理结果，利用板载LED灯或7段LED数码管显示出来。例如，将一路4bit二进制输入与另一路4bit二进制输入相加，利用两组分别2个LED数码管以10进制形式显示“被加数”和“加数”，另外一组LED数码管以10进制形式显示“和”等（具体任务形式不做严格 实验仪 序主要流程图。1.采用VerilogHDL在quartus中实现基本的具有20条MIPS指令的单周期CPU设计。 AlteraDE1-SOC实验板1示波器1数字万用表1

puter_sim.rar90%代码，我们需要补全剩余代码。各1，按照该图补全真值表再分别补全alu.v与cu.v，完善这两个构件的功能。图1:单周期alu.v的补alucaluc123456789modulealu(a,b,aluc,s,z);input[31:0]a,b;input[3:0]aluc;output[31:0]s; z;reg[31:0]s; zalways@(aorboraluc //casex(aluc4’bx000:s=a+b //x0004’bx100:s=a−b //x1004’bx001:s=a&b //x0014’bx101:s=a|b //x1014’bx010:s=a^b //x0104’bx110:s=b<<16 //x110LUI:imm<<164’b0011:s=b<<a //0011SLL:rd<−(rt<<sa4’b0111:s=b>>a; //0111SRL:rd<−(rt>>sa)(logical) 4’b1111:s=$signed(b)>>>a; //1111SRA:rd<−(rt>>sa)(arithmetic) default:s=0 if(s== z=1 elsez=0 26sc_cu.vmodulesc_cu(op,func,z,wmem,wreg,regrt,m2reg,aluc,shimodulesc_cu(op,func,z,wmem,wreg,regrt,m2reg,aluc,shift,aluimm,pcsource,jal,sext); [5:0]op,func; z; wreg,regrt,jal,m2reg,shift,aluimm,sextoutput[3:0]aluc //seealu.123456 output[1:0]pcsource;//mux4x32nextpc(p4,adr,ra,jpc,pcsource,) wirer_type=~|op9 wirei_add=r_type&func[5]&~func[4]&~func[3] ~func[2]&~func[1]&~func[0] // wirei_sub=r_type&func[5]&~func[4]&~func[3] ~func[2]&func[1]&~func[0] // pleasecompletethedeletedcode wirei_and=r_type&func[5]&~func[4]&~func[3]&func[2]&~func[1]&~func[0]; wirei_or=r_type&func[5]&~func[4]&~func[3]&func[2]&~func[1]&func[0]; wirei_xor=r_type&func[5]&~func[4]&~func[3]&func[2]&func[1]&~func[0]; wirei_sll=r_type&~func[5]&~func[4]&~func[3]&~func[2]&~func[1]&~func[0]; wirei_srl=r_type&~func[5]&~func[4]&~func[3]&~func[2]&func[1]&~func[0]; wirei_sra=r_type&~func[5]&~func[4]&~func[3]&~func[2]&func[1]&func[0]; wirei_jr=r_type&~func[5]&~func[4]&func[3]&~func[2]&~func[1]&~func[0]; wirei_addi=~op[5]&~op[4]&op[3]&~op[2]&~op[1]&~op[0];// wirei_andi=~op[5]&~op[4]&op[3]&op[2]&~op[1]&~op[0];// wirei_ori ~op[5]&~op[4]&op[3]&op[2]&~op[1]&op[0] wirei_xori ~op[5]&~op[4]&op[3]&op[2]&op[1]&~op[0] wire op[5]&~op[4]&~op[3]&~op[2]&op[1]&op[0] wire =op[5]&~op[4]&op[3]&~op[2]&op[1]&op[0] wirei_beq=~op[5]&~op[4]&~op[3]&op[2]&~op[1]&~op[0] wirei_bne=~op[5]&~op[4]&~op[3]&op[2]&~op[1]&op[0] wirei_l =~op[5] ~op[4]&op[3]&op[2]&op[1] op[0] wire =~op[5]&~op[4]&~op[3]&~op[2]&op[1]&~op[0] wirei_jal=~op[5]&~op[4]&~op[3]&~op[2]&op[1]&op[0] assignpcsource[1]=i_jr|i_j|i_jal assignpcsource[0]=(i_beq&z)|(i_bne&~z)|i_j|i_jal assignwreg=i_add|i_sub|i_and| | ii_sll|i_srl|i_sra|i_addi|i_andii_ori|i_xori|i_lw|i_l |i_jalassignaluc[3]assignaluc[2]=i_lui;assignaluc[1]assignaluc[0]i_sra|i_sw //completebyyourself|i_or|i_srl||i_ori|i_bne|i_beq|i_sll|i_srl||i_or|i_andi||i_xori|i_lui|i_sll|i_srl|i_sraassignshif =i_sll|i_srl|i_sraassignaluimm=i_addi|i_ori|i_andi|i_xori|i_lw|i_sw|i_lui; completebyyourself.assignsext =i_addi|i_lw|i_sw|i_beq|i_bne;assignwmem =i_sw;assign i_lwassignregrt =i_addi|i_ori|i_andi|i_xori|i_lw|i_sw|i_lui;assignjal =i_jal;I/O将I/O地址空间设计为内存地址空间的一部分，即I/O地址和内存地址统一编址，CPU在内存MEM和I/O端口时，采用相同的指令，区自己的范围）的识别进行区分。如图2，利用address[7]，来区分是RAM还是I/O。本实验中，若address[7:2]为 则分别为out_port0、out_port1、out_port2，输出端口地址：80h，84h，88h；若address[7:2]为1100002、1100012则为in_port0、in_port1，输入////moduleio_input_reg(addr,io_clk,io_read_data,in_port0,in_port1)io_input_muxio_imput_mux2x32(in_reg0,in_reg1,addr[7:2],io_read_data)23[31:0[31:0addrio_clkin_port0,in_port1[31:0io_read_data[31:0in_reg0 //input[31:0in_reg1 //input56789图2:I/Oalwaysalways@(posedgeio_clkin_reg0<=in_port0;in_reg1<=in_port1moduleio_input_mux(a0,a1,sel_addr,y)[31:0a0,a1[5:0sel_addr[31:0y[31:0yalways@case(sel_addr6’b110000:y=a06’b110001:y=a1////moduleio_output_reg(addr,datain,write_io_enable,io_clk,clrn,out_port0,out_port1,out_port2);input[31:0]addr,dataininputwrite_io_enable,io_clk;inputclrn;//resetsignal.ifnecessary,canusethissignaltoresettheoutputto0.output[31:0]out_port0,out_port1,out_port2;reg[31:0]out_port0,out_port1,out_port2always@(posedgeio_clkornegedgeclrn)if(clrn==0)out_port0<=0;out_port1<=0;out_port2<=0;23456789elseelseif(write_io_enable==1)case(addr[7:2])6’b100000:out_port0<=datain;//80h6’b100001:out_port1<=datain;//84h6’b100010:out_port2<=datain;//88hputer.v的补computer的设计，将之computercpu设计自己的时钟频率，此次实验中将去原频率的半频。为方便输入输出数据在FPGA板上的显示，通过整除取puterputer(resetn,mem_clk,in_port0,in_port1,out_port0,out_port1out_port2,HEX0,HEX1,HEX2,HEX3,HEX4,HEX5)//inputresetn,clock,mem_clk;inputresetn,mem_clk;wireclockinput[3:0 in_port0 in_port1//output[31:0]pc,inst,aluout,memout;wire[31:0]pc,inst,aluout,memout;//imem_clk,dmem_clkwireimem_clk,dmem_clkoutput[31:0 out_port0,out_port1,out_port2//reg[31:0]tmp0,tmp1,tmp2wire[31:0]out_port0,out_port1,out_port2; [31:0]data; wmem;//allthese”wire”sareusedtoconnectorinterfacethecpu,dmem,imemandsoon.outputwire[6:0]half_frequencyhf(resetn,mem_clk,clock)sc_cpucpu(clock,resetn,inst,memout,pc,wmem,aluout,data)module//23456789 sc_instmemimem(pc,inst,clock,mem_clk,imem_clk); instructionmemory. sc_datamemdmem(aluout,data,memout,wmem,clock,mem_clk,dmem_clk,resetn,in_port0,in_port1,out_port0,out_port1,out_port2);//datamemory.reg[3:0]low0,high0,,high1,low2,high2alwayshigh0=out_port0/10low0=out_port0−*10high1=out_port1/10low1=out_port1−*10high2=out_port2/10low2=out_port2−*10sevensegs0(low0,HEX4)sevensegs1(high0,HEX5)sevensegs2(low1,HEX2)sevensegs3(high1,HEX3)sevensegs4(low2,HEX0)sevensegs5(high2,HEX1)4547modulehalf_frequency(resetn,mem_clk,clock) inputresetn,mem_clk outputclock regclock initia clock=0 always@(posedge if(~resetn clock<=0 clock<=~clock 6163modulesevenseg(in,sevenseg)65input[3:0]in66output[6:0]sevenseg67reg[6:0]sevenseg69initia70 sevenseg=07273alwayscase(in4’h0sevenseg[6:0=7’;4’h1sevenseg[6:0=7’;4’h2sevenseg[6:0=7’;4’h3sevenseg[6:0=7’;4’h4sevenseg[6:0=7’;4’h5sevenseg[6:0=7’;4’h6sevenseg[6:0=7’;4’h7sevenseg[6:0=7’;4’h8sevenseg[6:0=7’;4’h9sevenseg[6:0=7’;4sevenseg[6:0=7’;4sevenseg[6:0=7’;4sevenseg[6:0=7’;4sevenseg[6:0=7’;4sevenseg[6:0