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IntroductiontoDRAMTesting---DRAMinsideteam---2015.MayIntroductiontoDRAMTesting--AgendaBasisofTestingTypicalDRAMTestingFlowBurn-inDCTest(Open/Short,Leakage,IDD)FunctionalTest&TestPatternSpeedTestAgendaBasisofTestingDRAMManufactureWaferAssemblyFinalTestingFinalProductDRAMManufactureWaferAssemblyFWhyTesting?ToscreenoutdefectWaferdefectAssemblydefectMakesureproductmeetspecofcustomerVoltageguardbandTemperatureguardbandTimingguardbandComplextestpatternCollectdatafordesign&processimprovementQualityReliabilityCostEfficiencyWhyTesting?ToscreenoutdefeICTestMethodologyICTesterPPSDriverComparatorDUT**DUT=DeviceUnderTestPowerSupplyOutputInputTestingofaDUT:1.ToconnectPPS,Driver,Comparator&GND.2.ToapplypowertoDUT.3.ToinputdatatoDUT(Address,ControlCommand,Data)4.Tocompareoutputwith“expectvalue”andjudgePASS/FAILICTestMethodologyICTesterPPBasicTestSignalDigitalWaveformElementsLogicVoltageTimingBasicTestSignalDigitalWavefTypicalDRAMFinalTestFlowBurn-inMBT(MonitorBurninTest):StresstoscreenoutEarlyFailuresTBT(TestBurninTest):LongtimepatterntestVeryLowSpeed(5-20MHz),HighParallelTest(10-20Kpcs/oven),LowCostCoreTestDCTestFunctionalTestLowSpeed(DDR3@667MHz),TypicaltesterAdvantestT5588+512DUTHiFixSpeedTestSpeed&ACTimingTestFullSpeed(DDR3@1600MHzandabove),AdvantestT5503+256DUTHiFixBackendMarkingBallScanVisualInspectionBakingVacuumPackTypicalDRAMFinalTestFlowBuDRAMBurn-in(MBT) MBTistostressICandscreenoutearlyfailuresHighTemperatureStress(125degC)HighVoltageStressStressfulPatternBIOperationTimeFailureRateInfantMortalityNormalLifeWornoutNewproductMatureproductBathCurveDRAMBurn-in(MBT) MBTistosDRAMBurn-in(TBT)TBTisforlongtimetestpatternsMultipletemperaturetested(e.g.88’C,25’C,-10’C)LongtesttimeatlowspeedPatternscoverallcellarraysNoStressfulconditionHighparalleltestcount,lowcostBothMBTandTBTdoesNOTtestDC(AndoOven)DRAMBurn-in(TBT)TBTisforlDRAMAdvantestTestDCTestOpen/ShorttestLeakagetestIDDtestFunctionalTest(CoreTest)Differentparameter&PatternforeachfunctionTocheckDRAMcanoperatefunctionallySpeedTestTimingtest@differentspeedgradeDRAMAdvantestTestDCTestDCTestDCTestMethod:ISVM:
ISource
VMeasureVSIM
VSource
IMeasureVCCVCCDCTestDCTestMethod:VCCVCCDCTest–OpenShortPurpose:
CheckconnectionbetweenpinsandtestfixtureCheckifpintopinisshortinICpackageCheckifpintowaferpadhasopeninICpackageCheckifprotectiondiodes
workondie
ItisaquickelectricalchecktodetermineifitissafetoapplypowerAlsocalledContinuityTestDCTest–OpenShortPurpose:DCTest–OpenShortFailureMode:a)Wafer
Problem
Defectofdiodeb)AssemblyProblem
WirebondingSolderballc)ContactProblemSocket
issueCoreCircuitDefectivediodeSocketPogoPindefectWiretouchedDCTest–OpenShortFailureMoDCTest–OpenShortO/STestCondition:ProcedureGroundallpins(includingVDD)UsingPMUforce100uA,onepinatatimeMeasurevoltageFailopentestifthevoltageisgreaterthan1.5VFailshorttestifthevoltageislessthan0.2V100uA0.65VPMUforcesenseforceMeasureVss=0Vdd=0100uAFailOpenPassFailShort>1.5V<0.2VISVMOther=0Typical0.65VDCTest–OpenShortO/STestCDCTest–OpenShortO/STestCondition:ProcedureGroundallpins(includingVDD)UsingPMUforce–100uA,onepinatatimeMeasurevoltageFailopentestifthevoltageislessthan–1.5VFailshorttestifthevoltageisgreaterthan–0.2VFailShortPassFailOpen>–0.2V<–1.5V-100uA-0.65VPMUforcesenseforceMeasureVss=0Vdd=0-100uAISVMOther=0Typical-0.65VDCTest–OpenShortO/STestCDCTest–LeakagePurpose:
VerifyresistanceofpintoVDD/VSSishighenoughVerifyresistanceofpintopinsishighenoughIdentifyprocessprobleminCMOSdeviceDCTest–LeakagePurpose:DCTest–LeakageILIH/ILIL:InputLeakageHigh/LowToverifyinputbuffersofferahighresistanceNopreconditioningpatternappliedILOH/ILOL:OutputLeakageHigh/LowToverifytri-stateoutputbuffersofferahighresistanceinoffstateTestrequirespreconditioningpatternPerformedonlyonthree-stateoutputsandbi-directionalpinsDCTest–LeakageILIH/ILIL:InDCTest–LeakageFailureMode:a)Wafer
problemb)Assemblyproblemc)SocketContactproblem(short)DiecrackBalltouch(Short)DCTest–LeakageFailureMode:DCTest–InputLeakageLowTestCondition:ProcedureApplyVDDmax(2.0V)Pre-conditionallinputpinstologic‘1’(highvoltage)UsingPMU(ParametricMeasureUnit)forceGroundtotestedpinWaitfor1to5msecMeasurecurrentoftestedpinFailIILtestifthecurrentislessthan–1.5uAPassFail<–1.5uA0V-10nAPMUforceMeasureVss=0VDDmaxILILVLSICore“0”“1”allinputpins=2.3VOFFONDCTest–InputLeakageLowTesDCTest–InputLeakageHighTestCondition:ProcedureApplyVDDmax(2.0V)Pre-conditionallinputpinstologic‘0’(Lowvoltage)UsingPMUforceVDDMAXtotestedpinWaitfor1to5msecMeasurecurrentoftestedpinFailIIHtestifthecurrentisgreaterthan+1.5uAPassFail>
1.5uA2.0V10nAPMUforceMeasureVss=0VDDmaxILIHVLSICore“1”“0”allinputpins=0VONOFFDCTest–InputLeakageHighTeDCTest–OutputLeakageLowTestCondition:ProcedureApplyVDDmax(2.0V)Pre-conditiontheDUTtotristatewithspecificpatternWaitaspecifictimeUsingPMUforceVDDMAXtotestedI/OpinMeasurecurrentFailIOHtestifthecurrentisgreaterthan+4.5uAorlessthan-4.5uAPassFailGT4.5uA0.0V-10nAPMUforceMeasureVss=0VDDmaxILOLVLSICoreOFFOFFPre-condition
Pattern1/0FailLT-4.5uA“0”Allinputpins=2.3VAlloutputpins=0V/2.3VDCTest–OutputLeakageLowTeDCTest–OutputLeakageHighTestCondition:ProcedureApplyVDDmax(2.0V)Pre-conditiontheDUTtotristatewithspecificpatternWaitaspecifictimeUsingPMUforceVDDMAXtotestedI/OpinMeasurecurrentFailIOHtestifthecurrentisgreaterthan+4.5uAorlessthan-4.5uAPassFailGT4.5uA2.0V10nAPMUforceMeasureVss=0VDDmaxILOHVLSICoreAllinputpins=2.3VAlloutputpins=0V/2.3VOFFOFFPre-condition
Pattern1/0FailLT-4.5uA“1”DCTest–OutputLeakageHighTDCTest–TestProgramConditionDCTest–TestProgramConditiDCTest–IDDPurpose:IDD(orICC)measurescurrentofVddpinindifferentstates
Itmakessurepowerconsumptionnothigherthanexpected.FailureMode:WaferprocessissueAssemblyissueContactissue(VDD,VSS)DCTest–IDDPurpose:FailureMDCTest–StaticIDDTestCondition:ProcedureUsingPMUtoapplyVDDmaxonVDDpinExecutePre-conditionpatternStopthepatternWaitaspecifictime
MeasurecurrentflowingintoVDDpinswhiledeviceisinidleFailIDDtestifthecurrentisgreaterthanIDDspec.(NormalinmA)PassFailGTspec2.0V10mAPMUforcesenseforceMeasureVDDIDDVLSIVSS=0Pre-condition
PatternDCTest–StaticIDDTestCondiDCTest–DynamicIDDTestCondition:ProcedureUsingPMUtoapplyVDDmaxonVDDpinExecutePre-conditionpatternWaitaspecifictime
MeasurecurrentflowingintoVDDpinswhiledeviceisexecutingpatternFailIDDtestifthecurrentisgreaterthanIDDspec.(NormalinmA)StoppatternPassFailGTspec2.0V80mAPMUforcesenseforceMeasureVDDIDDVLSIVSS=0Pre-condition
PatternPre-condition
PatternDCTest–DynamicIDDTestCondFunctionTest
ToverifyDRAMcanoperatefunctionally,weneedtodoFunctionaltest. -EasyFunctionTest(EFT)
ItcheckbasicICfunctionalitybyreading“0”(or“1”)fromall cellafterwriting“0”(or“1”)in. TypicalTestPattern:MarchPattern(e.g.MarchC-)
MarchC-
Algorithm: ↑(w0);↑(r0,w1);↑(r1,w0);↓(r0,w1);↓(r1,w0);↓(r0) OperationCount:10*n
Scantype:X-Scan(Xinc->Yinc),Y-Scan(Yinc->Xinc) FaultCoverage:MostofFailureModeFunctionTest ToverifyDRAMc0000000000000000000000000000000R0000000000000000W100000000000000R0100000000000000W110000000000000R0110000000000000W111000000000000R0111000000000000W1111000000001111111100001111111111111111111111111111DRAMTest–Pattern(X-scan)YX000110110001101100000000000000000000000000000028DRAMTest–MarchPatternDRAMTest–MarchPattern29DRAMTest–FailureModeStuck-atFault(SAF)CouplingFault(CF)ShortsbetweendatalinesCrosstalkbetweendatalinesTransistionFault(TF)Cellcanbesetto0andnotto1(orviceversa)whenit’soperatedAddressingFault(AF)AddresslinestuckOpeninaddresslineShortsbetweenaddresslinesWrongaccessCellstuckDriverstuckDatalinestuckNeighborPatternSensitiveFault(NPSF)PatternsensitiveinteractionbetweencellsDataRetentionFault(DRF)DatacannotkeptsamestatusincellastimepassDRAMTest–FailureModeStuck-DRAMTest–MarchPatternMarchC-isthemosteffectiveDRAMTest–MarchPatternMarch31DRAMTest–1HTDefectModeOPENLEAKIDDEFTTESTERRELATED○○○○WAFERISSUE○○○○DIECRACK○○○DIECHIP○○○SURFACEDAMAGE○○NGDie○NONDIE○○NONWIRE○A~EOPEN○WIRESHORTWITHWIRE○WIRESHORTWITHDIEEDGE○WIRESWEEP○NONBROKENINNERLEAD○○OTHERS○○○○○:SUSPECTIONFORFAILAbovetablecomesfromourexperiences.Itisnotcoveredalloffailuremodesvsphenomena.So,itisonlyforyourreference.DRAMTest–1HTDefectModeOPEN32DRAMTest–FunctionalTestOtherFunctionalTestCheckCoreFunction(80%oftotaltesttime)DataRetention,ODT,BurstRead/Write,…etcDetectPatternSensitiveFault(PSF)000010000000000000DRAMTest–FunctionalTestOth33DRAMTest–ACTestACParameterTest
ToverifyICcanworkaseachtimingparameterdefinedindatasheet
Riseandfalltime
SetupandholdtimeDelaytestOthersDRAMTest–ACTestACParamete34DRAMTest–SpeedTest
TestDRAMatdifferentspeed:1.DDR3-1600(11-11-11)Test2.DDR3-1333(9-9-9)Test3.DDR3-1066(7-7-7)TestTestforeachtiming(tRCD,tRRD…)……DDR3-1600DDR3-1333SpeedFailDRAMTest–SpeedTest TestDR35DRAMTest–TestPlaninProgramO/SLeakageIDDEFTFUNCTestSpeed1333Fail16001866DRAMTest–TestPlaninProgr36DRAMinsideDRAM内存颗粒测试简介课件37IntroductiontoDRAMTesting---DRAMinsideteam---2015.MayIntroductiontoDRAMTesting--AgendaBasisofTestingTypicalDRAMTestingFlowBurn-inDCTest(Open/Short,Leakage,IDD)FunctionalTest&TestPatternSpeedTestAgendaBasisofTestingDRAMManufactureWaferAssemblyFinalTestingFinalProductDRAMManufactureWaferAssemblyFWhyTesting?ToscreenoutdefectWaferdefectAssemblydefectMakesureproductmeetspecofcustomerVoltageguardbandTemperatureguardbandTimingguardbandComplextestpatternCollectdatafordesign&processimprovementQualityReliabilityCostEfficiencyWhyTesting?ToscreenoutdefeICTestMethodologyICTesterPPSDriverComparatorDUT**DUT=DeviceUnderTestPowerSupplyOutputInputTestingofaDUT:1.ToconnectPPS,Driver,Comparator&GND.2.ToapplypowertoDUT.3.ToinputdatatoDUT(Address,ControlCommand,Data)4.Tocompareoutputwith“expectvalue”andjudgePASS/FAILICTestMethodologyICTesterPPBasicTestSignalDigitalWaveformElementsLogicVoltageTimingBasicTestSignalDigitalWavefTypicalDRAMFinalTestFlowBurn-inMBT(MonitorBurninTest):StresstoscreenoutEarlyFailuresTBT(TestBurninTest):LongtimepatterntestVeryLowSpeed(5-20MHz),HighParallelTest(10-20Kpcs/oven),LowCostCoreTestDCTestFunctionalTestLowSpeed(DDR3@667MHz),TypicaltesterAdvantestT5588+512DUTHiFixSpeedTestSpeed&ACTimingTestFullSpeed(DDR3@1600MHzandabove),AdvantestT5503+256DUTHiFixBackendMarkingBallScanVisualInspectionBakingVacuumPackTypicalDRAMFinalTestFlowBuDRAMBurn-in(MBT) MBTistostressICandscreenoutearlyfailuresHighTemperatureStress(125degC)HighVoltageStressStressfulPatternBIOperationTimeFailureRateInfantMortalityNormalLifeWornoutNewproductMatureproductBathCurveDRAMBurn-in(MBT) MBTistosDRAMBurn-in(TBT)TBTisforlongtimetestpatternsMultipletemperaturetested(e.g.88’C,25’C,-10’C)LongtesttimeatlowspeedPatternscoverallcellarraysNoStressfulconditionHighparalleltestcount,lowcostBothMBTandTBTdoesNOTtestDC(AndoOven)DRAMBurn-in(TBT)TBTisforlDRAMAdvantestTestDCTestOpen/ShorttestLeakagetestIDDtestFunctionalTest(CoreTest)Differentparameter&PatternforeachfunctionTocheckDRAMcanoperatefunctionallySpeedTestTimingtest@differentspeedgradeDRAMAdvantestTestDCTestDCTestDCTestMethod:ISVM:
ISource
VMeasureVSIM
VSource
IMeasureVCCVCCDCTestDCTestMethod:VCCVCCDCTest–OpenShortPurpose:
CheckconnectionbetweenpinsandtestfixtureCheckifpintopinisshortinICpackageCheckifpintowaferpadhasopeninICpackageCheckifprotectiondiodes
workondie
ItisaquickelectricalchecktodetermineifitissafetoapplypowerAlsocalledContinuityTestDCTest–OpenShortPurpose:DCTest–OpenShortFailureMode:a)Wafer
Problem
Defectofdiodeb)AssemblyProblem
WirebondingSolderballc)ContactProblemSocket
issueCoreCircuitDefectivediodeSocketPogoPindefectWiretouchedDCTest–OpenShortFailureMoDCTest–OpenShortO/STestCondition:ProcedureGroundallpins(includingVDD)UsingPMUforce100uA,onepinatatimeMeasurevoltageFailopentestifthevoltageisgreaterthan1.5VFailshorttestifthevoltageislessthan0.2V100uA0.65VPMUforcesenseforceMeasureVss=0Vdd=0100uAFailOpenPassFailShort>1.5V<0.2VISVMOther=0Typical0.65VDCTest–OpenShortO/STestCDCTest–OpenShortO/STestCondition:ProcedureGroundallpins(includingVDD)UsingPMUforce–100uA,onepinatatimeMeasurevoltageFailopentestifthevoltageislessthan–1.5VFailshorttestifthevoltageisgreaterthan–0.2VFailShortPassFailOpen>–0.2V<–1.5V-100uA-0.65VPMUforcesenseforceMeasureVss=0Vdd=0-100uAISVMOther=0Typical-0.65VDCTest–OpenShortO/STestCDCTest–LeakagePurpose:
VerifyresistanceofpintoVDD/VSSishighenoughVerifyresistanceofpintopinsishighenoughIdentifyprocessprobleminCMOSdeviceDCTest–LeakagePurpose:DCTest–LeakageILIH/ILIL:InputLeakageHigh/LowToverifyinputbuffersofferahighresistanceNopreconditioningpatternappliedILOH/ILOL:OutputLeakageHigh/LowToverifytri-stateoutputbuffersofferahighresistanceinoffstateTestrequirespreconditioningpatternPerformedonlyonthree-stateoutputsandbi-directionalpinsDCTest–LeakageILIH/ILIL:InDCTest–LeakageFailureMode:a)Wafer
problemb)Assemblyproblemc)SocketContactproblem(short)DiecrackBalltouch(Short)DCTest–LeakageFailureMode:DCTest–InputLeakageLowTestCondition:ProcedureApplyVDDmax(2.0V)Pre-conditionallinputpinstologic‘1’(highvoltage)UsingPMU(ParametricMeasureUnit)forceGroundtotestedpinWaitfor1to5msecMeasurecurrentoftestedpinFailIILtestifthecurrentislessthan–1.5uAPassFail<–1.5uA0V-10nAPMUforceMeasureVss=0VDDmaxILILVLSICore“0”“1”allinputpins=2.3VOFFONDCTest–InputLeakageLowTesDCTest–InputLeakageHighTestCondition:ProcedureApplyVDDmax(2.0V)Pre-conditionallinputpinstologic‘0’(Lowvoltage)UsingPMUforceVDDMAXtotestedpinWaitfor1to5msecMeasurecurrentoftestedpinFailIIHtestifthecurrentisgreaterthan+1.5uAPassFail>
1.5uA2.0V10nAPMUforceMeasureVss=0VDDmaxILIHVLSICore“1”“0”allinputpins=0VONOFFDCTest–InputLeakageHighTeDCTest–OutputLeakageLowTestCondition:ProcedureApplyVDDmax(2.0V)Pre-conditiontheDUTtotristatewithspecificpatternWaitaspecifictimeUsingPMUforceVDDMAXtotestedI/OpinMeasurecurrentFailIOHtestifthecurrentisgreaterthan+4.5uAorlessthan-4.5uAPassFailGT4.5uA0.0V-10nAPMUforceMeasureVss=0VDDmaxILOLVLSICoreOFFOFFPre-condition
Pattern1/0FailLT-4.5uA“0”Allinputpins=2.3VAlloutputpins=0V/2.3VDCTest–OutputLeakageLowTeDCTest–OutputLeakageHighTestCondition:ProcedureApplyVDDmax(2.0V)Pre-conditiontheDUTtotristatewithspecificpatternWaitaspecifictimeUsingPMUforceVDDMAXtotestedI/OpinMeasurecurrentFailIOHtestifthecurrentisgreaterthan+4.5uAorlessthan-4.5uAPassFailGT4.5uA2.0V10nAPMUforceMeasureVss=0VDDmaxILOHVLSICoreAllinputpins=2.3VAlloutputpins=0V/2.3VOFFOFFPre-condition
Pattern1/0FailLT-4.5uA“1”DCTest–OutputLeakageHighTDCTest–TestProgramConditionDCTest–TestProgramConditiDCTest–IDDPurpose:IDD(orICC)measurescurrentofVddpinindifferentstates
Itmakessurepowerconsumptionnothigherthanexpected.FailureMode:WaferprocessissueAssemblyissueContactissue(VDD,VSS)DCTest–IDDPurpose:FailureMDCTest–StaticIDDTestCondition:ProcedureUsingPMUtoapplyVDDmaxonVDDpinExecutePre-conditionpatternStopthepatternWaitaspecifictime
MeasurecurrentflowingintoVDDpinswhiledeviceisinidleFailIDDtestifthecurrentisgreaterthanIDDspec.(NormalinmA)PassFailGTspec2.0V10mAPMUforcesenseforceMeasureVDDIDDVLSIVSS=0Pre-condition
PatternDCTest–StaticIDDTestCondiDCTest–DynamicIDDTestCondition:ProcedureUsingPMUtoapplyVDDmaxonVDDpinExecutePre-conditionpatternWaitaspecifictime
MeasurecurrentflowingintoVDDpinswhiledeviceisexecutingpatternFailIDDtestifthecurrentisgreaterthanIDDspec.(NormalinmA)StoppatternPassFailGTspec2.0V80mAPMUforcesenseforceMeasureVDDIDDVLSIVSS=0Pre-condition
PatternPre-condition
PatternDCTest–DynamicIDDTestCondFunctionTest
ToverifyDRAMcanoperatefunctionally,weneedtodoFunctionaltest. -EasyFunctionTest(EFT)
ItcheckbasicICfunctionalitybyreading“0”(or“1”)fromall cellafterwriting“0”(or“1”)in. TypicalTestPattern:MarchPattern(e.g.MarchC-)
MarchC-
Algorithm: ↑(w0);↑(r0,w1);↑(r1,w0);↓(r0,w1);↓(r1,w0);↓(r0) OperationCount:10*n
Scantype:X-Scan(Xinc->Yinc),Y-Scan(Yinc->Xinc) FaultCoverage:MostofFailureModeFunctionTest ToverifyDRAMc0000000000000000000000000000000R0000000000000000W100000000000000R0100000000000000W110000000000000R0110000000000000W111000000000000R0111000000000000W1111000000001111111100
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