基于FPGA的UART模块设计报告

第2部分UART模块模块框图和功能简介UART模块的主要作用是提供串口控制程序，与PC上位机进行通信，将键盘按键对应的ASCII码输出到串口终端上，通过上位机观察键盘按键的ASCII码，验证PS/2接口模块的输出结果的正确性。该模块的输入输出示意图如REF_Ref295250634\r\h图1所示：UART模块I/O端口其中，key_data是键盘按键对应ASCII码；key_int则为对应的中断信号，默认时该信号始终保持高，当键盘有键被按下，经过PS/2模块译码后将对应的ASCII码送到key_data上，然后将key_int拉低一个周期，表示新键被按下，UART模块可以读取key_data上的信号并能通过串口发送出去。clk和rst_n分别为系统时钟（50MHz）和复位信号（低电平有效）；rs232_rx和rs232_tx分别为串口的接收信号线和发送信号线。模块内部框图如REF_Ref295251586\r\h图2所示：UART模块内部框图UART模块主要由三个子模块构成：speed_select、my_uart_rx和my_uart_tx。speed_select的主要功能是由系统时钟产生串口通信所需要的波特率时钟。由于本开发板的系统时钟为50MHz，不同波特率对应的分频系数见下表：波特率分频系数9600520719200260338400130157600867115200433speed_select的原理图符合如REF_Ref295252303\r\h图3所示：speed_select模块原理图在speed_select中，bps_start为时钟使能信号，当发送或接收模块需要发送或接收数据时，将该信号线拉高，使能speed_select模块产生对应波特率所需要的时钟，由clk_bps输出。clk和rst_n分别为时钟信号和复位信号。my_uart_rx则是串口接收模块，主要功能是从主模块的rs232_rx信号线上接收数据，完成串并转换，然后输出，其原理图符合如REF_Ref295253364\r\h图4所示：my_uart_rx模块原理图在my_uart_rx模块中，bps_start为波特率时钟使能信号，当从rs232_rx信号线上检测到下降沿（起始位）时，即将bps_start信号置位，从而使能发送波特率时钟模块（speed_rx，speed_select的一个实例），产生波特率时钟，从clk_bps输入。rx_data为接收到的数据的并行输出。在本设计的UART模块中，并不需要通过串口向开发板发送数据，因此如果出现了上位机通过串口向开发板发送数据的情况，不做别的响应，仅将数据传回。因此，rx_data被送到my_uart_tx模块中。rx_int为接收数据中断信号，每次数据接收完毕后，my_uart_rx模块即在该信号线上产生一个周期的低电平。my_uart_tx检测到该信号线上出现下降沿，即读取rx_data中的数据。my_uart_tx模块有两个功能，一是将my_uart_rx模块接收到的数据再发送回去，二是将ps/2模块检测到的按键的ASCII码发送到串口上，该模块原理图符合如REF_Ref295253398\r\h图5所示：my_uart_tx模块原理图由于需完成两个功能，该模块配套需要两个波特率时钟产生电路，分别由bps_start和bps_start_key使能，产生的波特率时钟信号由clk_bps和clk_bps_key输入。rx_data为接收到的数据，rx_int为接收数据中断信号。key_data则为按键ASCII码数据，key_int则为按键ASCII码数据中断信号，每当在key_int上检测到下降沿，my_uart_tx模块就会读取key_data上的数据并发送到rs232_tx上。综合报告Copyright(c)1995-2007Xilinx,Inc.Allrightsreserved.CPU:0.00/0.20s|Elapsed:0.00/0.00s-->Parameterxsthdpdirsetto./xstCPU:0.00/0.20s|Elapsed:0.00/0.00sTABLEOFCONTENTS1)SynthesisOptionsSummary2)HDLCompilation3)DesignHierarchyAnalysis4)HDLAnalysis5)HDLSynthesis5.1)HDLSynthesisReport6)AdvancedHDLSynthesis6.1)AdvancedHDLSynthesisReport7)LowLevelSynthesis8)PartitionReport9)FinalReport9.1)Deviceutilizationsummary9.2)PartitionResourceSummary9.3)TIMINGREPORT=========================================================================*SynthesisOptionsSummary*=========================================================================----SourceParametersInputFileName:"my_uart_top.prj"InputFormat:mixedIgnoreSynthesisConstraintFile:NO----TargetParametersOutputFileName:"my_uart_top"OutputFormat:NGCTargetDevice:xc3s500e-4-fg320----SourceOptionsTopModuleName:my_uart_topAutomaticFSMExtraction:YESFSMEncodingAlgorithm:AutoSafeImplementation:NoFSMStyle:lutRAMExtraction:YesRAMStyle:AutoROMExtraction:YesMuxStyle:AutoDecoderExtraction:YESPriorityEncoderExtraction:YESShiftRegisterExtraction:YESLogicalShifterExtraction:YESXORCollapsing:YESROMStyle:AutoMuxExtraction:YESResourceSharing:YESAsynchronousToSynchronous:NOMultiplierStyle:autoAutomaticRegisterBalancing:No----TargetOptionsAddIOBuffers:YESGlobalMaximumFanout:500AddGenericClockBuffer(BUFG):24RegisterDuplication:YESSlicePacking:YESOptimizeInstantiatedPrimitives:NOUseClockEnable:YesUseSynchronousSet:YesUseSynchronousReset:YesPackIORegistersintoIOBs:autoEquivalentregisterRemoval:YES----GeneralOptionsOptimizationGoal:SpeedOptimizationEffort:1KeepHierarchy:NORTLOutput:YesGlobalOptimization:AllClockNetsReadCores:YESWriteTimingConstraints:NOCrossClockAnalysis:NOHierarchySeparator:/BusDelimiter:<>CaseSpecifier:maintainSliceUtilizationRatio:100BRAMUtilizationRatio:100Verilog2001:YESAutoBRAMPacking:NOSliceUtilizationRatioDelta:5==================================================================================================================================================*HDLCompilation*=========================================================================Compilingverilogfile"speed_select.v"inlibraryworkCompilingverilogfile"my_uart_tx.v"inlibraryworkModule<speed_select>compiledCompilingverilogfile"my_uart_rx.v"inlibraryworkModule<my_uart_tx>compiledCompilingverilogfile"my_uart_top.v"inlibraryworkModule<my_uart_rx>compiledModule<my_uart_top>compiledNoerrorsincompilationAnalysisoffile<"my_uart_top.prj">succeeded.=========================================================================*DesignHierarchyAnalysis*=========================================================================Analyzinghierarchyformodule<my_uart_top>inlibrary<work>.Analyzinghierarchyformodule<speed_select>inlibrary<work>.Analyzinghierarchyformodule<my_uart_rx>inlibrary<work>.Analyzinghierarchyformodule<my_uart_tx>inlibrary<work>.=========================================================================*HDLAnalysis*=========================================================================Analyzingtopmodule<my_uart_top>.Module<my_uart_top>iscorrectforsynthesis.Analyzingmodule<speed_select>inlibrary<work>.Module<speed_select>iscorrectforsynthesis.Analyzingmodule<my_uart_rx>inlibrary<work>.Module<my_uart_rx>iscorrectforsynthesis.Analyzingmodule<my_uart_tx>inlibrary<work>.Module<my_uart_tx>iscorrectforsynthesis.=========================================================================*HDLSynthesis*=========================================================================Performingbidirectionalportresolution...SynthesizingUnit<speed_select>.Relatedsourcefileis"speed_select.v".WARNING:Xst:1780-Signal<uart_ctrl>isneverusedorassigned.Found1-bitregisterforsignal<clk_bps_r>.Found13-bitupcounterforsignal<cnt>.Summary: inferred1Counter(s). inferred1D-typeflip-flop(s).Unit<speed_select>synthesized.SynthesizingUnit<my_uart_rx>.Relatedsourcefileis"my_uart_rx.v".WARNING:Xst-Property"use_dsp48"isnotapplicableforthistechnology.Found1-bitregisterforsignal<rx_int>.Found1-bittristatebufferforsignal<bps_start_r>.Found1-bitregisterforsignal<Mtridata_bps_start_r>.Found4-bitregisterforsignal<num>.Found4-bitadderforsignal<num$addsub0000>createdatline93.Found1-bitregisterforsignal<rs232_rx0>.Found1-bitregisterforsignal<rs232_rx1>.Found1-bitregisterforsignal<rs232_rx2>.Found1-bitregisterforsignal<rs232_rx3>.Found8-bitregisterforsignal<rx_data_r>.Found8-bitregisterforsignal<rx_temp_data>.Summary: inferred26D-typeflip-flop(s). inferred1Adder/Subtractor(s). inferred1Tristate(s).Unit<my_uart_rx>synthesized.SynthesizingUnit<my_uart_tx>.Relatedsourcefileis"my_uart_tx.v".Found1-bittristatebufferforsignal<bps_start_key_r>.Found1-bittristatebufferforsignal<bps_start_r>.Found1-bitregisterforsignal<key_en>.Found1-bitregisterforsignal<key_int0>.Found1-bitregisterforsignal<key_int1>.Found1-bitregisterforsignal<key_int2>.Found1-bitregisterforsignal<Mtridata_bps_start_key_r>.Found1-bitregisterforsignal<Mtridata_bps_start_r>.Found4-bitregisterforsignal<num>.Found4-bitadderforsignal<num$share0000>.Found1-bitregisterforsignal<rs232_tx_r>.Found1-bitregisterforsignal<rx_int0>.Found1-bitregisterforsignal<rx_int1>.Found1-bitregisterforsignal<rx_int2>.Found8-bitregisterforsignal<tx_data>.Found1-bitregisterforsignal<tx_en>.Summary: inferred23D-typeflip-flop(s). inferred1Adder/Subtractor(s). inferred2Tristate(s).Unit<my_uart_tx>synthesized.SynthesizingUnit<my_uart_top>.Relatedsourcefileis"my_uart_top.v".Unit<my_uart_top>synthesized.INFO:Xst:1767-HDLADVISOR-Resourcesharinghasidentifiedthatsomearithmeticoperationsinthisdesigncansharethesamephysicalresourcesforreduceddeviceutilization.Forimprovedclockfrequencyyoumaytrytodisableresourcesharing.=========================================================================HDLSynthesisReportMacroStatistics#Adders/Subtractors:24-bitadder:2#Counters:313-bitupcounter:3#Registers:321-bitregister:284-bitregister:28-bitregister:2#Tristates:31-bittristatebuffer:3==================================================================================================================================================*AdvancedHDLSynthesis*=========================================================================LoadingdeviceforapplicationRf_Devicefromfile'3s500e.nph'inenvironmentD:\Xilinx91i.=========================================================================AdvancedHDLSynthesisReportMacroStatistics#Adders/Subtractors:24-bitadder:2#Counters:313-bitupcounter:3#Registers:52Flip-Flops:52==================================================================================================================================================*LowLevelSynthesis*=========================================================================WARNING:Xst:2042-Unitmy_uart_tx:2internaltristatesarereplacedbylogic(pull-upyes):bps_start,bps_start_key.WARNING:Xst:2041-Unitmy_uart_rx:1internaltristateisreplacedbylogic(pull-upyes):bps_start.Optimizingunit<my_uart_top>...Optimizingunit<my_uart_rx>...Optimizingunit<my_uart_tx>...Mappingallequations...Buildingandoptimizingfinalnetlist...Foundareaconstraintratioof100(+5)onblockmy_uart_top,actualratiois1.FinalMacroProcessing...ProcessingUnit<my_uart_top>:INFO:Xst:741-HDLADVISOR-A2-bitshiftregisterwasfoundforsignal<my_uart_tx/key_int1>andcurrentlyoccupies2logiccells(1slices).Removingtheset/resetlogicwouldtakeadvantageofSRL16(andderived)primitivesandreducethisto1logiccells(1slices).Evaluateiftheset/resetcanberemovedforthissimpleshiftregister.Themajorityofsimplepipelinestructuresdonotneedtobeset/resetoperationally.INFO:Xst:741-HDLADVISOR-A2-bitshiftregisterwasfoundforsignal<my_uart_tx/rx_int1>andcurrentlyoccupies2logiccells(1slices).Removingtheset/resetlogicwouldtakeadvantageofSRL16(andderived)primitivesandreducethisto1logiccells(1slices).Evaluateiftheset/resetcanberemovedforthissimpleshiftregister.Themajorityofsimplepipelinestructuresdonotneedtobeset/resetoperationally.Unit<my_uart_top>processed.=========================================================================FinalRegisterReportMacroStatistics#Registers:91Flip-Flops:91==================================================================================================================================================*PartitionReport*=========================================================================PartitionImplementationStatus-------------------------------NoPartitionswerefoundinthisdesign.-------------------------------=========================================================================*FinalReport*=========================================================================FinalResultsTopLevelOutputFileName:my_uart_topOutputFormat:NGCOptimizationGoal:SpeedKeepHierarchy:NODesignStatistics#IOs:13CellUsage:#BELS:233#GND:1#INV:4#LUT1:36#LUT2:13#LUT2_D:3#LUT3:11#LUT3_D:1#LUT3_L:1#LUT4:77#LUT4_D:7#LUT4_L:3#MUXCY:36#MUXF5:3#VCC:1#XORCY:36#FlipFlops/Latches:91#FDC:52#FDCE:35#FDE:1#FDPE:1#FDSE:2#ClockBuffers:1#BUFGP:1#IOBuffers:12#IBUF:11#OBUF:1=========================================================================Deviceutilizationsummary:---------------------------SelectedDevice:3s500efg320-4NumberofSlices:92outof46561%NumberofSliceFlipFlops:91outof93120%Numberof4inputLUTs:156outof93121%NumberofIOs:13NumberofbondedIOBs:13outof2325%NumberofGCLKs:1outof244%---------------------------PartitionResourceSummary:---------------------------NoPartitionswerefoundinthisdesign.---------------------------=========================================================================TIMINGREPORTNOTE:THESETIMINGNUMBERSAREONLYASYNTHESISESTIMATE.FORACCURATETIMINGINFORMATIONPLEASEREFERTOTHETRACEREPORTGENERATEDAFTERPLACE-and-ROUTE.ClockInformation:-----------------------------------------------------+------------------------+-------+ClockSignal|Clockbuffer(FFname)|Load|-----------------------------------+------------------------+-------+clk|BUFGP|91|-----------------------------------+------------------------+-------+AsynchronousControlSignalsInformation:--------------------------------------------------------------------------------+-----------------------------+-------+ControlSignal|Buffer(FFname)|Load|----------------------------------------+-----------------------------+-------+my_uart_rx/rst_n_inv(rst_n_inv1_INV_0:O)|NONE(my_uart_rx/rx_data_r_1)|88|----------------------------------------+-----------------------------+-------+TimingSummary:---------------SpeedGrade:-4Minimumperiod:6.019ns(MaximumFrequency:166.141MHz)Maximumcombinationalpathdelay:NopathfoundTimingDetail:--------------Allvaluesdisplayedinnanoseconds(ns)=========================================================================Timingconstraint:DefaultperiodanalysisforClock'clk'Clockperiod:6.019ns(frequency:166.141MHz)Totalnumberofpaths/destinationports:1233/120-------------------------------------------------------------------------Delay:6.019ns(LevelsofLogic=4)Source:speed_key/cnt_2(FF)Destination:speed_key/cnt_11(FF)SourceClock:clkrisingDestinationClock:clkrisingDataPath:speed_key/cnt_2tospeed_key/cnt_11GateNetCell:in->outfanoutDelayDelayLogicalName(NetName)----------------------------------------------------FDC:C->Q30.5910.706speed_key/cnt_2(speed_key/cnt_2)LUT4_L:I0->LO10.7040.135speed_key/cnt_or000016(speed_key/cnt_or0000_map8)LUT4:I2->O110.7040.937speed_key/cnt_or000025(speed_key/cnt_or0000_map13)LUT4_D:I3->O20.7040.526speed_key/cnt_or000048(speed_key/cnt_or0000)LUT2:I1->O10.7040.000speed_key/Mcount_cnt_eqn_111(speed_key/Mcount_cnt_eqn_11)FDC:D0.308speed_key/cnt_11----------------------------------------Total6.019ns(3.715nslogic,2.304nsroute)(61.7%logic,38.3%route)=========================================================================Timingconstraint:DefaultOFFSETINBEFOREforClock'clk'Totalnumberofpaths/destinationports:57/57-------------------------------------------------------------------------Offset:4.812ns(LevelsofLogic=3)Source:rst_n(PAD)Destination:speed_key/cnt_7(FF)DestinationClock:clkrisingDataPath:rst_ntospeed_key/cnt_7GateNetCell:in->outfanoutDelayDelayLogicalName(NetName)----------------------------------------------------IBUF:I->O71.2180.883rst_n_IBUF(rst_n_IBUF)LUT2_D:I0->O90.7040.995speed_key/cnt_or000048_SW0(N365)LUT4:I0->O10.7040.000speed_key/Mcount_cnt_eqn_71(speed_key/Mcount_cnt_eqn_7)FDC:D0.308speed_key/cnt_7----------------------------------------Total4.812ns(2.934nslogic,1.878nsroute)(61.0%logic,39.0%route)=========================================================================Timingconstraint:DefaultOFFSETOUTAFTERforClock'clk'Totalnumberofpaths/destinationports:1/1-------------------------------------------------------------------------Offset:4.283ns(LevelsofLogic=1)Source:my_uart_tx/rs232_tx_r(FF)Destination:rs232_tx(PAD)SourceClock:clkrisingDataPath:my_uart_tx/rs232_tx_rtors232_txGateNetCell:in->outfanoutDelayDelayLogicalName(NetName)----------------------------------------------------FDPE:C->Q10.5910.420my_uart_tx/rs232_tx_r(my_uart_tx/rs232_tx_r)OBUF:I->O3.272rs232_tx_OBUF(rs232_tx)----------------------------------------Total4.283ns(3.863nslogic,0.420nsroute)(90.2%logic,9.8%route)=========================================================================CPU:20.38/20.62s|Elapsed:21.00/21.00s-->Totalmemoryusageis300512kilobytesNumberoferrors:0(0filtered)Numberofwarnings:4(0filtered)Numberofinfos:3(0filtered)源代码UART模块顶层设计`timescale1ns/1psmodulemy_uart_top( clk,rst_n, rs232_rx,rs232_tx, key_data,key_int );inputclk; //50MHz主时钟inputrst_n; //低电平复位信号input[7:0]key_data;//键盘ASCII码信号线inputkey_int; //键盘终端信号,下降沿有效。先将数据送到key_data上，然后输入key_int信号（低），保留一定时间后再拉高inputrs232_rx; //RS232接收数据信号outputrs232_tx; // RS232发送数据信号wirebps_start1,bps_start2,bps_start3; //接收到数据后，波特率时钟启动信号置位wireclk_bps1,clk_bps2,clk_bps3; wire[7:0]rx_data; //接收数据寄存器，//----------------------------------------------------speed_select speed_rx( .clk(clk), //波特率选择模块 .rst_n(rst_n), .bps_start(bps_start1), .clk_bps(clk_bps1) );my_uart_rx my_uart_rx( .clk(clk), //接收数据模块 .rst_n(rst_n), .rs232_rx(rs232_rx), .rx_data(rx_data), .rx_int(rx_int), .clk_bps(clk_bps1), .bps_start(bps_start1) );/////////////////////////////////////////// speed_select speed_tx( .clk(clk), //波特率选择模块 .rst_n(rst_n), .bps_start(bps_start2), .clk_bps(clk_bps2) );speed_select speed_key( .clk(clk), //波特率选择模块 .rst_n(rst_n), .bps_start(bps_start3), .clk_bps(clk_bps3) ); my_uart_tx my_uart_tx( .clk(clk), //发送数据模块 .rst_n(rst_n), .rx_data(rx_data), .rx_int(rx_int), .rs232_tx(rs232_tx), .clk_bps(clk_bps2), .bps_start(bps_start2), .key_data(key_data), .key_int(key_int), .clk_bps_key(clk_bps3), .bps_start_key(bps_start3) );endmodulespeed_select模块`timescale1ns/1psmodulespeed_select( clk,rst_n, bps_start,clk_bps );inputclk; //50MHz主时钟inputrst_n; //低电平复位信号inputbps_start; //接收到数据后，波特率时钟启动信号置位outputclk_bps; //clk_bps的高电平为接收或者发送数据位的中间采样点`define BPS_PARA 5207 //波特率为9600时的分频计数值50`define BPS_PARA_2 2603 //波特率为9600时的分频计数值的一半，用于数据采样reg[12:0]cnt; //分频计数regclk_bps_r; //波特率时钟寄存器//----------------------------------------------------------reg[2:0]uart_ctrl; //uart波特率选择寄存器//----------------------------------------------------------always@(posedgeclkornegedgerst_n) if(!rst_n)cnt<=13'd0; elseif((cnt==`BPS_PARA)||!bps_start)cnt<=13'd0; //波特率计数清零 elsecnt<=cnt+1'b1; //波特率时钟计数启动always@(posedgeclkornegedgerst_n) if(!rst_n)clk_bps_r<=1'b0; elseif(cnt==`BPS_PARA_2)clk_bps_r<=1'b1; //clk_bps_r高电平为接收数据位的中间采样点,同时也作为发送数据的数据改变点 elseclk_bps_r<=1'b0;assignclk_bps=clk_bps_r;endmodule串口接收模块`timescale1ns/1psmodulemy_uart_rx( clk,rst_n, rs232_rx,rx_data,rx_int, clk_bps,bps_start );inputclk; //50MHz主时钟inputrst_n; //低电平复位信号inputrs232_rx; //RS232接收数据信号inputclk_bps; //clk_bps的高电平为接收或者发送数据位的中间采样点outputbps_start; //接收到数据后，波特率时钟启动信号置位output[7:0]rx_data; //接收数据寄存器，保存直至下一个数据来到outputrx_int; //接收数据中断信号,接收到数据期间始终为高电平//----------------------------------------------------------------regrs232_rx0,rs232_rx1,rs232_rx2,rs232_rx3; //接?帐菁拇嫫鳎瞬ㄓ?wireneg_rs232_rx; //表示数据线接收到下降沿always@(posedgeclkornegedgerst_n)begin if(!rst_n)begin rs232_rx0<=1'b0; rs232_rx1<=1'b0; rs232_rx2<=1'b0; rs232_rx3<=1'b0; end elsebegin rs232_rx0<=rs232_rx; rs232_rx1<=rs232_rx0; rs232_rx2<=rs232_rx1; rs232_rx3<=rs232_rx2; endend //下面的下降沿检测可以滤掉<20ns-40ns的毛刺(包括高脉冲和低脉冲毛刺)， //这里就是用资源换稳定（前提是我们对时间要求不是那么苛刻，因为输入信号打了好几拍） //（当然我们的有效低脉冲信号肯定是远远大于40ns的）assignneg_rs232_rx=rs232_rx3&rs232_rx2&~rs232_rx1&~rs232_rx0; //接收到下降沿后neg_rs232_rx置高一个时钟周期//----------------------------------------------------------------regbps_start_r;reg[3:0]num; //移位次数regrx_int; //接收数据中断信号,接收到数据期间始终为高电平always@(posedgeclkornegedgerst_n) if(!rst_n)begin bps_start_r<=1'bz; rx_int<=1'b0; end elseif(neg_rs232_rx)begin //接收到串口接收线rs232_rx的下降沿标志信号 bps_start_r<=1'b1; //启动串口准备数据接收 rx_int<=1'b1; //接收数据中断信号使能 end elseif(num==4'd12)begin //接收完有用数据信息 bps_start_r<=1'b0; //数据接收完毕，释放波特率启动信号 rx_int<=1'b0; //接收数据中断信号关闭 endassignbps_start=bps_start_r;//----------------------------------------------------------------reg[7:0]rx_data_r; //串口接收数据寄存器，保存直至下一个数据来到//----------------------------------------------------------------reg[7:0]rx_temp_data; //当前接收数据寄存器always@(posedgeclkornegedgerst_n) if(!rst_n)begin rx_temp_data<=8'd0; num<=4'd0; rx_data_r<=8'd0; end elseif(rx_int)begin //接收数据处理 if(clk_bps)begin //读取并保存数据,接收数据为一个起始位，8bit数据，1或2个结束位 num<=num+1'b1; case(num) 4'd1:rx_temp_data[0]<=rs232_rx; //锁存第0bit 4'd2:rx_temp_data[1]<=rs232_rx; //锁存第1bit 4'd3:rx_temp_data[2]<=rs232_rx; //锁存第2bit 4'd4:rx_temp_data[3]<=rs232_rx; //锁存第3bit 4'd5:rx_temp_data[4]<=rs232_rx; //锁存第4bit 4'd6:rx_temp_data[5]<=rs232_rx; //锁存第5bit 4'd7:rx_temp_data[6]<=rs232_rx; //锁存第6bit 4'd8:rx_temp_data[7]<=rs232_rx; //锁存第7bit default:; endcase end elseif(num==4'd12)begin //我们的标准接收模式下只有1+8+1(2)=11bit的有效数据 num<=4'd0; //接收到STOP??后结束,num清零 rx_data_r<=rx_temp_data; //把数据锁存到数据寄存器rx_data中 end endassignrx_data=rx_data_r; endmodule串口接收模块`timescale1ns/1psmodulemy_uart_tx( clk,rst_n, rx_data,rx_int,rs232_tx, clk_bps,bps_start, key_data,key_int,clk_bps_key,bps_start_key //键盘输入数据 );inputclk; //50MHz主时钟inputrst_n; //低电平复位信号inputclk_bps; //clk_bps_r高电平为接收数据位的中间采样点,同时也作为发送数据的数据改变点input[7:0]rx_data; //接收数据寄存器inputrx_int; //接收数据中断信号,接收到数据期间始终为高电平,在该模块中利用它的下降沿来启动串口发送数据input[7:0]key_data;//键盘按键对应的ASCII码inputkey_int;//向串口发送键盘按键ASCII码的中断信号,不需??发送数据时该数据线应时钟为高inputclk_bps_key;//键盘输入数据对应的波特率时钟outputbps_start_key; //开始产生波特率??钟，该信号送给键盘ASCII码对应的那??speed_select??择模块outputrs232_tx; //RS232发送数据信号outputbps_start; //接收或者要发送数据，波特率时钟启动信号置位//---------------------------------------------------------regrx_int0,rx_int1,rx_int2; //rx_int信号寄存器，捕捉下降沿滤波用wireneg_rx_int; //rx_int下降沿标志位regkey_int0,key_int1,key_int2; //key_int信号寄存器，捕捉下降沿滤波用wirene