版权说明:本文档由用户提供并上传,收益归属内容提供方,若内容存在侵权,请进行举报或认领
文档简介
嵌入式系统设计与应用嵌入式系统设计与应用STM32F103MCU
本课程的主要内容STM32F103MCU
本课程的主要内容主要内容Cortex-M3的总结STM32F系列的特点STM32F103系列的特点STM32F103的概述STM32F103的外特性STM32F103的内特性STM32F103的SFRSTM32F103的应用主要内容Cortex-M3的总结主要参考资料STM32F103xxx_Datasheet.pdfSTM32F103xxx_Reference_Manual.pdfSTM32F103xxx_Library_Manual.pdfRVMDK>3.2主要参考资料STM32F103xxx_Datasheet.pCortex-M3的总结Cortex-M3的总结CM3NVIC……Cortex-M3的总结Cortex-M3的总结Cortex-M3的总结Cortex-M3的特性Cortex-M3blockdiagramCortex-M3的总结Cortex-M3的特性Cortex-M3的总结Cortex-M3的特性ProcessorcoreARMv7-Marchitecture.Themainfeatures:Thumb-2instructionsetsubset.HarvardArchitecturewithdataload/store.Three-stagepipeline.Singlecycle32-bitmultiply.Hardwaredivide.ThumbandDebugstates.HandlermodesandThreadmodes.withouttheoverheadofstatesavingandrestorationbetweeninterrupts.Interruptible-continuedLDM/STM,PUSH/POP.ARMv6compatibleBE8andLEaccesssupport.ARMv6compatibleunalignedaccesssupport.Cortex-M3的总结Cortex-M3的特性Cortex-M3的总结Cortex-M3的特性ProcessorcoreARMv7-Marchitecture.Themainfeatures:LowlatencyISRentryandexit.—Processorstatesavingandrestoration,withnoinstructionfetchoverhead.Exceptionvectorisfetchedfrommemoryinparallelwiththestatesaving,enablingfasterISRentry.—Supportforlatearriving(迟来)interrupts.—Tightlycoupledinterfacetointerruptcontrollerenablingefficientprocessingoflate-arriving(迟来)interrupts.—Tail-chaining(尾连)ofinterrupts,enablingback-to-back(背靠背)interruptprocessingCortex-M3的总结Cortex-M3的特性Cortex-M3的总结Cortex-M3的特性ProcessorcoreRegistersTheprocessorcontains:13generalpurpose32-bitregisters,R0toR12LinkRegister(LR) -R14ProgramCounter(PC) -R15ProgramStatusRegister,xPSRtwobankedSPregisters. -R13Cortex-M3的总结Cortex-M3的特性Cortex-M3的总结Cortex-M3的特性ProcessorcoreMemoryinterfaceTheprocessorhasaHarvardinterfacetoenablesimultaneousinstructionfetcheswithdataload/stores.Memoryaccessesarecontrolledby:AseparateLoadStoreUnit(LSU)thatdecouplesloadandstoreoperationsfromtheArithmeticandLogicUnit(ALU).A3-wordentryPrefetchUnit(PFU).Onewordisfetchedatatime.ThiscanbetwoThumbinstructions:oneword-alignedThumb32-bitinstruction;theupper/lowerhalfwordofahalfword-alignedThumb32-bitinstructionwithoneThumbinstruction,orthelower/upperhalfwordofanotherhalfword-alignedThumb32-bitinstruction.Cortex-M3的总结Cortex-M3的特性Cortex-M3的总结Cortex-M3的特性ProcessorcoreNVICTheNVICistightlycoupledtotheprocessorcore.Thisfacilitateslowlatencyexceptionprocessing.Themainfeaturesinclude:aconfigurablenumberofexternalinterrupts,from1to240aconfigurablenumberofbitsofpriority,fromthreetoeightbitslevelandpulseinterruptsupportdynamicreprioritizationofinterruptsprioritygroupingsupportfortail-chainingofinterruptsprocessorstateautomaticallysavedoninterruptentry,andrestoredoninterruptexit,withnoinstructionoverhead.Cortex-M3的总结Cortex-M3的特性Cortex-M3的总结Cortex-M3的特性ProcessorcoreBusmatrixThebusmatrixconnectstheprocessoranddebuginterfacetotheexternalbuses.Thebusmatrixinterfacestothefollowingexternalbuses:ICodebus.Thisisforinstructionandvectorfetchesfromcodespace,itisa32-bitAHB-Litebus.DCodebus.Thisisfordataload/storesanddebugaccessestocodespace.itisa32-bitAHB-Litebus.Systembus.Thisisforinstructionandvectorfetches,dataLD/STanddebugaccessestosystemspace.Thisisa32-bitAHB-Litebus.PPB.ThisisfordataLD/STanddebugaccessestoPPBspace.Thisisa32-bitAPB(v3.0)bus.Cortex-M3的总结Cortex-M3的特性Cortex-M3的总结Cortex-M3的特性ProcessorcoreBusmatrixThebusmatrixalsocontrolsthefollowing:Unalignedaccesses.Thebusmatrixconvertsunalignedprocessoraccessesintoalignedaccesses.Bit-banding.Thebusmatrixconvertsbit-bandaliasaccessesintobit-bandregionaccesses.Itperforms:—bitfieldextractforbit-bandloads;—atomicread-modify-writeforbit-bandstores.Writebuffering.Thebusmatrixcontainsaone-entrywritebuffertodecouplebusstallsfromtheprocessorcore.Cortex-M3的总结Cortex-M3的特性Cortex-M3的总结Cortex-M3的特性ProcessorcoreDWTYoucanconfiguretheimplementationtoincludeaDWT.Ifpresent,youcanconfiguretheDWTtoincorporatethefollowingdebugfunctionality:fourcomparatorsthatyoucanconfigureeitherasahardwarewatchpoint,anETMtrigger,aPCsamplereventtrigger,oradataaddresssamplereventtriggerseveralcountersoradatamatcheventtriggerforperformanceprofiling(性能分析)configurabletoemitPCsamplesatdefinedintervals,andtoemitinterrupteventinformation.Cortex-M3的总结Cortex-M3的特性Cortex-M3的总结Cortex-M3的特性ProcessorcoreETMYoucanconfigurethesystematimplementationtoincludeanETM.Thisisalow-costtracemacrocellthatsupportsinstructiontraceonly.WICYoucanconfiguretheimplementationtoincludeaWake-upInterruptController(WIC).Cortex-M3的总结Cortex-M3的特性Cortex-M3的总结Cortex-M3的编程模式Abouttheprogrammer’smodelTheprocessorarchitectureistheARMv7-M.InstructionsarchitectureistheThumb-2.Operatingmodes:Theprocessorsupportstwomodesofoperation,ThreadmodeandHandlermode:ThreadmodeisenteredonReset,andcanbeenteredasaresultofanexceptionreturn.PrivilegedandUser(Unprivileged)codecanruninThreadmode.Handlermodeisenteredasaresultofanexception.AllcodeisprivilegedinHandlermode.Cortex-M3的总结Cortex-M3的编程模式Cortex-M3的总结Cortex-M3的编程模式Abouttheprogrammer’smodelOperatingstatesTheprocessorcanoperateinoneoftwooperatingstates:Thumb-2state.Thisisnormalexecutionrunning16-bitand32-bithalfwordalignedThumbinstructions.DebugState.Thisisthestatewheninhaltingdebug.Cortex-M3的总结Cortex-M3的编程模式Cortex-M3的总结Cortex-M3的编程模式PrivilegedaccessanduseraccessCodecanexecuteasprivilegedoruser:User(Unprivileged)executionlimitsorexcludesaccesstosomeresources.Privilegedexecutionhasaccesstoallresources.Handlermodeisalwaysprivileged.Threadmodecanbeprivilegedorunprivileged.WhenThreadmodehasbeenchangedfromprivilegedtouser,itcannotchangeitselfbacktoprivileged.OnlyaHandlercanchangetheprivilegeofThreadmode.Handlermodeisalwaysprivileged.Cortex-M3的总结Cortex-M3的编程模式Cortex-M3的总结Cortex-M3的编程模式PrivilegedaccessanduseraccessMainstackandprocessstackOutofreset,allcodeusesthemainstack.AnexceptionhandlersuchasSVCcanchangethestackusedbyThreadmodefrommainstacktoprocessstackbychangingtheEXC_RETURNvalueitusesonexit.Allexceptionscontinuetousethemainstack.Thestackpointer,r13,isabankedregisterthatswitchesbetweenSP_mainandSP_process.Onlyonestack,theprocessstackorthemainstack,isvisible,usingr13,atanytime.ItisalsopossibletoswitchfrommainstacktoprocessstackwhileinThreadmodebywritingtoCONTROL[1]usingtheMSRinstruction,inadditiontobeingselectableusingtheEXC_RETURNvaluefromanexitfromHandlermode.Cortex-M3的总结Cortex-M3的编程模式Cortex-M3的总结Cortex-M3的编程模式RegistersTheprocessorhasthefollowing32-bitregisters:13general-purposeregisters,r0-r12Stackpointaliasofbankedregisters,SP_processandSP_mainLinkregister,r14Programcounter,r15Oneprogramstatusregister,xPSR.Figureshowstheprocessorregisterset.Cortex-M3的总结Cortex-M3的编程模式Cortex-M3的总结Cortex-M3的编程模式RegistersTheprocessorhasthefollowing32-bitregisters:13general-purposeregisters,r0-r12Stackpointaliasofbankedregisters,SP_processandSP_mainLinkregister,r14Programcounter,r15Oneprogramstatusregister,xPSR.Figureshowstheprocessorregisterset.Cortex-M3的总结Cortex-M3的编程模式Cortex-M3的总结Cortex-M3的编程模式RegistersGeneral-purposeregistersThegeneral-purposeregistersr0-r12havenospecialarchitecturally-defineduses.Mostinstructionsthatcanspecifyageneral-purposeregistercanspecifyr0-r12.LowregistersRegistersr0-r7areaccessiblebyallinstructionsthatspecifyageneral-purposeregister.HighregistersRegistersr8-r12areaccessiblebyall32-bitinstructionsthatspecifyageneral-purposeregister.Registersr8-r12arenotaccessiblebyall16-bitinstructions.Cortex-M3的总结Cortex-M3的编程模式Cortex-M3的总结Cortex-M3的编程模式RegistersTher13havefollowingspecialfunctions:StackpointerRegisterr13isusedastheStackPointer(SP).BecausetheSPignoreswritestobits[1:0],itisautoalignedtoaword,four-byteboundary.HandlermodealwaysusesSP_main,butyoucanconfigureThreadmodetouseeitherSP_mainorSP_process.Ther14havefollowingspecialfunctions:LinkregisterRegisterr14isthesubroutineLinkRegister(LR).TheLRreceivesthereturnaddressfromPCwhenaBranchandLink(BL)orBranchandLinkwithExchange(BLX)instructionisexecuted.Cortex-M3的总结Cortex-M3的编程模式Cortex-M3的总结Cortex-M3的编程模式RegistersTher14havefollowingspecialfunctions:TheLRisalsousedforexceptionreturn.Atallothertimes,youcantreatr14asageneral-purposeregister.Ther15havefollowingspecialfunctions:ProgramcounterRegisterr15istheProgramCounter(PC).Bit[0]isalways0,soinstructionsarealwaysalignedtowordorhalfwordboundaries.Cortex-M3的总结Cortex-M3的编程模式Cortex-M3的总结Cortex-M3的编程模式RegistersSpecial-purposeProgramStatusRegisters(xPSR)Processorstatusatthesystemlevelbreaksdownintothreecategories:ApplicationPSRInterruptPSRExecutionPSRTheycanbeaccessedasindividualregisters,acombinationofanytwofromthree,oracombinationofallthreeusingtheMovetoRegisterfromStatus(MRS)andMSRinstructions.Cortex-M3的总结Cortex-M3的编程模式Cortex-M3的总结Cortex-M3的编程模式RegistersSpecial-purposeProgramStatusRegisters(xPSR)ApplicationPSRTheApplicationPSR(APSR)containstheconditioncodeflags.Beforeenteringanexception,theprocessorsavestheconditioncodeflagsonthestack.YoucanaccesstheAPSRwiththeMSR(2)andMRS(2)instructions.FigureshowsthebitassignmentsoftheAPSR.Cortex-M3的总结Cortex-M3的编程模式Cortex-M3的总结Cortex-M3的编程模式RegistersxPSRAPSRCortex-M3的总结Cortex-M3的编程模式Cortex-M3的总结Cortex-M3的编程模式RegistersxPSRInterruptPSRTheInterruptPSR(IPSR)containstheInterruptServiceRoutine(ISR)numberofthecurrentexceptionactivation.Cortex-M3的总结Cortex-M3的编程模式Cortex-M3的总结Cortex-M3的编程模式RegistersxPSRIPSRCortex-M3的总结Cortex-M3的编程模式Cortex-M3的总结Cortex-M3的编程模式RegistersxPSRExecutionPSRTheExecutionPSR(EPSR)containstwooverlappingfields:theInterruptible-ContinuableInstruction(ICI)fieldforinterruptedloadmultipleandstoremultipleinstructions;theexecutionstatefieldfortheIf-Then(IT)instruction,andtheThumbstatebit(T-bit).Interruptible-continuableinstructionfield.LoadMultiple(LDM)operationsandStoreMultiple(STM)operationsareinterruptible.TheICIfieldoftheEPSRholdstheinformationrequiredtocontinuetheloadorstoremultiplefromthepointthattheinterruptoccurred.Cortex-M3的总结Cortex-M3的编程模式Cortex-M3的总结Cortex-M3的编程模式RegistersxPSRExecutionPSRIf-thenstatefield:TheITfieldoftheEPSRcontaintheexecutionstatebitsfortheIf-Theninstruction.BecausetheICIfieldandtheITfieldoverlap,loadorstoremultipleswithinanIf-Thenblockcannotbeinterrupt-continued.Cortex-M3的总结Cortex-M3的编程模式Cortex-M3的总结Cortex-M3的编程模式RegistersxPSREPSRCortex-M3的总结Cortex-M3的编程模式Cortex-M3的总结Cortex-M3的编程模式RegistersSavedxPSRbitsOnenteringanexception,theprocessorsavesthecombinedinformationfromthethreestatusregistersonthestack.ThestackedxPSRalsocontainsinformationaboutwhetherthestackwas8-bytealignedornotdependingonthevalueofSTKALIGNintheConfigurationControlRegister.Thisinformationisstoredinbit[9]ofthexPSRonthestack,anditisa1ifthestackwasforcedtobe8-bytealigned.Cortex-M3的总结Cortex-M3的编程模式Cortex-M3的总结Cortex-M3的编程模式MemoryformatsTheprocessorviewsmemoryasalinearcollectionofbytesnumberedinascendingorderfrom0.Forexample:bytes0-3holdthefirststoredwordbytes4-7holdthesecondstoredword.Theprocessorcanaccessdatawordsinmemoryinlittle-endianformatorbig-endianformat.Italwaysaccessescodeinlittle-endianformat.Cortex-M3的总结Cortex-M3的编程模式Cortex-M3的总结Cortex-M3的编程模式Memoryformatslittle-endianformatCortex-M3的总结Cortex-M3的编程模式Cortex-M3的总结Cortex-M3的编程模式InstructionsetsummaryThissectionprovides:asummaryoftheprocessor16-bitinstructionsasummaryoftheprocessor32-bitinstructions.略Cortex-M3的总结Cortex-M3的编程模式Cortex-M3的总结SystemControlSummaryofprocessorregistersDescribestheregistersthatcontrolfunctionality.Itcontainsthefollowing:NestedVectoredInterruptControllerregistersCoredebugregisters;Systemdebugregisters;Debuginterfaceportregisters;MemoryProtectionUnitregisters;TracePortInterfaceUnitregisters;EmbeddedTraceMacrocellregisters.Cortex-M3的总结SystemControlCortex-M3的总结SystemControlSummaryofprocessorregistersDescribestheregistersthatcontrolfunctionality.Itcontainsthefollowing:NestedVectoredInterruptControllerregistersCoredebugregisters;Systemdebugregisters;Debuginterfaceportregisters;MemoryProtectionUnitregisters;TracePortInterfaceUnitregisters;EmbeddedTraceMacrocellregisters.主要介绍NVICCortex-M3的总结SystemControlCortex-M3的总结NVICNVICregistermapTheNVICspaceissplitasfollows:0xE000E000-0xE000E00F:InterruptTypeRegister0xE000E010-0xE000E0FF:SystemTimer0xE000E100-0xE000ECFF:NVIC0xE000ED00-0xE000ED8F:SystemControlBlock:—CPUID—Systemcontrol,configuration,andstatus—Faultreporting0xE000EF00-0xE000EF0F:SoftwareTriggerExceptionRegister0xE000EFD0-0xE000EFFF:IDspace.Cortex-M3的总结NVICCortex-M3的总结NVICNameofregisterTypeAddressResetvalueInterruptControlTypeRegisterRead-only0xE000E004aAuxiliaryControlRegisterRead/write0xE000E0080x0SysTickControlandStatusRegisterRead/write0xE000E0100x00000000SysTickReloadValueRegisterRead/write0xE000E014UnpredictableSysTickCurrentValueRegisterRead/writeclear0xE000E018UnpredictableSysTickCalibrationValueRegisterRead-only0xE000E01CSTCALIBIrq0to31SetEnableRegisterRead/write0xE000E1000x00000000............Irq224to239SetEnableRegisterRead/write0xE000E11C0x00000000Irq0to31ClearEnableRegisterRead/write0xE000E1800x00000000............Irq224to239ClearEnableRegisterRead/write0xE000E19C0x00000000Irq0to31SetPendingRegisterRead/write0xE000E2000x00000000............Irq224to239SetPendingRegisterRead/write0xE000E21C0x00000000Irq0to31ClearPendingRegisterRead/write0xE000E2800x00000000............Irq224to239ClearPendingRegisterRead/write0xE000E29C0x00000000Irq0to31ActiveBitRegisterRead-only0xE000E3000x00000000............Irq224to239ActiveBitRegisterRead-only0xE000E31C0x00000000Cortex-M3的总结NVICNameofregistCortex-M3的总结NVICNameofregisterTypeAddressResetvalueIrq0to3PriorityRegisterRead/write0xE000E4000x00000000............Irq236to239PriorityRegisterRead/write0xE000E4EC0x00000000CPUIDBaseRegisterRead-only0xE000ED000x412FC230InterruptControlStateRegisterRead/writeorread-only0xE000ED040x00000000VectorTableOffsetRegisterRead/write0xE000ED080x00000000ApplicationInterrupt/ResetControlRegisterRead/write0xE000ED0C0x00000000SystemControlRegisterRead/write0xE000ED100x00000000ConfigurationControlRegisterRead/write0xE000ED140x00000200SystemHandlers4-7PriorityRegisterRead/write0xE000ED180x00000000SystemHandlers8-11PriorityRegisterRead/write0xE000ED1C0x00000000SystemHandlers12-15PriorityRegisterRead/write0xE000ED200x00000000SystemHandlerControlandStateRegisterRead/write0xE000ED240x00000000ConfigurableFaultStatusRegistersRead/write0xE000ED280x00000000HardFaultStatusRegisterRead/write0xE000ED2C0x00000000DebugFaultStatusRegisterRead/write0xE000ED300x00000000MemManageAddressRegisterRead/write0xE000ED34UnpredictableBusFaultAddressRegisterRead/write0xE000ED38UnpredictableAuxiliaryFaultStatusRegisterRead/write0xE000ED3C0x00000000PFR0:ProcessorFeatureregister0Read-only0xE000ED400x00000030PFR1:ProcessorFeatureregister1Read-only0xE000ED440x00000200Cortex-M3的总结NVICNameofregistCortex-M3的总结NVICNameofregisterTypeAddressResetvalueDFR0:DebugFeatureregister0Read-only0xE000ED480x00100000AFR0:AuxiliaryFeatureregister0Read-only0xE000ED4C0x00000000MMFR0:MemoryModelFeatureregister0Read-only0xE000ED500x00000030MMFR1:MemoryModelFeatureregister1Read-only0xE000ED540x00000000MMFR2:MemoryModelFeatureregister2Read-only0xE000ED580x00000000MMFR3:MemoryModelFeatureregister3Read-only0xE000ED5C0x00000000ISAR0:ISAFeatureregister0Read-only0xE000ED600x01141110ISAR1:ISAFeatureregister1Read-only0xE000ED640x02111000ISAR2:ISAFeatureregister2Read-only0xE000ED680x21112231ISAR3:ISAFeatureregister3Read-only0xE000ED6C0x01111110ISAR4:ISAFeatureregister4Read-only0xE000ED700x01310102SoftwareTriggerInterruptRegisterWriteOnly0xE000EF00-Peripheralidentificationregister(PID4)Read-only0xE000EFD00x04Peripheralidentificationregister(PID5)Read-only0xE000EFD40x00Peripheralidentificationregister(PID6)Read-only0xE000EFD80x00Peripheralidentificationregister(PID7)Read-only0xE000EFDC0x00PeripheralidentificationregisterBits[7:0](PID0)Read-only0xE000EFE00x00PeripheralidentificationregisterBits[15:8](PID1)Read-only0xE000EFE40xB0PeripheralidentificationregisterBits[23:16](PID2)Read-only0xE000EFE80x2BPeripheralidentificationregisterBits[31:24](PID3)Read-only0xE000EFEC0x00Cortex-M3的总结NVICNameofregistCortex-M3的总结NVICNameofregisterTypeAddressResetvalueComponentidentificationregisterBits[7:0](CID0)ReadOnly0xE000EFF00x0DComponentidentificationregisterBits[15:8](CID1)Read-only0xE000EFF40xE0ComponentidentificationregisterBits[23:16](CID2)Read-only0xE000EFF80x05ComponentidentificationregisterBits[31:24](CID3)Read-only0xE000EFFC0xB1Cortex-M3的总结NVICNameofregistCortex-M3的总结MemoryMapDescribestheprocessorfixedmemorymapanditsbit-bandingfeature.Itcontainsthefollowingsections:AboutthememorymapBit-bandingROMmemorytableCortex-M3的总结MemoryMapCortex-M3的总结MemoryMapCortex-M3的总结MemoryMapCortex-M3的总结MemoryMapMemoryMapInterfaceCodeInstructionfetchesareperformedovertheICodebus.DataaccessesareperformedovertheDCodebus.SRAMInstructionfetchesanddataaccessesareperformedoverthesystembus.SRAM_bitbandAliasregion.Dataaccessesarealiases.Instructionaccessesarenotaliases.PeripheralInstructionfetchesanddataaccessesareperformedoverthesystembus.Periph_bitbandAliasregion.Dataaccessesarealiases.Instructionaccessesarenotaliases.ExternalRAMInstructionfetchesanddataaccessesareperformedoverthesystembus.ExternalDeviceInstructionfetchesanddataaccessesareperformedoverthesystembus.PrivatePeripheralBus(PPB)Accessesto:areperformedtotheprocessorinternalPPB.•InstrumentationTraceMacrocell(ITM)•NestedVectoredInterruptController(NVIC)•FlashpatchandBreakpoint(FPB)•DataWatchpointandTrace(DWT)•MemoryProtectionUnit(MPU)Accessesto:areperformedovertheexternalPPBinterface.•TracePointInterfaceUnit(TPIU)•EmbeddedTraceMacrocell(ETM)•SystemareasofthePPBmemorymapThismemoryregionisExecuteNever(XN),andsoinstructionfetchesareprohibited.AnMPU,ifpresent,cannotchangethis.SystemSystemsegmentforvendorsystemperipherals.ThismemoryregionisXN,andsoinstructionfetchesareprohibited.AnMPU,ifpresent,cannotchangethis.Cortex-M3的总结MemoryMapMemoryMCortex-M3的总结MemoryMapMemoryregionpermissionsWBWA:WritebackwriteallocateNameRegionDevicetypeXNCacheCode0x00000000-0x1FFFFFFFNormal-WTSRAM0x20000000-0x3FFFFFFFNormal-WBWASRAM_1M+0000000---SRAM_31M+0100000--SRAM_bitband+2000000Internal--SRAM+4000000---Peripheral0x40000000-0x5FFFFFFFDeviceXN-Periph_1IM+0000000---Periph_31IM+0100000---Periph_bitband+2000000Internal--Peripheral+4000000---ExternalRAM0x60000000-0x7FFFFFFFNormal-WBWAExternalRAM0x80000000-0x9FFFFFFFNormal-WTExternalDevice0xA0000000-0xBFFFFFFFDeviceXN-ExternalDevice0xC0000000-0xDFFFFFFFDeviceXN-System0xE0000000-0xFFFFFFFF-XN-PrivatePeripheralBus+0000000SO,sharedXN-Vendor_SYS+0100000DeviceXN-Notes:PrivatePeripheralBusandSystemspaceat0xE0000000-0xFFFFFFFFarepermanentlyXN.TheMPUcannotchangethis.Cortex-M3的总结MemoryMapNameRegiCortex-M3的总结MemoryMapBit-bandingTheprocessormemorymapincludestwobit-bandregions.Theseoccupythelowest1MBoftheSRAMandPeripheralmemoryregionsrespectively.Thesebit-bandregionsmapeachwordinanaliasregionofmemorytoabitinabit-bandregionofmemory.Thememorymaphastwo32-MBaliasregionsthatmaptotwo1-MBbit-bandregions:Accessestothe32-MBSRAMaliasregionmaptothe1-MBSRAMbit-bandregion.Accessestothe32-MBperipheralaliasregionmaptothe1-MBperipheralbit-bandregion.Cortex-M3的总结MemoryMapCortex-M3的总结Bit-bandingPrincipleThemappingformulais:One-bitMappingtoOne-Word!bit_word_offset=(byte_offset×32)+(bit_number×4)bit_word_addr=bit_band_base+bit_word_offsetwhere:Bit_word_offsetisthepositionofthetargetbitinthebit-bandmemoryregion.Byte_offsetisthenumberofthebyteinthebit-bandregionthatcontainsthetargetedbit.Bit_numberisthebitposition(0-7)ofthetargetedbit.Bit_word_addristheaddressofthewordinthealiasmemoryregionthatmapstothetargetedbit.Bit_band_baseisthestartingaddressofthealiasregion.Cortex-M3的总结Bit-bandingCortex-M3的总结Bit-bandingPrincipleFigureshowsexamplesofbit-bandmappingbetweentheSRAMbit-bandaliasregionandtheSRAMbit-bandregion:Thealiaswordat0x23FFFFE0mapstobit[0]ofthebit-bandbyteat0x200FFFFF:0x23FFFFE0=0x22000000+(0xFFFFF*32)+0*4.Thealiaswordat0x23FFFFFCmapstobit[7]ofthebit-bandbyteat0x200FFFFF:0x23FFFFFC=0x22000000+(0xFFFFF*32)+7*4.Thealiaswordat0x22000000mapstobit[0]ofthebit-bandbyteat0x20000000:0x22000000=0x22000000+(0*32)+0*4.Thealiaswordat0x2200001Cmapstobit[7]ofthebit-bandbyteat0x20000000:0x2200001C=0x22000000+(0*32)+7*4.Cortex-M3的总结Bit-bandingCortex-M3的总结Bit-bandingFigureCortex-M3的总结Bit-bandingCortex-M3的总结Bit-bandingDirectlyaccessinganaliasregionWritingtoawordinthealiasregionhasthesameeffectasaread-modify-writeoperationonthetargetedbitinthebit-bandregion.Bit[0]ofthevaluewrittentoawordinthealiasregiondeterminesthevaluewrittentothetargetedbitinthebit-bandregion.Writingavaluewithbit[0]setwritesa1tothebit-bandbit,andwritingavaluewithbit[0]clearedwritesa0tothebit-bandbit.Bits[31:1]ofthealiaswordhavenoeffectonthebit-bandbit.Writing0x01hasthesameeffectaswriting0xFF.Writing0x00hasthesameeffectaswriting0x0E.Cortex-M3的总结Bit-bandingCortex-M3的总结Bit-bandingDirectlyaccessinganaliasregionReadingawordinthealiasregionreturnseither0x01or0x00.Avalueof0x01indicatesthatthetargetedbitinthebit-bandregionisset.Avalueof0x00indicatesthatthetargetedbitisclear.Bits[31:1]arezero.Directlyaccessingabit-bandregionYoucandirectlyaccessthebit-bandregionwithnormalreadsandwrites,andwritestothatregion.Cortex-M3的总结Bit-bandingCortex-M3的总结ROMmemorytableOffsetValueNameDescription0x0000xFFF0F003NVICPointstotheNVICat0xE000E000.0x0040xFFF02002or003ifpresentDWTPointstotheDataWatchpointandTraceblockat0xE0001000.Valuehasbit[0]setifDWTispresent.0x0080xFFF03002or003ifpresentFPBPointstotheFlashPatchandBreakpointblockat0xE0002000.Valuehasbit[0]setto1ifFPBispresent.0x00C0xFFF01002or003ifpresentITMPointstotheInstrumentationTraceblockat0xE0000000.Valuehasbit[0]setifITMispresent.0x0100xFFF41002or003ifpresentTPIUPointstotheTPIU.Valuehasbit[0]setto1ifTPIUispresent.TPIUisat0xE0040000.0x0140xFFF42002or003ifpresentETMPointstotheETM.Valuehasbit[0]setto1ifETMispresent.ETMisat0xE0041000.0x0180EndMarkstheendoftheROMtable.IfCoreSightcomponentsareadded,theyareaddedstartingfromthislocationandtheEndmarkerismovedtothenextlocationaftertheadditionalcomponents.0xFCC0x1MEMTYPEBits[31:1]RAZ.Bit[0]issetwhenthesystemmemorymapisaccessibleusingtheDAP.Bit[0]isclearwhenonlydebugresourcesareaccessibleusingtheDAP.Cortex-M3的总结ROMmemorytableOfCortex-M3的总结ROMmemorytableOffsetValueNameDescription0xFD00x0PID4-0xFD40x0PID5-0xFD80x0PID6-0xFDC0x0PID7-0xFE00x0PID0-0xFE40x0PID1-0xFE80x0PID2-0xFEC0x0PID3-0xFF00x0DCID0-0xFF40x10CID1-0xFF80x05CID2-0xFFC0xB1CID3-Cortex-M3的总结ROMmemorytableOfCortex-M3的总结ExceptionsDescribestheexceptionmodeloftheprocessor.Itcontainssections:AbouttheexceptionmodelExceptiontypesExceptionpriorityPrivilegeandstacksPre-emptionTail-chainingLate-arrivingExitResetsExceptioncontroltransferSettingupmultiplestacksAbortmodelActivationlevelsFlowchartsCortex-M3的总结ExceptionsCortex-M3的总结ExceptionsAbouttheexceptionmodelNestedVectoredInterruptController=NVICTheprocessorandNVICprioritizeandhandleallexceptions.AllexceptionsarehandledinHandlermode.Processorstateisautomaticallystoredtothestackonanexception,andautomaticallyrestoredfromthestackattheendoftheInterruptServiceRoutine(ISR).Thevectorisfetchedinparalleltothestatesaving,enablingefficientinterruptentry.Theprocessorsupportstail-chainingthatenablesback-to-backinterruptswithouttheoverheadofstatesavingandrestoration.Cortex-M3的总结ExceptionsCortex-M3的总结ExceptionsAbouttheexceptionmodelThefollowingfeaturesenableefficient,lowlatencyexceptionhandling:Automaticstatesavingandrestoring.TheprocessorpushesstateregistersonthestackbeforeenteringtheISR,andpopsthemaf
温馨提示
- 1. 本站所有资源如无特殊说明,都需要本地电脑安装OFFICE2007和PDF阅读器。图纸软件为CAD,CAXA,PROE,UG,SolidWorks等.压缩文件请下载最新的WinRAR软件解压。
- 2. 本站的文档不包含任何第三方提供的附件图纸等,如果需要附件,请联系上传者。文件的所有权益归上传用户所有。
- 3. 本站RAR压缩包中若带图纸,网页内容里面会有图纸预览,若没有图纸预览就没有图纸。
- 4. 未经权益所有人同意不得将文件中的内容挪作商业或盈利用途。
- 5. 人人文库网仅提供信息存储空间,仅对用户上传内容的表现方式做保护处理,对用户上传分享的文档内容本身不做任何修改或编辑,并不能对任何下载内容负责。
- 6. 下载文件中如有侵权或不适当内容,请与我们联系,我们立即纠正。
- 7. 本站不保证下载资源的准确性、安全性和完整性, 同时也不承担用户因使用这些下载资源对自己和他人造成任何形式的伤害或损失。
最新文档
- 2024届贵州省贵阳市普通中学高三入学考试数学试题试卷
- Unit2 A new student Story time(说课稿)-2024-2025学年译林版(三起)英语五年级上册
- 布草收发劳务合同
- 裱花师傅劳动合同总结
- 顶板事故应急演练
- 物联网通信导论课件
- 姿态敏感器相关行业投资规划报告范本
- 缓控释制剂相关行业投资方案
- 电工材料:电气相关项目投资计划书范本
- 湿法混合颗粒机相关行业投资方案
- 火力发电厂设计技术规程(热控部分)
- 工装验证报告
- 中医师承学员报名申请表
- MSDS(T-35)DBE溶剂
- DFMEA模板(完整版)
- 实验室6S管理实施细则
- 灭火和应急疏散预案演练记录表
- 学习解读2021年《全民科学素质行动规划纲要(2021—2035年)》PPT演示课件
- 施工企业物资核销综述
- 赴广东学习考察职业教育心得体会及办学思路.doc
- 固定资产分类及折旧年限
评论
0/150
提交评论