VHDL程序的设计题

.PAGE....VHDL程序设计题四、编程题〔共50分1、请补全以下二选一VHDL程序〔本题10分Entitymuxisport<d0,d1,sel:inbit;q:outBIT>;<2>endmux;architectureconnectofMUXis<4>signaltmp1,TMP2,tmp3:bit;<6>begincale:blockbegintmp1<=d0andsel;tmp2<=d1and<notsel>tmp3<=tmp1andtmp2;q<=tmp3;<8>endblockcale;endCONNECT;<10>2、编写一个2输入与门的VHDL程序,请写出库、程序包、实体、构造体相关语句,将端口定义为标准逻辑型数据结构〔本题10分&&abyLIBRARYIEEE;;〔2ENTITYnand2ISPORT<a,b:INSTD_LOGIC;〔4y:OUTSTD_LOGIC>;〔6ENDnand2;ARCHITECTUREnand2_1OFnand2IS〔8BEGINy<=aNANDb;--与y<=NOT<aANDb>;等价〔10ENDnand2_1;3、根据下表填写完成一个3-8线译码器的VHDL程序〔16分。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYdecoder_3_to_8ISPORT<a,b,c,g1,g2a,g2b:INSTD_LOGIC;y:OUTSTD_LOGIC_VECTOR<7DOWNTO0>>;〔2ENDdecoder_3_to_8;ARCHITECTURErtlOFdecoder_3_to_8ISSIGNALindata:STD_LOGIC_VECTOR<2DOWNTO0>; 〔4BEGINindata<=c&b&a; 〔6PROCESS<indata,g1,g2a,g2b>BEGINIF<g1='1'ANDg2a='0'ANDg2b='0'>THEN 〔8CASEindataISWHEN"000"=>y<="11111110";WHEN"001"=>y<="11111101";WHEN"010"=>y<="11111011"; 〔10 WHEN"011"=>y<="11110111";WHEN"100"=>y<="11101111";WHEN"101"=>y<="11011111";WHEN"110"=>y<="10111111"; 〔12 WHEN"111"=>y<="01111111";WHENOTHERS=>y<="XXXXXXXX";ENDCASE;ELSEy<="11111111"; 〔14ENDIF;ENDPROCESS; 〔16ENDrtl;4、三态门电原理图如右图所示,真值表如左图所示,请完成其VHDL程序构造体部分。〔本题14分LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYtri_gateISPORT<din,en:INSTD_LOGIC; dout:OUTSTD_LOGIC>;ENDtri_gate;ARCHITECTUREzasOFtri_gateISBEGIN PROCESS<din,en> BEGIN IF<en=‘1'>THENdout<=din; ELSE dout<=‘Z’; ENDIF; ENDPROCESS;ENDzas;四、编程题〔共50分1、根据一下四选一程序的结构体部分,完成实体程序部分〔本题8分entityMUX4isport<<2>s: instd_logic_vector<1downto0>; <4>d: instd_logic_vector<3downto0>; <6>y: outstd_logic <8>>;endMUX4;architecturebehaveofMUX4isbeginprocess<s> begin if<s="00">then y<=d<0>; elsif<s="01">then y<=d<1>; elsif<s="10">then y<=d<2>; elsif<s="11">then y<=d<3>; else null; endif;endprocess;endbehave;2、编写一个数值比较器VHDL程序的进程〔不必写整个结构框架,要求使能信号g低电平时比较器开始工作,输入信号p=q,输出equ为‘0’,否则为‘1process<p,q> <2> begin ifg='0'then <4> ifp=qthen equ<='0'; <6> else equ<='1'; <8> endif; else equ<='1'; <10> endif; endprocess;3、填写完成一个8-3线编码器的VHDL程序〔16分。Libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entityeight_triis port< b: instd_logic_vector<7downto0>;〔2 en: instd_logic;y: out std_logic_vector<2downto0>〔4 >;endeight_tri;architectureaofeight_triis〔6signalsel:std_logic_vector<8downto0>; begin sel<=en&b;〔8 y<="000”when<sel="100000001”>else "001”when<sel="100000010”>else "010”when<sel="100000100”>else "011”when<sel="100001000”>else "100”when<sel="100010000”>else "101”when<sel="100100000”>else "110”when<sel="101000000”>else "111”when<sel="110000000”>else "zzz";enda;4、图中给出了4位逐位进位全加器,请完成其VHDL程序。〔本题16分libraryIEEE;useIEEE.std_logic_1164.all;useIEEE.std_logic_arith.all;useIEEE.std_logic_unsigned.all;entityfull_addis port< a,b: in std_logic_vector<3downto0>;〔2 carr: inoutstd_logic_vector<4downto0>; sum: out std_logic_vector<3downto0> >;endfull_add;architecturefull_add_archoffull_addiscomponentadder 〔4port< a,b,c: in std_logic; carr: inout std_logic;sum: out std_logic 〔6 >;endcomponent;begin carr<0><='0'; u0:adder portmap<a<0>,b<0>,carr<0>,carr<1>,sum<0>>; u1:adder portmap<a<1>,b<1>,carr<1>,carr<2>,sum<1>>; 〔8〔10u2:adder portmap<a<2>,b<2>,carr<2>,carr<3>,sum<2>>; 〔12 u3:adder portmap<a<3>,b<3>,carr<3>,carr<4>,sum<3>>; 〔14〔16endfull_add_arch;四、编程〔共50分1、完成下图所示的触发器。〔本题10分CLRCLRCLKDQQNlibraryIEEE;useIEEE.std_logic_1164.all;entityVposDffisport<CLK,CLR,D:inSTD_LOGIC;2分Q,QN:outSTD_LOGIC>;4分endVposDff;architectureVposDff_archofVposDffisbeginprocess<CLK,CLR>6分beginifCLR='1'thenQ<='0';QN<='1';elsifCLK'eventandCLK='1'thenQ<=D;QN<=notD;8分endif;endprocess;10分endVposDff_arch;2、完成以下4位全加器代码〔本题10分libraryIEEE;useIEEE.std_logic_1164.all;entityfull_addis port< a,b: in std_logic_vector<3downto0>; cin: in std_logic; cout: outstd_logic; sum: out std_logic_vector<3downto0> >;endfull_add;architecturefull_add_archoffull_addiscomponentadderport< a,b,c: in std_logic; carr: out std_logic; sum: out std_logic >;endcomponent;signalc1,c2,c3:std_logic;2分begin u0:adder portmap<a<0>,b<0>,cin,c1,sum<0>>;4分 u1:adder portmap<a<1>,b<1>,c1,c2,sum<1>>;5分 u2:adder portmap<a<2>,b<2>,c2,c3,sum<2>>;6分 u3:adder portmap<a<3>,b<3>,c3,cout,sum<3>>;10分endfull_add_arch;3、补充完整如下代码,使之完成4状态不断循环。<本题10分>ARCHITECTUREarcOFssIStypestatesis<st0,st1,st2,st3>;2分signaloutc:states;4分BEGIN PROCESS<clk> BEGIN IFreset='1'thenoutc<=st0;6分 elsifclk'eventandclk='1'then CASEoutcIS WHENst0=>outc<=st1;7分 WHENst1=>outc<=st2;8分 WHENst2=>outc<=st3;9分 WHENst3=>outc<=st0;10分 WHENOTHERS=>outc<=st0; ENDCASE; endif; ENDPROCESS;ENDarc;4、设计异或门逻辑：〔本题20分如下异或门,填写右边的真值表。〔此项5分ABY000011101110其表达式可以表示为：〔此项5分这一关系图示如下：试编写完整的VHDL代码实现以上逻辑。可以采用任何描述法。〔此项10分libraryieee;useieee.std_logic_1164.all;1分entityyihuo1is port< a,b :instd_logic; y :outstd_logic >;endyihuo1;4分architectureyihuo1_behaviorofyihuo1isbegin7分 process<a,b>y<=axorb; begin〔第2种写法 ifa=bthen y<='0'; else y<='1'; endif; endprocess;endyihuo1_behavior;10分四、编程〔共50分,除特殊声明,实体可只写出PORT语句,结构体要写完整1、用IF语句编写一个二选一电路,要求输入a、b,sel为选择端,输出q。〔本题10分Entitysel2isPort<a,b:instd_logic; sel:instd_logic; q:outstd_logic>;Endsel2; <3>Architectureaofsel2isbegin ifsel=‘0’ q<=a; <6> else q<=b; <9> endif;enda; <10>2、编写一个4位加法计数器VHDL程序的进程〔不必写整个结构框架,要求复位信号reset低电平时计数器清零,变高后,在上升沿开始工作；输入时钟信号为clk,输出为q。〔本题10分Process<reset,clk> <2>begin ifreset=‘0’ q<="0000” elsifclk’eventandclk=‘1’ q<=q+1; <9> endif;endprocess; <10>3、填写完成一个8-3线编码器的真值表〔5分,并写出其VHDL程序〔10分。8-3线编码器真值表enby0y1y21000000000001000000100011000001000101000010000111000100001001001000001011010000001101100000001110xxxxxxxx高阻态entityeight_triis port< b: instd_logic_vector<7downto0>; en: instd_logic; y: out std_logic_vector<2downto0> >;endeight_tri; <3>architectureaofeight_triissignalsel:std_logic_vector<8downto0>; <4> begin sel<=en&b; y<="000”when<sel="100000001”>else "001”when<sel="100000010”>else "010”when<sel="100000100”>else "011”when<sel="100001000”>else "100”when<sel="100010000”>else "101”when<sel="100100000”>else "110”when<sel="101000000”>else "111”when<sel="110000000”>else <9> "zzz"; <10>enda;4、根据已给出的全加器的VHDL程序,试写出一个4位逐位进位全加器的VHDL程序。〔本题15分libraryIEEE;useIEEE.std_logic_1164.all;useIEEE.std_logic_arith.all;useIEEE.std_logic_unsigned.all;entityadderis port< a,b,c: instd_logic;carr: inoutstd_logic;sum: outstd_logic>;endadder;architectureadder_archofadderisbegin sum<=axorbxorc; carr<=<aandb>or<bandc>or<aandc>;endadder_arch;entityfull_addis port< a,b: in std_logic_vector<3downto0>; carr: inoutstd_logic_vector<4downto0>; sum: out std_logic_vector<3downto0> >;endfull_add; <5>architecturefull_add_archoffull_addiscomponentadderport< a,b,c: in std_logic; carr: inout std_logic; sum: out std_logic >;endcomponent; <10>begin carr<0><='0'; u0:adder portmap<a<0>,b<0>,carr<0>,carr<1>,sum<0>>; u1:adder portmap<a<1>,b<1>,carr<1>,carr<2>,sum<1>>; u2:adder portmap<a<2>,b<2>,carr<2>,carr<3>,sum<2>>; u3:adder portmap<a<3>,b<3>,carr<3>,carr<4>,sum<3>>;endfull_add_arch; <15>四、编程〔共50分,除特殊声明,实体可只写出PORT语句,结构体要写完整1、用IF语句编写一个四选一电路,要求输入d0～d3,s为选择端,输出y。〔本题10分entityMUX4is port< s: instd_logic_vector<1downto0>; d: instd_logic_vector<3downto0>; y: outstd_logic >;endMUX4;<3>architecturebehaveofMUX4isbeginprocess<s> begin if<s="00">then y<=d<0>; <4> elsif<s="01">then y<=d<1>; <5> elsif<s="10">then y<=d<2>; <6> elsif<s="11">then y<=d<3>; <7> else null; <9> endif;endprocess;endbehave; <10>2、编写一个数值比较器VHDL程序的进程〔不必写整个结构框架,要求使能信号g低电平时比较器开始工作,输入信号p=q,输出equ为‘0’,否则为‘1process<p,q> <2> begin ifg='0'then <4> ifp=qthen equ_tmp<='0'; <6> else equ_tmp<='1'; <8> endif; else equ_tmp<='1'; <10> endif; endprocess;3、填写完成一个3-8线译码器的真值表〔5分,并写出其VHDL程序〔10分。3-8译码器的真值表ena2a1ay1000000000011001000000101010000001001011000010001100000100001101001000001110010000001111100000000xxx00000000entitytri_eightis port< a: instd_logic_vector<2downto0>; en: instd_logic; y: out std_logic_vector<7downto0> >;endtri_eight; <2>architectureaoftri_eightis signalsel: std_logic_vector<3downto0>; <4>begin sel<0><=a<0>; sel<1><=a<1>; sel<2><=a<2>; se