VLSI系统导论：第三讲 Verilog Basic

VerilogHDLYangJundragon@NationalEngineeringResearchCenterofASICSystemAgendaVerilogBasicsSynthesizableVerilogVerilogRTLModelExampleAgendaVerilogBasicsSynthesizableVerilogVerilogRTLExampleWhatisVerilog1985:GatewayDesignAutomationInc.releasesfirstVerilogsimulator1987:Efficientgatelevelsimulator(Verilog-XL)1989:CadencebuysGateway1990:CadencereleaseslanguagetoOpenVerilogInternational(OVI)1990:Synthesis1993:Moresimulators1995:BecomesIEEE1364-1995standard2001:IEEE1364-2001Now:MostpopularhardwaredescriptionlanguageApplicationAreasofVerilogSystemSpecificationHW/SWPartitionHardwareSpecSoftwreSpecASICFPGAPLDStdPartsBoards&SystemsSoftwareSuitableforalllevelsBehaviorallevelNotsuitableDescriptionofdigitalsystemsonlyBasicLimitationofVerilogAbstractionLevelsinVerilogBehavioralRTLGateLayout(VLSI)OurfocusMainLanguageConcepts(i)ConcurrencyStructureMainLanguageConcepts(ii)ProceduralStatementsTimeUserIdentifiersFormedfrom{[A-Z],[a-z],[0-9],_,$},but

can’tbeginwith$or[0-9]myidentifier

m_y_identifier 3my_identifier $my_identifier _myidentifier$ Casesensitivitymyid

MyidComments// Therestofthelineisacomment/* Multipleline

comment *//* Nesting/*comments*/doNOTwork*/VerilogValueSet0 representslowlogiclevelorfalsecondition1 representshighlogiclevelortrueconditionx representsunknownlogiclevelz representshighimpedancelogiclevelNumbersinVerilog(i)

<size>’<radix><value>8’hax=1010xxxx12’o3zx7=011zzzxxx111NoofbitsBinaryborBOctaloorODecimaldorDHexadecimalhorHConsecutivechars0-f,x,zNumbersinVerilog(ii)Youcaninsert“_”forreadability12’b000_111_010_10012’b00011101010012’o07_24BitextensionMSbit=0,xorzextendthis4’bx1=4’bxx_x1MSbit=1zeroextension4’b1x=4’b00_1xRepresentthesamenumberNumbersinVerilog(iii)IfsizeisommitteditisinferredfromthevalueortakesthesimulationspecificnumberofbitsortakesthemachinespecificnumberofbitsIfradixisommittedtoo..decimalisassumed15=<size>’d15Nets(i)CanbethoughtashardwarewiresdrivenbylogicEqualzwhenunconnectedVarioustypesofnetswirewand (wired-AND)wor (wired-OR)tri (tri-state)Infollowingexamples:Yisevaluated,automatically,everytimeAorBchangesNets(ii)ABYwireY;//declarationassignY=A&B;

BAYwandY;//declarationassignY=A;

assignY=B;worY;//declarationassignY=A;

assignY=B;AYdrtriY;//declarationassignY=(dr)?A:z;

RegistersVariablesthatstorevaluesDonotrepresentrealhardwarebut....realhardwarecanbeimplementedwithregistersOnlyonetype:reg regA,C;//declaration //assignmentsarealwaysdoneinsideaprocedure A=1;

C=A;//Cgetsthelogicalvalue1 A=0;//Cisstill1 C=0;//Cisnow0Registervaluesareupdatedexplicitly!!VectorsRepresentbuses wire[3:0]busA; reg[1:4]busB; reg[1:0]busC;LeftnumberisMSbitSlicemanagement

busC[1]=busA[2]; busC[0]=busA[1];Vectorassignment(byposition!!)

busB[1]=busA[3]; busB[2]=busA[2]; busB[3]=busA[1]; busB[4]=busA[0];busB=busA; busC=busA[2:1];

Integer&RealDataTypesDeclaration

integeri,k; realr;Useasregisters(insideprocedures)

i=1;//assignmentsoccurinsideprocedure r=2.9; k=r;//kisroundedto3Integersarenotinitialized!!Realsareinitializedto0.0TimeDataTypeSpecialdatatypeforsimulationtimemeasuringDeclaration

timemy_time;Useinsideprocedure

my_time=$time;//getcurrentsimtimeSimulationrunsatsimulationtime,notrealtimeArrays(i)Syntax integercount[1:5];//5integers regvar[-15:16];//321-bitregs reg[7:0]mem[0:1023];//10248-bitregsAccessingarrayelementsEntireelement:mem[10]=8’b10101010;Elementsubfield(needstempstorage):reg[7:0]temp;..temp=mem[10];var[6]=temp[2];Arrays(ii)Limitation:Cannotaccessarraysubfieldorentirearrayatonce var[2:9]=???;//WRONG!! var=???;//WRONG!!Nomulti-dimentionalarrays regvar[1:10][1:100];//WRONG!!Arraysdon’tworkfortheRealdatatype realr[1:10];//WRONG!!StringsImplementedwithregs: reg[8*13:1]string_val;//canholdupto13chars .. string_val=“HelloVerilog”;

string_val=“hello”;//MSBytesarefilledwith0

string_val=“Iamoverflowed”;//“I”istruncatedEscapedchars:\n newline\t tab%% %\\ \\“ “LogicalOperators&&logicalAND||logicalOR!logicalNOTOperandsevaluatedtoONEbitvalue:0,1orxResultisONEbitvalue:0,1orx

A=6; A&&B1&&00 B=0; A||!B1||11 C=x; C||Bx||0xBitwiseOperators(i)& bitwiseAND| bitwiseOR~ bitwiseNOT^ bitwiseXOR~^or^~ bitwiseXNOROperationonbitbybitbasisBitwiseOperators(ii)c=~a;c=a&b;a=4’b1010; b=4’b1100;a=4’b1010; b=2’b11;c=a^b;ReductionOperators& AND| OR^ XOR~& NAND~| NOR~^or^~ XNOROnemulti-bitoperandOnesingle-bitresult a=4’b1001; .. c=|a;//c=1|0|0|1=1ShiftOperators>> shiftright<< shiftleftResultissamesizeasfirstoperand,alwayszerofilled

a=4’b1010; ... d=a>>2; //d=0010 c=a<<1; //c=0100ConcatenationOperator

{op1,op2,..} concatenatesop1,op2,..tosinglenumberOperandsmustbesized!! rega; reg[2:0]b,c; .. a=1’b1; b=3’b010; c=3’b101; catx={a,b,c}; //catx=1_010_101 caty={b,2’b11,a}; //caty=010_11_1 catz={b,1}; //WRONG!!Replication.. catr={4{a},b,2{c}}; //catr=1111_010_101101RelationalOperators> greaterthan< lessthan>= greaterorequalthan<= lessorequalthanResultisonebitvalue:0,1orx

1>0 1

’b1x1<=0 x

10<z

xEqualityOperators== logicalequality!= logicalinequality=== caseequality!==caseinequality

4’b1z0x==4’b1z0xx

4’b1z0x!=4’b1z0xx

4’b1z0x===4’b1z0x1

4’b1z0x!==4’b1z0x0Return0,1orxReturn0or1ConditionalOperatorcond_expr?true_expr:false_exprLikea2-to-1mux..ABYselY=(sel)?A:B;01ArithmeticOperators(i)+,-,*,/,%IfanyoperandisxtheresultisxNegativeregisters:regscanbeassignednegativebutaretreatedasunsignedreg[15:0]regA;..regA=-4’d12; //storedas216-12=65524regA/3 evaluatesto21861ArithmeticOperators(ii)Negativeintegers:canbeassignednegativevaluesdifferenttreatmentdependingonbasespecificationornotreg[15:0]regA;integerintA;..intA=-12/3; //evaluatesto-4(nobasespec)intA=-’d12/3;//evaluatesto1431655761(basespec)OperatorPrecedenceUseparenthesestoenforceyourpriorityHierarchicalDesignTopLevelModuleSub-Module1Sub-Module2BasicModule3BasicModule2BasicModule1FullAdderHalfAdderHalfAdderE.g.Modulefin1in2inNout1out2outMmy_modulemodulemy_module(out1,..,inN);outputout1,..,outM;inputin1,..,inN;..//declarations..//descriptionoff(maybe..//sequential)endmoduleEverythingyouwriteinVerilogmustbeinsideamoduleexception:compilerdirectivesExample:HalfAddermodulehalf_adder(S,C,A,B);outputS,C;inputA,B;wireS,C,A,B;assignS=A^B;assignC=A&B;endmoduleHalfAdderABSCABSCExample:FullAddermodulefull_adder(sum,cout,in1,in2,cin);outputsum,cout;inputin1,in2,cin;wiresum,cout,in1,in2,cin;wireI1,I2,I3;half_adderha1(I1,I2,in1,in2);half_adderha2(sum,I3,I1,cin);assigncout=I2||I3;endmoduleInstancenameModulenameHalfAdderha2ABSCHalfAdder1ha1ABSCin1in2cincoutsumI1I2I3HierarchicalNamesha2.ARemembertouseinstancenames,notmodulenamesHalfAdderha2ABSCHalfAdder1ha1ABSCin1in2cincoutsumI1I2I3PortAssignmentsmoduleregornetnetmoduleregornetnetmodulenetnetInputsOutputsInoutsContinuousAssignementsSyntax:assign#del<id>=<expr>;Wheretowritethem:insideamoduleoutsideproceduresProperties:theyallexecuteinparallelareorderindependentarecontinuouslyactiveoptionalnettype!!StructuralModel(GateLevel)Built-ingateprimitives: and,nand,nor,or,xor,xnor,buf,not,bufif0,bufif1,notif0,notif1Usage:nand(out,in1,in2);2-inputNANDwithoutdelayand#2(out,in1,in2,in3);3-inputANDwith2t.u.delaynot#1N1(out,in);NOTwith1t.u.delayandinstancenamexorX1(out,in1,in2);2-inputXORwithinstancenameWritetheminsidemodule,outsideproceduresExample:HalfAdder,

2ndImplementationAssuming:XOR:2t.u.delayAND:1t.u.delaymodulehalf_adder(S,C,A,B);outputS,C;inputA,B;wireS,C,A,B;xor#2(S,A,B);and#1(C,A,B);endmoduleABSCBehavioralModel-Procedures(i)Procedures=sectionsofcodethatweknowtheyexecutesequentiallyProceduralstatements=statementsinsideaprocedure(theyexecutesequentially)e.g.another2-to-1muximplem: begin if(sel==0) Y=B; else Y=A; endExecutionFlowProceduralassignments:Ymustbereg!!BehavioralModel-Procedures(ii)ModulescancontainanynumberofproceduresProceduresexecuteinparallel(inrespecttoeachother)and....canbeexpressedintwotypesofblocks:initial theyexecuteonlyoncealways theyexecuteforever(untilsimulationfinishes)“Initial”BlocksStartexecutionatsimtimezeroandfinishwhentheirlaststatementexecutesmodulenothing;initial $display(“I’mfirst”);initialbegin #50; $display(“Really?”); endendmoduleWillbedisplayedatsimtime0Willbedisplayedatsimtime50“Always”BlocksStartexecutionatsimtimezeroandcontinueuntilsimfinishesEvents(i)@always@(signal1orsignal2or..)

begin .. endalways@(posedgeclk)

begin .. endalways@(negedgeclk)

begin .. endexecutiontriggerseverytimeanysignalchangesexecutiontriggerseverytimeclkchangesfrom0to1executiontriggerseverytimeclkchangesfrom1to0Examples3rdhalfadderimplemmodulehalf_adder(S,C,A,B);outputS,C;inputA,B;regS,C;wireA,B;always@(AorB)begin S=A^B; C=A&&B; endendmoduleBehavioraledge-triggeredDFFimplemmoduledff(Q,D,Clk);outputQ;inputD,Clk;regQ;wireD,Clk;always@(posedgeClk) Q=D;endmoduleEvents(ii)wait(expr)

alwaysbegin wait(ctrl) #10cnt=cnt+1; #10cnt2=cnt2+2; end

e.g.LeveltriggeredDFF?executionloopseverytimectrl=1(levelsensitivetimingcontrol)ExampleabcYWclkresalways@(resorposedgeclk)begin if(res)begin Y=0; W=0; end elsebegin Y=a&b; W=~c; end endTiming(i)initialbegin #5c=1; #5b=0; #5d=c; end051015TimebcdEachassignmentisblockedbyitspreviousoneTiming(ii)initialbegin fork #5c=1; #5b=0; #5d=c; join end051015TimebcdAssignmentsarenotblockedhereProceduralStatements:ifif(expr1) true_stmt1;elseif(expr2) true_stmt2;..else def_stmt;

E.g.4-to-1mux:modulemux4_1(out,in,sel);outputout;input[3:0]in;input[1:0]sel;regout;wire[3:0]in;wire[1:0]sel;always@(inorsel) if(sel==0) out=in[0]; elseif(sel==1) out=in[1]; elseif(sel==2) out=in[2]; else out=in[3];endmoduleProceduralStatements:casecase(expr)item_1,..,item_n: stmt1;item_n+1,..,item_m:stmt2;..default: def_stmt;endcaseE.g.4-to-1mux:modulemux4_1(out,in,sel);outputout;input[3:0]in;input[1:0]sel;regout;wire[3:0]in;wire[1:0]sel;always@(inorsel) case(sel) 0:out=in[0]; 1:out=in[1]; 2:out=in[2]; 3:out=in[3]; endcaseendmoduleProceduralStatements:forfor(init_assignment;cond;step_assignment) stmt;E.g.modulecount(Y,start);output[3:0]Y;inputstart;reg[3:0]Y;wirestart;integeri;initial Y=0;always@(posedgestart) for(i=0;i<3;i=i+1) #10Y=Y+1;endmoduleProceduralStatements:whilewhile(expr)stmt;E.g.modulecount(Y,start);output[3:0]Y;inputstart;reg[3:0]Y;wirestart;integeri;initial Y=0;always@(posedgestart)begin i=0; while(i<3)begin #10Y=Y+1; i=i+1; end endendmoduleProceduralStatements:repeatrepeat(times)stmt;E.g.modulecount(Y,start);output[3:0]Y;inputstart;reg[3:0]Y;wirestart;initial Y=0;always@(posedgestart) repeat(4)#10Y=Y+1;endmoduleCanbeeitheranintegeroravariableProceduralStatements:foreverforeverstmt;Typicalexample:clockgenerationintestmodules

moduletest;regclk;initial begin clk=0; forever#10clk=~clk; endother_module1o1(clk,..);other_module2o2(..,clk,..);endmoduleExecutesuntilsimfinishesTclk=20timeunitsMixedModelCodethatcontainsvariousbothstructureandbehavioralstylesmodulesimple(Y,c,clk,res);outputY;inputc,clk,res;regY;wirec,clk,res;wiren;not(n,c);//gate-levelalways@(resorposedgeclk) if(res) Y=0; else Y=n;endmodulecYclkresnSystemTasks$display(“..”,arg2,arg3,..);muchlikeprintf(),displaysformattedstringinstdoutputwhenencountered$monitor(“..”,arg2,arg3,..);like$display(),but..displaysstringeachtimeanyofarg2,arg3,..Changes$stop;suspendssimwhenencountered$finish;finishessimwhenencountered$fopen(“filename”);returnsfiledescriptor(integer);then,youcanuse$fdisplay(fd,“..”,arg2,arg3,..);or$fmonitor(fd,“..”,arg2,arg3,..);towritetofile$fclose(fd);closesfile$random(seed);returnsrandominteger;giveheranintegerasaseedAlwayswritteninsideprocedures$display&$monitorstringformatCompilerDirectives`include“filename”

insertscontentsoffileintocurrentfile;writeitanywhereincode..`define<text1><text2>text1substitutestext2;e.g.`defineBUSreg[31:0] indeclarationpart: `BUSdata;`timescale<timeunit>/<precision>e.g.`timescale10ns/1ns later: #5a=b;50nsLoopsWhileloopwhile(expression)beginendForLoop integercount;initialfor(count=0;count<10;count++) $display(“count=%d\n”,count);LoopsContinuedRepeatloop repeat(128) //repeatthefollowingblock128times begin $display(“count=%d\n”,count); endForeverloop

regclock; initial begin clock=1’b0; forever#10clock=~clock; #100$finish; endTasksandFunctionsTasks

timingconstructsmultipleoutputs.Functions

purelycombinationalNoTimingcontrol0simulationtimeonlyoneoutput.InvokeotherfunctionbuttasksTaskexample//Defineamodule“operation”thatcontainsatask“bitwise_oper”moduleoperation;reg[7:0]A,B;reg[7:0]AB_AND,AB_OR,AB_XOR;always@(AorB)//invokethetaskwheneverAorBchangesbegin

bitwise_oper(AB_AND,AB_OR,AB_XOR,A,B);end//definethetasktask

bitwise_oper;output[7:0]ab_and,ab_or,ab_xor;input[7:0]a,b;begin

ab_and=a&b;

ab_or=a|b;

ab_xor=a^b;endendtaskendmoduleFunctionexample//Defineamodule“parity”thatcontainsafunction“cal_parity”moduleparity;reg[7:0]data;regparity;always@(data)//invokethefunctionwheneverdatachangesbegin parity=cal_parity(data);end//definethefunctionfunctioncal_parity;input[7:0]data;begin//usetheimplicitinternalregistercal_parity

cal_parity=^data//returnthexorofallthebitsendendfunctionendmoduleParametersmoduledff4bit(Q,D,clk);output[3:0]Q;input[3:0]D;inputclk;reg[3:0]Q;wire[3:0]D;wireclk;always@(posedgeclk) Q=D;endmodulemoduledff2bit(Q,D,clk);output[1:0]Q;input[1:0]D;inputclk;reg[1:0]Q;wire[1:0]D;wireclk;always@(posedgeclk) Q=D;endmodulein[3:0]out[2:0]p_in[3:0]wdwuclkA.Implelementationwithoutparametersmoduletop(out,in,clk);output[1:0]out;input[3:0]in;inputclk;wire[1:0]out;wire[3:0]in;wireclk;wire[3:0]p_in; //internalnetswirewu,wd;assignwu=p_in[3]&p_in[2];assignwd=p_in[1]&p_in[0];dff4bitinstA(p_in,in,clk);dff2bitinstB(out,{wu,wd},clk);//noticetheconcatenation!!endmoduleParameters(ii)A.Implelementationwithoutparameters(cont.)Parameters(iii)moduledff(Q,D,clk);parameterWIDTH=4;output[WIDTH-1:0]Q;input[WIDTH-1:0]D;inputclk;reg[WIDTH-1:0]Q;wire[WIDTH-1:0]D;wireclk;always@(posedgeclk) Q=D;endmoduleB.Implelementationwithparametersmoduletop(out,in,clk);output[1:0]out;input[3:0]in;inputclk;wire[1:0]out;wire[3:0]in;wireclk;wire[3:0]p_in;wirewu,wd;assignwu=p_in[3]&p_in[2];assignwd=p_in[1]&p_in[0];dffinstA(p_in,in,clk);//WIDTH=4,fromdeclarationdffinstB(out,{wu,wd},clk); defparaminstB.WIDTH=2;//WechangedWIDTHforinstBonlyendmoduleTestingYourModulesmoduletop_test;wire[1:0]t_out; //Top’ssignalsreg[3:0]t_in;regclk;topinst(t_out,t_in,clk);//Top’sinstanceinitialbegin //Generateclock clk=0; forever#10clk=~clk;endinitialbegin //Generateremaininginputs $monitor($time,"%b->%b",t_in,t_out); #5t_in=4'b0101; #20t_in=4'b1110; #20t_in[0]=1; #300$finish;endendmoduleAgendaVerilogBasicsSynthesizableVerilogVerilogRTLModelVerificationwithVCSWhatissynthesisIdealInverterCircuitM1OUTINVDDVDDCMOSPL=0.24uW=1.8uM2OUTIN00CMOSNL=0.24UW=0.9UVDDVDD02.5VININ00PULSE02.52n.5n.5n7n20nCLOADOUT020fF.OPTIONSLISTNODEPOST.TRAN200p20n.PRINTTRANV(IN)V(OUT).LIB"tsmc_025um_model"CMOS_MODELS.ENDModuleinverter(input,output);

…endmoduleSynthesisPlace&routingDesignComplierIn&OutDesignComplierDesignOperatingEnvironmentGoals

(Timing,Area,Power)OptimizedDesignReportsSchematicsIntroductionVerilogisbothasimulationandasynthesislanguage.Manycomplexfeaturesarenotreallymeantforsynthesis.Forexample:Initialblocks.$displayEffectiveSynthesisusingVerilogTrytoenvisionthehardwarethatwillbebuiltfromthedescriptionyouarewriting.RefrainfromtryingtouseVerilogasatraditionalprogramminglanguage.Manythingswillhappeninparallelandnotinsequence.Thereareseveralwaysofdescribingthesamecircuit.Trytodescribeitinthemostnaturalwaypossible.Parallel&SequentialWithinmodules:Statementsruninparallel.Withinalwaysblock:Statementscanrunsequentially.module.........always@(...)......end......endmoduleParallelSequentialAlwaysBlocksalways@(eventlist)…Activatedwhenanyoftheeventsintheeventlistoccur.Assignmentsaremadetoregisters.Aregistervariable“holds”itslastassignedvalueunlessmodified.Canmodelbothsequentialandcombinationallogic.CombinationalAlwaysBlocksEventlist:Containsallsignalsusedtocomputefunction.Variables:Variablesmodifiedshouldbedefinedonallpathsthroughblock.CombinationalLogicalways@(aorborcor...)...abcImpliedLatchLatchmustn’tbeusedinASICInternalHowtorecognizeLatch?LbinationcircuitIncompleteeventlistcausesimulatonmismatch(RTLvs.GateLevel)always@(asoraddr)if(as==0)if(addr==1)active=1;elseactive=0;else active=1;SequentialAlwaysBlocksAlwaysblockactivatedbyanedgeonaclock.Resetoptional.Outputonlychangesinresponsetoclock.SequentialLogicalways@(posedge

clk)if(reset==1)...else...abclkNon-BlockingandBlockingmodulenblk_blk(clk,i,p,q);inputclk,i;outputp,q;

regp,q;

always@(posedge

clk)beginp<=i;q<=p;p=i;q=p;endendmoduleiqpiqpDFFwithResetmoduledffr(d,clk,reset,q);inputd,clk,reset;outputq;

regq;

always@(posedge

clkorposedgereset)beginif(reset)q<=0;elseq<=d;endendmoduleFibonacciCountermodulefibonacci(clk,reset,fib);inputclk,reset;output[15:0]fib;wire[15:0]sum,fib;

reg[15:0]fib0,fib1;

assignsum=fib0+fib1;assignfib=fib1;

always@(posedge

clkorposedgereset)beginif(reset)beginfib0<=1;fib1<=1;endelsebeginfib0<=sum;fib1<=fib0;endendendmoduleFourBitAddermoduleadder_v0(cin,a,b,sum,cout);inputcin;input[3:0]a,b;output[3:0]sum;outputcout;wire[2:0]ctmp;

fadderg0(cin,a[0],b[0],sum[0],ctmp[0]);

fadderg1(ctmp[0],a[1],b[1],sum[1],ctmp[1]);

fadderg2(ctmp[1],a[2],b[2],sum[2],ctmp[2]);

fadderg3(ctmp[2],a[3],b[3],sum[3],cout);endmodulemodulefadder(cin,a,b,sum,cout);inputcin,a,b;outputsum,cout;

assignsum=cin^a^b;assigncout=(cin&a)|(a&b)|(cin&b);endmoduleModuleInstantiationTwomethodsofinstantiatingmoduleswithparameters:Option1:adder#(8)addunit1(cin,x,y,sum,cout);Option2:adderaddunit1(cin,x,y,sum,cout);defparam.n=8;FSMParityFSMmoduleparity(clk,reset,i,o);inputclk,reset,i;outputo;

reg

st,next_st,o;parameterst_even=0,st_odd=1;always@(posedge

clkorposedgereset)beginif(reset==1)

st<=st_even;else

st<=next_st;end/*statetransitions*//*outputcomputation*/endmoduleEven/0Odd/1Reseti=1i=1ParityFSM,StateTransitionsalways@(iorst)begin if(i==1)beginif(st==st_even)

next_st=st_odd;else

next_st=st_even;endelse

next_st=st;endEven/0Odd/1Reseti=1i=1ParityFSM,OutputComputationalways@(st)beginif(st==st_even)o=0;elseo=1;endEven/0Odd/1Reseti=1i=1CoinFSMmodulecoin(clk,reset,n,d,o);inputclk,reset,n,d;outputo;

reg[1:0]st,next_st;

rego;parameterst_0=2'b00,st_5=2'b01,st_10=