计数器与分频器VHDL源程序

1、计数器与分频器VHDL源程序通用计数器(可赋初值、模数可调、触发边沿可选、双向计数、具有使能端): library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity countn isgeneric(N: integer:=10); -N 为正整数port(clk,dir: in std_logic;reset: in std_logic;enable: in std_logic;q: out integer range 0 to N-1);end entity;architecture rtl of countn

2、 isbeginprocess (clk)variablecnt: integer range 0 to N-1;-定义中间变量beginif reset = 1 thencnt := 0;-赋初值 0elsif enable = 1 thenif(clkevent and clk=1) then -上升沿计数if dir=1 then -加法计数if(cnt0 ) thencnt:= cnt-1;elsecnt := N-1;end if;end if;end if;end if;q = cnt;-输出计数值end process;end rtl;占空比和分频系数可调的分频器(占空比50%的

3、奇数分频器除外)：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity fdivn isgeneric(n: integer:=10;m: integer:=3 -分频系数=n,占空比m:n； m,n为正整数，mn, n为奇数时m不能等于1/2 n );port(clkin: in std_logic;clkout: out std_logic);end fdivn;architecture a of fdivn issignal

4、cnt: integer range 0 to n-1;-定义中间信号beginprocess(clkin)beginif(clkinevent and clkin=1) then -模 n 加法计数if(cntn-1) thencnt = cnt+1;elsecnt = 0;end if;end if;end process;clkout = 1 when cntm else - cntm时输出高电平，否则输出低电平0;end a;占空比50%的奇数分频器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.

5、all;use ieee.std_logic_arith.all;entity fdivo isgeneric(N: integer:=5);-rate=N，N 是奇数port(clkin : in std_logic;clkout : out std_logic);end fdivo;architecture a of fdivo issignal cntl, cnt2: integer range 0 to N-1;-定义中间信号 beginprocess(clkin)beginif(clkinevent and clkin=1) then -上升沿计数 if(cnt1N-1) then cnt1 = cnt1+1;elsecnt1 = 0;end if;end if;end process;process(clkin)beginif(clkinevent and clkin=0) then -下降沿计数 if(cnt2N-1) then cnt2 = cnt2+1;elsecnt2