海思hi3536v100软硬件开发hi3536ddr channel capacity configuration description

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4、ranty of any kind, express or imp d.HiSiliconTechnologies.IndustrialBase Bantian, Longgang Shenzhen 518129 http:Ie00B01(2015-06-Hi3536DDRChannelCapacityConfiguration 1ChangingtheDDR1ChangingtheDDRC 1.1 describeshowtochangethecapacityofeachDDRchannelHi3536DDRChannelCapacityConfiguration 1ChangingtheD

5、DR1ChangingtheDDRC 1.1 describeshowtochangethecapacityofeachDDRchannelbyconfiguringcorrespondingDDRTheDDRhedefaultHi3536softwaredevelopmentkit(SDK)arebasedonthefollowingDDRFour16-bit4GbitsDDRSDRAMs(onthedemoEight8-bit4GbitsDDRSDRAMs(onthedemoplusIfyouwanttomodifytheDDRcapacity,followthehefollowingYo

6、uneedtopayattentiontothemodifiedhefollowingsections.Fordetailsaboutvaluesoftheunmodifi dbits,s e the heSDK.Youareadvisednottochangevaluesoftheunmodifiedbits.Fordetails,see thechaptersrelatedtotheDDR hechipTochangetheDDRcapacity,theregistersinbothsection1.1.1andsection1.1.2needtobe 1.1.1Configuringth

7、eCapacityoftheDDRSDRAMConnectedto Each ChannelTospeci ytherowaddress,columnaddress,b to con igure the following registers:addresswidth,anddatabitwidth,you Totalcapacity=2rowx2colxxDQForIe00B01(2015-06-3Hi3536DDRChannelCapacityConfiguration 1ChangingtheDDRIfchannel0connectstoa32-bit2GBDDR3SDRAM,the v

8、aluesof theregisterfieldsareas follows:mem_row= 101(16 bits), mem_col = 010(10 bits), mem_b =1 (23 = 8 b s). The DQ width is 32 bits.Therefore,thetotalcapacityis2GB(216x210 xHi3536DDRChannelCapacityConfiguration 1ChangingtheDDRIfchannel0connectstoa32-bit2GBDDR3SDRAM,the valuesof theregisterfieldsare

9、as follows:mem_row= 101(16 bits), mem_col = 010(10 bits), mem_b =1 (23 = 8 b s). The DQ width is 32 bits.Therefore,thetotalcapacityis2GB(216x210 x23x32bits=16Gbits).Thechannelb-column(RBC)isconfiguredasIfchannel1connectstoa32-bit1GBDDR3SDRAM,the th registerfieldsarefollows: mem_row = 100 (15 bits),

10、mem_col = 010 (10 bits), mem_b= 1 (23 = 8 bThe DQ width is 32 bits.Therefore,thetotalcapacityis1GB(215x210 x23 x32bits=8Gbits).T echannelRBCis configured as follows:1.1.2ConfiguringtheModeofAllStorageSpacesedbytheAddressSpaceVisibletoSoftwaretoTwoChannels theMDDRCUndertheDual-ChannelTomaptheaddresss

11、pacetotwochannels,performthefollowingDefinealltheaddressspacevisibletosoftwareassomeconsecutiveandnon-Step addressareas(ifthereisnolapplication).Specifythebaseaddress(startaddress)addressizeofeachaddressareabyconfiguringthefollowingAXI_REGION_MAP Specifythemodeofeachaddressarea.Tobespecific,specifyw

12、hetheranStep areaismappedtoonechannelorismappedtotwochannelsbasedongranularity Ifmultipleaddressareasaremappedtothesamechannel,theoffsetaddressestheaddressareasaftermap AXI_REGIN_ATTRIB-hechannelmustbespecifiedbyconfiguringtheForle,tsoftwarecansthestorageaddressspacerangingFtotis,3GBstoragespaceerna

13、l, memoryaddressheMDDRCrangesfrom_Ftochannel0connectstothe32-bit2GBDDRSDRAM,andchannel1connectstothe32-bit1 GB DDR SDRAM.OneconfigurationmethodisasDefinetheaddressspacerangingfrom_Fto0 x0000_0000astwoandnon-addressareas(atmost16addressareascanbe Ie00B01(2015-06-4Hi3536DDRChannelCapacityConfiguration

14、 1ChangingtheDDRTheaddressizeofarea0is2GB,itsbaseaddressis32h0000_0000.Area0mappedtochannelHi3536DDRChannelCapacityConfiguration 1ChangingtheDDRTheaddressizeofarea0is2GB,itsbaseaddressis32h0000_0000.Area0mappedtochannel0andchannel1erleavingmode.One1GBspaceofarea0mappedtothe lower1GBspace ofchannel0,

15、andthe other1GBspaceofarea0is mapped to the entire 1 GB space of channel 1.TheregisterconfigurationisasSetAXI_REGIOM_MAP_0rgn_ento1,AXI_REGIOM_MAP_0rgn_sizeto3h7(2 GB size), andAXI_REGIOM_MAP_0rgn_base_addrto8h00 (upper eightbits). The offset address of the AXI_REGIOM_MAP_0 register is 0 x100.SetAXI

16、_REGIOM_ATRIB_0ch_modeto2b10,ttheaddressarea mappedtotwochannels 2b00, tthedual-erleavingstartsfromchannel0.TheaddressoftheAXI_REGIOM_ATRIB_0registeris0 x104.ThenAXI_REGIOM_ATRIB_0ch_offsetto8h00becausetheaddressareaismappedtothe lower 1 GB space of channel 0.Theaddressizeofarea1is1GB,itsbaseaddress

17、is32h8000_0000.Area1mappedonlytotheupper1GBspaceofchannel TheregisterconfigurationisasSetAXI_REGIOM_MAP_1rgn_ento1,AXI_REGIOM_MAP_1rgn_sizeto3h6(1 GB size), andAXI_REGIOM_MAP_1rgn_base_addr to8h80 (upper eightbits). The offset address of the AXI_REGIOM_MAP_1 register is 0 x110.SetAXI_REGIOM_ATRIB_1c

18、h_modeto2b01,ttheaddressarea mappedonlytoonechannel;setAXI_REGIOM_ATRIB_1ch_startto2b01,indicating t the address area is mapped only to channel 0; setAXI_REGIOM_ATRIB_1ch offsetto8h40,ttheoffsetoftheareaaddressrelative tothe startaddressofchannel0is32h4000_0000.The offset address of the AXI_REGIOM_A

19、TRIB_1 register is 0 x1148.Figure1-1illustrateshowthememoryaddressspacerangingfrom0 xB 0 x0000_0000 is ma ped to two channelshe MDDRC._FIe00B01(2015-06-5Hi3536DDRChannelCapacityConfiguration 1ChangingtheDDRtwo channels _Thereareothermodes,whichwillnot.theAddressSpaceVisibletoSo twaretoHi3536DDRChannelCapacityConfiguration 1ChangingtheDDRtwo channels _Thereareothermodes,whichwillnot.theAddressSpaceVisibletoSo twar