TFT-LCD技术经典讲义

1、TFT-LCD技术经典讲义TFT-LCD技术经典讲义Outline TFT-LCD Introduction a-Si TFT Technology L-T Poly Si TFT Technology SummaryOutline TFT-LCD Introduction Classification TFT-LCD Scheme Basic Operation Principle Pixel Arrangement & ResolutionTFT-LCD Introduction Flat Panel Display ClassificationFPDsPDPsLEDsLCDsPassiv

2、eActiveMIMTFTa-Si:TFTLTPS TFTHTPS TFTTN、STN.etc.LCOS TFT-LCD IntroductionFlat Panel Display ClassificatTFT Classification TFT-LCD Introductiona-Si TFT Amorphous Silicon TFT LTPS TFT Low Temperature Poly- Silicon TFT HTPS TFT High Temperature Poly- Silicon TFT TFT Classification TFT-LCD InGeneration

3、TFT-LCD IntroductionGeneration 1Generation 2Generation 2.5Generation 3Generation 3.5300mm x 400mm8.4“10.4“370mm x 470mm10.4“12.1“550mm x 650mm12.1“13.3“15”650mm x 830mm15“12.1“Generation TFT-LCD IntroductiVideo DataTiming ControlPower Supply CircuitBack-LightLCD Timing ControllerGraphic Card SignalB

4、ack-Light Power SupplyData DriverScan DriverTFT-LCD SystemTFT-LCD Array TFT-LCD IntroductionVideo DataTiming Power Supply LTPS TFT-LCD SystemVideo DataTiming ControlPower Supply CircuitBack-LightLCD TimingControllerPC InterfaceBack-Light Power SupplyTFT-LCD ArrayData DriverScan DriverLTPS TFT-LCD Pa

5、nelI/O InterfaceI/O InterfaceX1X2X3072Y1Y2Y768Scan DriverData DriverBlock 1Block 2Block 3Block 4Glass SubstrateBufferLevel ShifterShift Register TFT-LCD IntroductionLTPS TFT-LCD SystemVideo DataTSpacerLCAlignment LayerTFT-Array SubstrateColor Filter SubstrateBlack MatrixColor Filter - Green PixelPol

6、arizerPolarizerPixel ElectrodeTFT TFT-LCD IntroductionTFT-LCD Cross Section View SpacerLCAlignment LayerTFT-ArrTFT-LCD Array with Circuit Board Data TABScan TABSignal ConnectorControl IC TFT-LCD IntroductionTFT-LCD Array with Circuit BoaPeripheral Driver IC & TAB Reduction(a)a-Si TFT Panel 10.4” SVG

7、A(b)LTPS TFT Panel 10.4” XGAOriginal Data ：成璟 Flat panel display 2000 TFT-LCD IntroductionPeripheral Driver IC & TAB RedBack-light ModulePrism lens sheetDiffuserLight Guide PlateCCFLReflection PlateLC cellLamp Cover TFT-LCD IntroductionBack-light ModulePrism lens shUltra-Slim LCD ModuleOrignal data:

8、SID 2000 SHORT COURSE S-2 TFT-LCD IntroductionUltra-Slim LCD ModuleOrignal dTFT Array PreviewS1S2S3SmSm-1D1D2D3Dn-1DnData LineCstGate LineClcTFTFrame TimeGate pulsewidth TFT-LCD IntroductionTFT Array PreviewS1S2S3SmSm-1DLCD OperationDrive VoltageTFT switchCommon electrodeITO PixelCapacitorLiquid cry

9、stalSignal electrode TFT-LCD IntroductionLCD OperationDrive VoltageTFT TN LC Operation ModePoloarizer-1Poloarizer-2LCBacklightE(b) Normally Black Operation(a) Normally White OperationEPoloarizer-1Poloarizer-2LCBacklight TFT-LCD IntroductionTN LC Operation ModePoloarizerLight Transmit through Liquid

10、Crystal考慮一線偏極光與vertical方向夾一角度通過在vertical方向折射率為ne在horizontal方向為no的物質。因垂直與水平方向折射率不同，所以線偏極光之垂直/水平二分量之行進速率將不同 (v =c/n)。故當光穿出此物質時，垂直與水平二分量的光會產生phase different (or phase shift)，導致出射光不再是一線偏極而為橢圓偏極光。 TFT-LCD IntroductionLight Transmit through Liquid 液晶分子由上至下旋轉90度當一平行第一層液晶分子長軸之線偏極光 由上入射，光通過第一層LC分子時因偏振方向與長軸平行

11、，所以沒有phase shift產生。當光通過第二層分子因與之夾一角度，所以產生了 phase shift。依此類推當光通過最底層分子時其phase different將達到90度(與LC分子扭轉角度相同)，且由原射之線偏極經橢圓偏極、圓偏極、橢圓偏極再變回線偏 TN (twisted nematic ) mode TFT-LCD IntroductionTN (twisted nematic ) mode TF橢圓偏極再變回線偏極。此時的線偏極方向與原來方向呈90度，與底層LC分子長軸平行。此現象稱為optical rotation 一般TN mode TFT LCD在上下板所貼的polar

12、izer呈垂直， 所以入射光經上板polarizer形成線偏極光再經過LC分子的optical rotation，出射光之偏振方向便與下板所貼之polarizer平行，形成LC transmittable state。TN (twisted nematic ) mode TFT-LCD Introduction橢圓偏極再變回線偏極。此時的線偏極方向與原來方向呈90度，T 施加電壓 當施加一電壓時，因dipole 在電場受轉矩之故，LC分子 會轉向呈垂直上下板排列。 當線偏極光由上入射，因偏 振方向與所有LC分子長軸垂 直，故無phase shift產生。入 射光通過LC後偏振方向不變。故出射光

13、無法通過下板偏極版 TFT-LCD IntroductionTN (twisted nematic ) mode 施加電壓 TFT-LCD IntroductioPixel Arrangement & ResolutionAV Equipment: Delta configuration-full colorOffice Equipment: Stripe configuration-sharp contrast TFT-LCD IntroductionPixel Arrangement & Resolution a-Si TFT Technologya-Si TFT Pixel Layout

14、 and Fabricationa-Si TFT Panel Designa-Si TFT Electrical Characteristics a-Si TFT TechnologyTFT Structure6-Mask BCE TFT-Array7-Mask CHP TFT-Array Reduce-Mask Process a-Si TFT pixel layout & fabrication a-Si TFT pixel layout & fabriTFT Structure Cross SectionBack Channel Etching (BCE)Channel-Passivat

15、ed (CHP)(a) Bottom Gate Structure(b) Bottom Gate Structure(c) Top Gate StructureStaggered-Electrode(1) 6-Mask a-Si TFT Process(2) SiNx/a-Si/N+ deposition continuously(1) 7-Mask a-Si TFT Process(2) SiNx channel etch stopper minimize a-Si thickness(1) 6-Mask a-Si TFT Process(2) N+ region define by dat

16、a bus line & islanda-Si TFT Technology TFT Structure Cross SectionBacBCE Fab. Process (Mask-1)MI sputteringScan line define (1st)SiNx/a-Si/N+ depositionIsland pattern (2nd)ITO sputteringPixel electrode pattern (3rd)Contact open (4th)MII sputteringData line define (5th)N+ a-Si etchingSiNx depositionP

17、assivation open (6th)TFTCsta-Si TFT Technology BCE Fab. Process (Mask-1)MI spBCE Fab. Process (Mask-2)TFTCstMI sputteringScan line define (1st)SiNx/a-Si/N+ depositionIsland pattern (2nd)ITO sputteringPixel electrode pattern (3rd)Contact open (4th)MII sputteringData line define (5th)N+ a-Si etchingSi

18、Nx depositionPassivation open (6th)a-Si TFT Technology BCE Fab. Process (Mask-2)TFTCsBCE Fab. Process (Mask-3)TFTCstMI sputteringScan line define (1st)SiNx/a-Si/N+ depositionIsland pattern (2nd)ITO sputteringPixel electrode pattern (3rd)Contact open (4th)MII sputteringData line define (5th)N+ a-Si e

19、tchingSiNx depositionPassivation open (6th)a-Si TFT Technology BCE Fab. Process (Mask-3)TFTCsBCE Fab. Process (Mask-5)TFTCstN+ etching backMI sputteringScan line define (1st)SiNx/a-Si/N+ depositionIsland pattern (2nd)ITO sputteringPixel electrode pattern (3rd)Contact open (4th)MII sputteringData lin

20、e define (5th)N+ a-Si etchingSiNx depositionPassivation open (6th)a-Si TFT Technology BCE Fab. Process (Mask-5)TFTCsBCE Fab. Process (Mask-6)TFTCstMI sputteringScan line define (1st)SiNx/a-Si/N+ depositionIsland pattern (2nd)ITO sputteringPixel electrode pattern (3rd)Contact open (4th)MII sputtering

21、Data line define (5th)N+ a-Si etchingSiNx depositionPassivation open (6th)a-Si TFT Technology BCE Fab. Process (Mask-6)TFTCsCHP Fab. Process (Mask-1)MI sputteringScan line define (1st)SiNx/a-Si/SiNx depositionEtch stopper pattern (2nd)N+ depositionIsland pattern (3rd)ITO sputteringPixel electrode pa

22、ttern (4rd)Contact open (5th)MII sputteringData line define (6th)N+ a-Si etchingSiNx depositionPassivation open (7th)TFTCsta-Si TFT Technology CHP Fab. Process (Mask-1)MI spCHP Fab. Process (Mask-2)MI sputteringScan line define (1st)SiNx/a-Si/SiNx depositionEtch stopper pattern (2nd)N+ depositionIsl

23、and pattern (3rd)ITO sputteringPixel electrode pattern (4rd)Contact open (5th)MII sputteringData line define (6th)N+ a-Si etchingSiNx depositionPassivation open (7th)TFTCsta-Si TFT Technology CHP Fab. Process (Mask-2)MI spCHP Fab. Process (Mask-3)MI sputteringScan line define (1st)SiNx/a-Si/SiNx dep

24、ositionEtch stopper pattern (2nd)N+ depositionIsland pattern (3rd)ITO sputteringPixel electrode pattern (4rd)Contact open (5th)MII sputteringData line define (6th)N+ a-Si etchingSiNx depositionPassivation open (7th)TFTCsta-Si TFT Technology CHP Fab. Process (Mask-3)MI spCHP Fab. Process (Mask-4)MI s

25、putteringScan line define (1st)SiNx/a-Si/SiNx depositionEtch stopper pattern (2nd)N+ depositionIsland pattern (3rd)ITO sputteringPixel electrode pattern (4rd)Contact open (5th)MII sputteringData line define (6th)N+ a-Si etchingSiNx depositionPassivation open (7th)TFTCsta-Si TFT Technology CHP Fab. P

26、rocess (Mask-4)MI spCHP Fab. Process (Mask-6)MI sputteringScan line define (1st)SiNx/a-Si/SiNx depositionEtch stopper pattern (2nd)N+ depositionIsland pattern (3rd)ITO sputteringPixel electrode pattern (4rd)Contact open (5th)MII sputteringData line define (6th)N+ a-Si etchingSiNx depositionPassivati

27、on open (7th)TFTCsta-Si TFT Technology CHP Fab. Process (Mask-6)MI spCHP Fab. Process (Mask-7)MI sputteringScan line define (1st)SiNx/a-Si/SiNx depositionEtch stopper pattern (2nd)N+ depositionIsland pattern (3rd)ITO sputteringPixel electrode pattern (4rd)Contact open (5th)MII sputteringData line de

28、fine (6th)N+ a-Si etchingSiNx depositionPassivation open (7th)TFTCsta-Si TFT Technology CHP Fab. Process (Mask-7)MI spTOP ITO Configurationa-Si TFT Technology TOP ITO Configurationa-Si TFT Reduce CHP Fab. ProcessMI sputteringScan line define (1st)SiNx/a-Si/SiNx depositionEtch stopper pattern (2nd)N+

29、 depositionMII sputteringData line define (3rd)SiNx depositionPassivation Open (4rd)ITO sputteringPixel Electrode pattern (5th)a-Si TFT Technology Reduce CHP Fab. ProcessMI sputReduce BCE Fab. ProcessMI sputteringScan line define (1st)SiNx/a-Si/N+ depositionMII sputteringData line & Island pattern (

30、2nd)O2 Plasma ashingSiNx depositionPassivation Open (3rd)ITO sputteringPixel Electrode pattern (4th)TFTCsta-Si TFT Technology Reduce BCE Fab. ProcessMI sputa-Si TFT Panel DesignPixel DesignCst DesignFeed-Through Effect & Scan Line Design Improvementa-Si TFT Panel DesignPixel Size & Aperture Ratio(a)

31、 Top view of one dot (three pixel)(a) Pixel Size DeterminationPanel SizeResolutionFor 12.1” SVGA (800 x 600)12.1 x 2.54 x 10 x (4 / 5) / 800 =0.307mm Dot Size：307m x 307mPixel Size：307m x 102.4m (b) Aperture RatioWhite Area (W)：Color Filter Black Area (B)：Black MatrixAperture ratio = W / (W + B) x 1

32、00%(b) Aperture ratioa-Si TFT Technology Pixel Size & Aperture Ratio(a)Process Margin123-b4-c4-a4-d4-b5-a5-b1：MI length min. 2：Island cover MI min. spacing3-a：ITO to N+ min spacing3-b：ITO to MI min spacing4-a：MII to MI cover length4-b：MII to ITO spacing4-c：Gate length4-d：MII cover Island min. spacin

33、g5-a：Passivation to ITO min. spacing5-b：Passivation to MII min. spacing# Cd loss caused by photo & etchingprocess should be compensated.3-aa-Si TFT Technology Process Margin123-b4-c4-a4-d4-Cst on common & Cst on gate (a) Cst on common configuration (b) Cst on gate configurationa-Si TFT Technology Cs

34、t on common & Cst on gate (Feed-Through EffectVn = VnVs = VsCgsCstClcnCommonVnVVdVs&a-Si TFT Technology Feed-Through EffectVn = VnVsScan Line DelayFor 1st data line：For N-th data line： Suppose Vs - Vs = 0.4Vp-pa-Si TFT Technology Scan Line DelayFor 1st data liHigh aperture ratio designBCB passivatio

35、n layer process 方法：用BCB代替傳統之SiOx 或SiNx當做護 層材料優點：降低ITO與MII（data line)間的寄生電 容 、增加開口率a-Si TFT Technology High aperture ratio designa-SiHigh aperture ratio designa-Si TFT Technology High aperture ratio designa-SiHigh aperture ratio design From IDMC 2000a-Si TFT Technology High aperture ratio design High

36、 aperture ratio designBCB gate metal planarization 方法：用BCB當作Gate line平坦化層 優點：增加開口率、降低Gate line阻值,解決 gate delay的問題 a-Si TFT Technology High aperture ratio designa-SiHigh aperture ratio designa-Si TFT Technology High aperture ratio designa-SiBCB Planarization LayerBCB1m Al-Nda-Si TFT Technology BCB Pl

37、anarization LayerBCB1m ITO Define Cst (a) AR increase by ITO Cst (b) Conventional MI Cst a-Si TFT Technology ITO Define Cst (a) AR increaseRing Shape Cst Aperture ratioAperture ratioRing CstBlack Matrixa-Si TFT Technology Ring Shape Cst Aperture ratioARepair Lines & Ladder Scan Line TAB ChipArray Ar

38、eaRepair LinesLaser RepairScan Line OpenInterlayer ShortShort after Repaira-Si TFT Technology Repair Lines & Ladder Scan LinColor Filter on TFTa-Si TFT Technology From SID 01Color Filter on TFTa-Si TFT TeArray on Color Filtera-Si TFT Technology From SID 01Array on Color Filtera-Si TFTESD Protection

39、Common LineDiode Connect TFTBus Line Shorting BarTAB Pada-Si TFT Technology ESD Protection Common LineDioda-Si TFT Electrical Characteristics a-Si:H TFT Characteristics Threshold Voltage - Vth Mobility - Subthreshold Swing- SS Linearitya-Si TFT Electrical Characteria-Si:H Compositionc-Sia-Sia-Si:H0.

40、1a-Si:H0.6a-Si TFT Technology a-Si:H Compositionc-Sia-Sia-Sia-Si:H Basic Concept2.353.84a-Si TFT Technology a-Si:H Basic Concept2.353.8TFT Operation & Typical Id-VgVgs Vth Channel InducedVds = Vds-saturation = Vgs - Vth Saturation Region：a-Si TFT Technology TFT Operation & Typical Id-VgVTypical a-Si

41、 & p-Si TFT Id-Vga-Si TFT Technology Typical a-Si & p-Si TFT Id-VgaVth - Constant Current MethodVth = Vfb + 2f+Qd / Cin Vfb = ms-(Qss) / CinVfb ：flat band voltage ms：work function Qss：surface states2f ：strong inversion voltageQd：depletion region space chargeCin：gate insulator capacitanceConstant Cur

42、rent Define：Vd = 0.1VVth = 1.0V a-Si TFT Technology Vth - Constant Current MethodVVth - Extrapolation MethodSaturation Region：Vds = 10VVgs VthVds = Vds-saturation = Vgs - VthVth = 1.0Va-Si TFT Technology Vth - Extrapolation MethodSatu - Mobilitya-Si TFT Technology - Mobilitya-Si TFT TechnologSS - Su

43、bthreshold Swinga-Si TFT Technology SS - Subthreshold Swinga-Si TFLinearitya-Si TFT Technology Linearitya-Si TFT Technology Gate Bias Stressa-Si TFT Technology Gate Bias Stressa-Si TFT TechnLow Temperature Poly-Si TFT TechnologyLTPS TFT introductiona-Si Vs L-T Poly Si TFTKey Technology of LTPS TFTLo

44、w Temperature Poly-Si TFT TeDifferent Crystalline SiliconSummary From SID 01Different Crystalline SiliconSLTPS TFT Technology LTPS TFT structure 比較LTPS TFT Technology LTPS TFT sTop-Gate LTPS TFT ProcessLTPS TFT Technology From SID 01Top-Gate LTPS TFT ProcessLTPS Leakage Current Suppression Structure

45、LTPS TFT Technology From SID 01Leakage Current Suppression Sta-Si TFT Vs LTPS TFTLTPS TFT Technology a-Si TFT Vs LTPS TFTLTPS TFT TKey Technology of LTPS TFTLTPS TFT Technology Buffer layer depositiona-Si depositionCrystallizationGate insulatorIon dopingIon activationKey Technology of LTPS TFTLTPSSP

46、C ( Solid Phase Crystallization )MIC/MILC (Metal Induced Lateral Crystallization)ELC (Excimer Laser Crystallization ) CGS (Continuous Grain Silicon)CrystallizationLTPS TFT Technology CrystallizationLTPS TFT TechnoEnergy Density & Grain SizeLTPS TFT Technology Energy Density & Grain SizeLTPFrom SID 9

47、9Grain Size & MobilityLTPS TFT Technology From SID 99Grain Size & MobiliFrom SID 01Grain Size & Number of ShotsLTPS TFT Technology From SID 01Grain Size & NumberSequential Lateral Solidification-SLSLTPS TFT Technology From SID 01Sequential Lateral SolidificatELA CrystallizationLTPS TFT Technology Fr

48、om SID 01ELA CrystallizationLTPS TFT TePhase Modulated ELA (PMELA)LTPS TFT Technology From SID 01Phase Modulated ELA (PMELA)LTPSummary Cost Down High Image Quality Enlarge Panel Size Compact SummaryCost DownImprove YieldDesignNew Material & TechnologyProcessReduce Mask NumberFully Dry Etching ProcessSummary Cost DownImprove YieldSummary High Image QualityHigh Re