超大CMOS集成电路原理chapter2

1、Digital Integrated CircuitsA Design PerspectiveManufacturingProcessJan M. RabaeyAnantha ChandrakasanBorivoje Nikolic1CMOS Process2A Modern CMOS ProcessDual-Well Trench-Isolated CMOS Process3Circuit Under Design4Its Layout View5The Manufacturing ProcessFor a great tour through the IC manufacturing pr

2、ocess and its different steps, check6oxidationopticalmaskprocessstepphotoresist coatingphotoresistremoval (ashing)spin, rinse, dryacid etchphotoresist stepper exposuredevelopmentTypical operations in a single photolithographic cycle (from Fullman).Photo-Lithographic Process7Patterning of SiO2Si-subs

3、trateSi-substrateSi-substrate(a) Silicon base material(b) After oxidation and depositionof negative photoresist(c) Stepper exposurePhotoresistSiO2UV-lightPatternedoptical maskExposed resistSiO2Si-substrateSi-substrateSi-substrateSiO2SiO2(d) After development and etching of resist,chemical or plasma

4、etch of SiO2(e) After etching(f) Final result after removal of resistHardened resistHardened resistChemical or plasmaetch8CMOS Process at a GlanceDefine active areasEtch and fill trenchesImplant well regionsDeposit and patternpolysilicon layerImplant source and drainregions and substrate contactsCre

5、ate contact and via windowsDeposit and pattern metal layers9CMOS Process Walk-Throughp+p-epi(a) Base material: p+ substrate with p-epi layerp+(c) After plasma etch of insulatingtrenches using the inverse of the active area maskp+p-epiSiO23SiN4(b) After deposition of gate-oxide andsacrificial nitride

6、 (acts as abuffer layer)10CMOS Process Walk-ThroughSiO2(d) After trench filling, CMP planarization, and removal of sacrificial nitride(e) After n-well and VTp adjust implantsn(f) After p-well andVTn adjust implantsp11CMOS Process Walk-Through(g) Afterpolysilicon depositionand etchpoly(silicon)(h) Af

7、ter n+ source/drain andp+ source/drain implants. Thesep+n+steps also dope the polysilicon.(i) After deposition of SiO2insulator and contact hole etch.SiO212CMOS Process Walk-Through(j) After deposition and patterning of first Al layer.Al(k) After deposition of SiO2insulator, etching of vias,depositi

8、on and patterning ofsecond layer of Al.AlSiO213Advanced Metallization14Advanced Metallization15Design Rules163D PerspectivePolysiliconAluminum17Design RulesInterface between designer and process engineerGuidelines for constructing process masksUnit dimension: Minimum line widthscalable design rules:

9、 lambda parameterabsolute dimensions (micron rules)18CMOS Process LayersLayerPolysiliconMetal1Metal2Contact To PolyContact To DiffusionViaWell (p,n)Active Area (n+,p+)ColorRepresentationYellowGreenRedBlueMagentaBlackBlackBlackSelect (p+,n+)Green19Layers in 0.25 mm CMOS process20Intra-Layer Design Ru

10、lesMetal24321Transistor Layout22Vias and Contacts23Select Layer24CMOS Inverter Layout25Layout Editor26Design Rule Checkerpoly_not_fet to all_diff minimum spacing = 0.14 um.27Sticks Diagram13InOutVDDGNDStick diagram of inverter Dimensionless layout entities Only topology is important Final layout generated by “compaction” program28Packaging29Packaging RequirementsElectrical: Low parasiticsMechanical: Reliable and robustThermal: Efficient heat removalEconomic