2014下-自动化数字逻辑设计课件1第五章

1、Chapter 5Combinational Logic Design PracticesDigital Design Pinciples and PracticesDigital Design Pinciples and PracticesEncoder Binary EncoderThe simplest encoder is 2n-to-n encoder.ApplicationEncoder Binary EncoderHow to design an 8-to-3 Encoder?8-to-3 Encoder Y0Y1Y2I0I1I2I3I4I5I6I7Y2 Y1 Y0Dont ne

2、ed the True TableY0 = I1 + I3 + I5 + I7x x 1x 1 x1 x xY1 = I2 + I3 + I6 + I7Y2 = I4 + I5 + I6 + I7DefaultA 2n-to-n encoder can be built from n 2n-1-input OR gatesEncoder Binary EncoderProblemI7 I6 I5 I4 I3 I2 I1 I0Y2 Y1 Y00008-to-3 Encoder Y0Y1Y2I0I1I2I3I4I5I6I7111Wrong!Only one Inputcan be asserted

3、 at a time !I0 Inputs or No Input ?7#6#5#EncoderHow to solve the problem ? Priority EncoderWhat is Priority ?让列宁同志先走Encoder Priority EncoderBe asserted if no inputsThe highest priorityDefine 8 intermediate variables. Hi means Ii is active.H7 = I7H6 = I6 I7H5 = I5 I6 I7H4 = I4 I5 I6 I7H3 = I3 I4 I5 I

4、6 I7H2 = I2 I3 I4 I5 I6 I7H1 = I1 I2 I3 I4 I5 I6 I7H0 = I0 I1 I2 I3 I4 I5 I6 I7A0 = H1 + H3 + H5 + H7A1 = H2 + H3 + H6 + H7A2 = H4 + H5 + H6 + H7IDLE = (I0 + I1 + I2 + I3 + I4 + I5 + I6 + I7)= I0 I1 I2 I3 I4 I5 I6 I7H5H4H3H2H1H6H7H0Design Example( 高位优先原则 )Encoder The 74x148 Priority EncoderEnable In

5、putGroup SelectEnable OutputFor cascading purposeTrue TableInstead of IDLEWhen /EI is asserted/GS = /EO/EO有效：表示在 /EI 有效下，不存在有效的输入。/GS有效：表示在 /EI 有效下，存在有效的输入 。/X means Active LowLogic Diagram for 74x148Priority EncoderEncoder The 74x148 Priority EncoderExample: Design a 16-to-4 Priority Encoder with 7

6、4x148s .InputY3Y2Y1Y0I15_L1111I15_LI14_LI13_LI12_LI11_LI10_LI9_LI8_LI7_LI6_LI5_LI4_LI3_LI2_LI1_LI0_LY3Y2Y1Y0U2U1A2_LA1_LA0_L000001I14_L1110010I13_L1101011I12_L1100100I11_L1011101I10_L1010110I9_L1001111I8_L1000000I7_L0111001I6_L0110010I5_L0101011I4_L0100100I3_L0011101I2_L0010110I1_L0001111I0_L0000U2U

7、1GSEI_LRed: Asserted (有效)Blue: Deasserted (无效) Outputs are Active HighVccEOCan connect GS_U1 to Y3?No. Cannt distinguish U1 has no input or U1 is disabled.Encoder The 74x148 Priority EncoderY2 Y1 Y0I0 I7I8 I15Y30Y400Y5111U1U2I16 I23I24 I3101U3U4I32 I39I40 I47I48 I55I56 I63010101U5U6U7U8Y3GSU2Y0Y1Y2A

8、0A1A2U1U1U1U2U2U2Y4GSU3U3U3U3U4U4U4U4U4Y5GSU5U6U7U8U7U8U6U8U5U6U7U8U5U6U7U8U5U6U7U8 8-to-3 EncodingCan be replaced by a 74x148 GS_U8GS_U7GS_U6GS_U5GS_U4GS_U3GS_U2GS_U1Y5Y4Y3How to design a 2n-to-n Encoder with 74x148s ? Encoder The 74x148 Priority EncoderExercise分析判定下面的优先级电路： 8个输入I0_LI7_L 为_电平有效，_的优

9、先级最高 地址输出A2A0为_电平有效 若输出VALID为高电平有效， 则表示 _A2A1A0GSEOEI74x148I7I0I0_LI7_LA2A1A0VALID低I0_L至少有一个输入有效高（参见表6-27）Three-State Devices Three-State Buffer/Driver The most basic Three States DeviceThree States: High (高电平), Low (低电平), Hi-Z (高阻态）InputOutputEnableVCCTpTnInputEnableOutputThree-State BufferThree-St

10、ate Devices Three-State Buffer/Driver The most basic Three States DeviceThree States: High (高电平), Low (低电平), Hi-Z (高阻态）InputOutputEnableVCCInputEnableOutputThree-State BufferAnother circuit structure of the same logic symbolThree-State Devices Three-State Buffer/Driver The most basic Three States De

11、viceThree States: High (高电平), Low (低电平), Hi-Z (高阻态）InputOutputEnableVCCInputEnableOutputThree-State Buffer?Whats the logic symbol of this one?Three-State Devices Three-State Buffer/Driver The most basic Three States DeviceThree States: High (高电平), Low (低电平), Hi-Z (高阻态）InputOutputEnableVCCInputEnable

12、OutputThree-State Buffer?Whats the logic symbol of this one?Three-State Devices Three-State Buffer/Driver The most basic Three States DeviceThree States: High (高电平), Low (低电平), Hi-Z (高阻态）InputOutputEnableVCCInputEnableOutputThree-State BufferWhats the logic symbol of this one?Three-State Devices Thr

13、ee-State Buffer/Driver The most basic Three States DeviceThree States: High (高电平), Low (低电平), Hi-Z (高阻态）There are four kinds of Three-State BufferThree-State Devices Three-State Buffer/Driver Multiple Three-State Devices can drive one signal line (Party Line, 同线) But only one device “talk” on the li

14、ne at a time.How to guarantee?Decoder !Party LineThree-State Devices Three-State Buffer/Driver 进入高阻的时间tpLZ /tpHZ 一般快于脱离高阻的时间tpZL/tpZH 但由于各三态门使能信号延迟和工作速度的快慢，仍可能冲突(Fighting) EN1EN2_L, EN3_LMax ( tpLZmax, tpHZmax )Min ( tpZLmin, tpZHmin )SSRC2:001237SDATAPQRSWDead time (截止时间) can avoid FightingWhy?“非高非

15、低”表示高阻状态可利用74x138的使能端进行时序控制来避免冲突Three-State Devices Standard SSI and MSI Three-State Buffer 74x541 Octal Three-State BufferSchmitt-Trigger BufferTo improve noise immunityWhy two? Three-State Devices Standard SSI and MSI Three-State Buffer Application of 74x541Three-State Devices Standard SSI and MSI

16、 Three-State Buffer Transfer Data in Either DirectionsABDIRDIREN_L（实现数据双向传输）Three-State Devices Standard SSI and MSI Three-State Buffer 74x245 Bus TransceiverThree-State Devices Standard SSI and MSI Three-State Buffer Application of 74x245Bus ABus B74x245ControlCircuitsMultiplexerDigital Switch, Mul

17、ti-Switch, Data Selector (又称数据开关、多路开关、数据选择器) 缩写：MUXUnder select controlling signals, select one of the multi-inputs to the output(在选择控制信号的作用下，从多个输入数据中选择其中一个作为输出)MultiplexerENSELD0Dn-1YEnableSelect Inputsn个1位数据源数据输出（1位）sENSELD0Dn-1YEnableSelectn个b位数据源数据输出（b位）bbsbs = log2 nn-Input, b-bit Multiplexern输

18、入b位多路复用器 mi is the Minterm of Select Inputs ? MultiplexerSD0D1Y2x1 MUX4x1 MUXS0D0D1D2D3S1Y2-to-4 Decoder Whats it?Multiplexer Standard MSI Multiplexers74x151EN_L C B A Y Y_L 1 X X X0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 1 0 1D0 D0D1 D1D2 D2D3 D3D4 D4D5 D5D6 D6D7 D7Truth Table 8输入1位多路

19、复用器 Select InputsData InputsEnableMultiplexer Standard MSI Multiplexers74x151EN_L C B A Y Y_L1 X X X0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 1 0 1D0 D0D1 D1D2 D2D3 D3D4 D4D5 D5D6 D6D7 D7Truth Table 8输入1位多路复用器 3-to-8 Decoder Whats it?Multiplexer Standard MSI Multiplexers74x157 2输入4位多路复用

20、器 Truth TableG_L S1 X0 00 1 0 0 0 01A 2A 3A 4A1B 2B 3B 4B1Y 2Y 3Y 4YSelect InputEnableMultiplexer Standard MSI Multiplexers74x157Truth TableG_L S1 X0 00 1 0 0 0 01A 2A 3A 4A1B 2B 3B 4B1Y 2Y 3Y 4Y 2输入4位多路复用器 Multiplexer Standard MSI Multiplexers74x153 4输入2位多路复用器 Truth Table1G_L 2G_L B A 1Y 2Y1 1 X X0

21、 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 1 0 01C0 2C01C1 2C11C2 2C21C3 2C31C0 01C1 01C2 01C3 0 0 2C0 0 2C1 0 2C2 0 2C3Select InputsEnableEnableMultiplexer Expanding MultiplexersExpanding Bits (位数扩展) How to design an 8-Input, 16-bit multiplexer?From 8-Input, 1

22、-bit to 8-Input, 16-bit (由8输入1位8输入16位)Need 16 74x151s. Each chip process 1-bit of 8 Inputs. (需要16片74x151，每片处理8组输入中的某1位)Select-Inputs connect to C,B,A of each chip (选择端连接到每片的C,B,A)Note: the fanout ability of select field (注意：选择端的扇出能力，需要驱动16个负载） ENYYABCD0D774x151Multiplexer Expanding MultiplexersExpan

23、ding Inputs (输入数扩展) How to design a 32-Input, 1-bit multiplexer?From 8 Inputs to 32 Inputs. Need 4 chips of 74x151 and 5 Select Inputs. (由8输入32输入，需4片74x151和5个选择输入端)How to control Select Inputs? (如何控制选择输入端?) By High bits plus Low bits. (分为高位低位)Low 3 bits connect to C,B,A of each chip. (低位接到每片的C,B,A)H

24、igh 2 bits enable one of 4 chips. (高2位用于使能4片中的某一片)Need a 2-to4 Decoder. (需要1片2-4译码器)Outputs connect to a OR Gate (4片的输出用或门连接) Refer to Figure 6-62Multiplexer Application of MultiplexersDesign an 8-to-1 Multiplexer with a Dual 4-to-1 Multiplexer(74x153)(用一片双4选1多路复用器(74x153)构成一个8选1多路复用器) D0D1D2D3D4D5D

25、6D7YA0A1A2ExerciseMultiplexer Application of Multiplexers用多路复用器设计组合逻辑电路 Realize F = A,B,C (0,1,3,7) with 74x151ENABCD0D1D2D3D4D5D6D7YY74x151当使能端有效时， 最小项之和的形式 mi is the Minterm of Select InputsCBAVCCFMultiplexer Application of MultiplexersExerciseRealize F = A,B,C (0,1,3,7) with 74x151ENABCD0D1D2D3D4

26、D5D6D7YY74x151CBAVCCFMultiplexer Application of MultiplexersExampleHow to realize F = W,X,Y,Z (0,1,3,7,9,13,14) with 74x151?降维：由4维 3维 !But there are only 3 Select Inputs of 74x151!Can use Shannons expansion theorems ( 香农展开定理 )How to doMultiplexer Application of MultiplexersExample填卡诺图F = ZF(W,X,Y,1) + ZF(W,X,Y,0)YWX00 01 11 100110ZZZZZ0F(W,X,Y,1) = F(W,X,Y,0) = 0, 填0 F(W,X,Y,1) = F(W,X,Y,0) = 1, 填1 F(W,X,Y,1)=1, F(W,X,Y,0)=0, 填Z F(W,X,Y,1)=0, F(W,X,Y,0)=1, 填Z YZWX00 01