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1、1Digital Logic Design and ApplicationJin YanhuaLecture #12Hardware Description LanguagesDocumentation Standard and Circuit TimingUESTC, Spring 2014Jin. UESTC2Real-World Logic DesignLots more than 6 inputs - cant use Karnaugh mapsDesign correctness more important than gate minimizationUse programs to

2、 manipulate logic expressions and minimize logic.Programmable Logic DevicesPALASM, ABEL, CUPL - developed for PLDsVHDL, Verilog - developed for ASICs6.3.1 PLA, programmable logic arrayJin. UESTC3Jin. UESTC4the number of inputs (n)the number of outputs (m)the number of product terms (p)Signetics 82S1

3、00, 16 inputs, 48 AND gates, 8 outputs.2*16*48=1536 fuses in the AND array, 8*48=384 in the OR arrayA 43 PLA with six product terms6.3.2 Programmable Array Logic DeviceJin. UESTC5Fixed OR arrayindividual three-state output enable signalSix I/O pinsLogic diagram of the PAL 16L86.3.3 Generic Array Log

4、ic DevicesJin. UESTC6Jin. UESTC7prime-number detector N3N0 N3N2N1N2N1N0N2N1N0Jin. UESTC8Chapter 5 Hardware Description LanguagesprimenumberdetectorN3N2N1N0Fdeclarationsstatements N3N0 N3N2N1N2N1N0N2N1N0moduleJin. UESTC9Chapter 5 Hardware Description LanguagesprimenumberdetectorN3N2N1N0Fdeclarationss

5、tatementsmodule primed (N3, N2, N1, N0, F);input N3, N2, N1, N0;output F; /structure description;endmodule;moduleJin. UESTC10Two kinds of signal : port : input and output; wire : any connect nets in module;The value of signals: 0 1 z xportwire N3N0 N3N2N1N2N1N0N2N1N0Jin. UESTC11Structural Design Ele

6、mentUse built-in gates for designJin. UESTC12Gate-levelw1w2w3w4module primed (N3, N2, N1, N0, F);input N3, N2, N1, N0;output F;wire notN3, notN2, notN1, w1, w2, w3, w4; not u1 (notN3, N3); not u2 (notN2, N2); not u3 (notN1, N1); and u4 (w1, notN3, N0); and u5 (w2, notN3, notN2, N1); and u6 (w3, notN

7、2, N1, N0); and u7 (w4, N2, notN1, N0); or u8 (F, w1, w2, w3, w4);endmodule;notN3notN2notN1Jin. UESTC13Dataflow Design Elementsw1w2w3w4module primed (N3, N2, N1, N0, F);input N3, N2, N1, N0;output F;wire w1, w2, w3, w4; assign w1= N3 & N0; assign w2 = N3 & N2 & N1; assign w3 = N2 & N1 & N0; assign w

8、4 = N2 & N1 & N0; assign F = w1 | w2 | w3 | w4;endmodule;assign F = (N3 & N0) | (N3 & N2 & N1) | (N2&N1&N0) | (N2&N1&N0);Hardware module: Name, Port and structureJin. UESTC14Behavioral Design Elementsmodule primed (N, F);input 3:0 N;output F;reg F; always (N) case (N) 1,2,3,5,7,11,13 : F=1; default

9、: F=0; end caseendmodule;15:0 N; always (N) if (N=1) F=1; else if ( (N%2) = 0) begin if (N=2) F=1; else F=0; end else if ( N=7) F=1; else if ( (N=11) | (N=13) ) F=1; else F=0;endmodule;15Chapter 6 Combinational Logic Design PracticesHow to conceive a complex system? structured thinkingSome useful co

10、mbinational componentsJin. UESTC166.1 Documentation StandardA documentation package contain the following items:Specification: description of interface and functionBlock diagram: systems major function module and their basic interconnections Schematic diagram （P360 Figure 6-17）Timing diagram （P363 F

11、igure 6-19）Structured logic device descriptionCircuit description: explains how the circuit works internallyJin. UESTC17schematic diagramJin. UESTC181. Block DiagramsA block diagram shows the inputs, outputs, functional modules, internal data paths, and important control signals of a system.P345 Fig

12、ure 6-1Jin. UESTC192. Gate SymbolsJin. UESTC20Equivalent Gate Symbols underthe Generalized Demorgans TheoreminverterbufferAND NAND NOR OR OR NOR NAND AND Jin. UESTC213. Active Levelsactive levelactive high and active lowasserted: a signal is at its active levelnegated / deasserted: signal is not at

13、its active level signal nameActive levels for pinsLogic Functions are performed inside the symbolic outlines.READYREQUESTGOREADY_LREQUEST_LGO_LIndicate an Active-Low PinJin. UESTC22Example: active levelsABFActive state: switchoff, lamplightA B F0 0 00 1 01 0 01 1 1Switch: 1off Lamp: 1light ABFSwitch

14、: 0off Lamp: 0light A B F0 0 00 1 11 0 11 1 1ABFF = A + B = ( A B )AND: the output is asserted if and only if all its inputs are asserted.Jin. UESTC23Example: active levelsABFActive state: switchoff, lamplightAND: the output is asserted if and only if all its inputs are asserted.ABFABFInversion bubb

15、le active-low pin normal gates Nonnormal gats Logic Functions are performed inside the symbolic outlines.Jin. UESTC247. Drawing Layoutflat schematic structureJin. UESTC25HierarchicalschematicstructureJin. UESTC266.2 Circuit Timingpropagation delay Timing analysis: worst-case delayMaximum delay Typic

16、al delay Minimum delay080804323232P366 Table 6-215202222tpHL and tpLH may be differentJin. UESTC27timing diagramGOREADYDATtDATtDATGOREADYDATtRDYtRDYCausality and Propagation DelayJin. UESTC28timing diagramGOREADYDATGOREADYDATtRDYmintRDYmaxMinimum and maximum delaysJin. UESTC29Some Useful Combinational ComponentsDecoders（译码器）Encoders（编码器）Three-State Devices（三态器件）Multiplexers（多路复用器）Parity Circuits（奇偶校验电路）Comparators（比较器）Adders（加法器）Jin. UESTC30Decoder and EncoderDecoderNormal